XHCI: Separate PORT and CAPs macros into dedicated file
Split the PORT and CAPs macro definitions into a separate file to facilitate sharing with other files without the need to include the entire xhci.h. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240124152525.3910311-2-Frank.Li@nxp.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Frank Li
Greg Kroah-Hartman
parent
983d23e293
commit
c35ba0ac48
85
drivers/usb/host/xhci-caps.h
Normal file
85
drivers/usb/host/xhci-caps.h
Normal file
@ -0,0 +1,85 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* hc_capbase bitmasks */
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/* bits 7:0 - how long is the Capabilities register */
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#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
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/* bits 31:16 */
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#define HC_VERSION(p) (((p) >> 16) & 0xffff)
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/* HCSPARAMS1 - hcs_params1 - bitmasks */
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/* bits 0:7, Max Device Slots */
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#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
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#define HCS_SLOTS_MASK 0xff
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/* bits 8:18, Max Interrupters */
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#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
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/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
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#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
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/* HCSPARAMS2 - hcs_params2 - bitmasks */
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/* bits 0:3, frames or uframes that SW needs to queue transactions
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* ahead of the HW to meet periodic deadlines */
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#define HCS_IST(p) (((p) >> 0) & 0xf)
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/* bits 4:7, max number of Event Ring segments */
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#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
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/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
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/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
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/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
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#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
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/* HCSPARAMS3 - hcs_params3 - bitmasks */
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/* bits 0:7, Max U1 to U0 latency for the roothub ports */
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#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
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/* bits 16:31, Max U2 to U0 latency for the roothub ports */
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#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
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/* HCCPARAMS - hcc_params - bitmasks */
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/* true: HC can use 64-bit address pointers */
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#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
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/* true: HC can do bandwidth negotiation */
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#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
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/* true: HC uses 64-byte Device Context structures
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* FIXME 64-byte context structures aren't supported yet.
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*/
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#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
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/* true: HC has port power switches */
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#define HCC_PPC(p) ((p) & (1 << 3))
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/* true: HC has port indicators */
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#define HCS_INDICATOR(p) ((p) & (1 << 4))
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/* true: HC has Light HC Reset Capability */
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#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
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/* true: HC supports latency tolerance messaging */
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#define HCC_LTC(p) ((p) & (1 << 6))
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/* true: no secondary Stream ID Support */
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#define HCC_NSS(p) ((p) & (1 << 7))
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/* true: HC supports Stopped - Short Packet */
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#define HCC_SPC(p) ((p) & (1 << 9))
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/* true: HC has Contiguous Frame ID Capability */
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#define HCC_CFC(p) ((p) & (1 << 11))
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/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
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#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
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/* Extended Capabilities pointer from PCI base - section 5.3.6 */
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#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
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#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
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/* db_off bitmask - bits 0:1 reserved */
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#define DBOFF_MASK (~0x3)
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/* run_regs_off bitmask - bits 0:4 reserved */
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#define RTSOFF_MASK (~0x1f)
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/* HCCPARAMS2 - hcc_params2 - bitmasks */
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/* true: HC supports U3 entry Capability */
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#define HCC2_U3C(p) ((p) & (1 << 0))
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/* true: HC supports Configure endpoint command Max exit latency too large */
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#define HCC2_CMC(p) ((p) & (1 << 1))
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/* true: HC supports Force Save context Capability */
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#define HCC2_FSC(p) ((p) & (1 << 2))
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/* true: HC supports Compliance Transition Capability */
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#define HCC2_CTC(p) ((p) & (1 << 3))
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/* true: HC support Large ESIT payload Capability > 48k */
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#define HCC2_LEC(p) ((p) & (1 << 4))
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/* true: HC support Configuration Information Capability */
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#define HCC2_CIC(p) ((p) & (1 << 5))
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/* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
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#define HCC2_ETC(p) ((p) & (1 << 6))
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176
drivers/usb/host/xhci-port.h
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176
drivers/usb/host/xhci-port.h
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@ -0,0 +1,176 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
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/* true: device connected */
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#define PORT_CONNECT (1 << 0)
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/* true: port enabled */
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#define PORT_PE (1 << 1)
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/* bit 2 reserved and zeroed */
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/* true: port has an over-current condition */
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#define PORT_OC (1 << 3)
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/* true: port reset signaling asserted */
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#define PORT_RESET (1 << 4)
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/* Port Link State - bits 5:8
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* A read gives the current link PM state of the port,
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* a write with Link State Write Strobe set sets the link state.
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*/
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#define PORT_PLS_MASK (0xf << 5)
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#define XDEV_U0 (0x0 << 5)
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#define XDEV_U1 (0x1 << 5)
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#define XDEV_U2 (0x2 << 5)
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#define XDEV_U3 (0x3 << 5)
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#define XDEV_DISABLED (0x4 << 5)
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#define XDEV_RXDETECT (0x5 << 5)
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#define XDEV_INACTIVE (0x6 << 5)
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#define XDEV_POLLING (0x7 << 5)
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#define XDEV_RECOVERY (0x8 << 5)
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#define XDEV_HOT_RESET (0x9 << 5)
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#define XDEV_COMP_MODE (0xa << 5)
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#define XDEV_TEST_MODE (0xb << 5)
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#define XDEV_RESUME (0xf << 5)
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/* true: port has power (see HCC_PPC) */
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#define PORT_POWER (1 << 9)
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/* bits 10:13 indicate device speed:
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* 0 - undefined speed - port hasn't be initialized by a reset yet
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* 1 - full speed
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* 2 - low speed
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* 3 - high speed
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* 4 - super speed
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* 5-15 reserved
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*/
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#define DEV_SPEED_MASK (0xf << 10)
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#define XDEV_FS (0x1 << 10)
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#define XDEV_LS (0x2 << 10)
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#define XDEV_HS (0x3 << 10)
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#define XDEV_SS (0x4 << 10)
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#define XDEV_SSP (0x5 << 10)
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#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
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#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
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#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
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#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
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#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
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#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
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#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
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#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
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/* Bits 20:23 in the Slot Context are the speed for the device */
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#define SLOT_SPEED_FS (XDEV_FS << 10)
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#define SLOT_SPEED_LS (XDEV_LS << 10)
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#define SLOT_SPEED_HS (XDEV_HS << 10)
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#define SLOT_SPEED_SS (XDEV_SS << 10)
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#define SLOT_SPEED_SSP (XDEV_SSP << 10)
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/* Port Indicator Control */
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#define PORT_LED_OFF (0 << 14)
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#define PORT_LED_AMBER (1 << 14)
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#define PORT_LED_GREEN (2 << 14)
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#define PORT_LED_MASK (3 << 14)
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/* Port Link State Write Strobe - set this when changing link state */
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#define PORT_LINK_STROBE (1 << 16)
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/* true: connect status change */
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#define PORT_CSC (1 << 17)
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/* true: port enable change */
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#define PORT_PEC (1 << 18)
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/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
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* into an enabled state, and the device into the default state. A "warm" reset
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* also resets the link, forcing the device through the link training sequence.
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* SW can also look at the Port Reset register to see when warm reset is done.
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*/
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#define PORT_WRC (1 << 19)
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/* true: over-current change */
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#define PORT_OCC (1 << 20)
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/* true: reset change - 1 to 0 transition of PORT_RESET */
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#define PORT_RC (1 << 21)
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/* port link status change - set on some port link state transitions:
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* Transition Reason
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* ------------------------------------------------------------------------------
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* - U3 to Resume Wakeup signaling from a device
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* - Resume to Recovery to U0 USB 3.0 device resume
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* - Resume to U0 USB 2.0 device resume
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* - U3 to Recovery to U0 Software resume of USB 3.0 device complete
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* - U3 to U0 Software resume of USB 2.0 device complete
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* - U2 to U0 L1 resume of USB 2.1 device complete
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* - U0 to U0 (???) L1 entry rejection by USB 2.1 device
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* - U0 to disabled L1 entry error with USB 2.1 device
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* - Any state to inactive Error on USB 3.0 port
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*/
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#define PORT_PLC (1 << 22)
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/* port configure error change - port failed to configure its link partner */
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#define PORT_CEC (1 << 23)
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#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
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PORT_RC | PORT_PLC | PORT_CEC)
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/* Cold Attach Status - xHC can set this bit to report device attached during
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* Sx state. Warm port reset should be perfomed to clear this bit and move port
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* to connected state.
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*/
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#define PORT_CAS (1 << 24)
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/* wake on connect (enable) */
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#define PORT_WKCONN_E (1 << 25)
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/* wake on disconnect (enable) */
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#define PORT_WKDISC_E (1 << 26)
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/* wake on over-current (enable) */
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#define PORT_WKOC_E (1 << 27)
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/* bits 28:29 reserved */
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/* true: device is non-removable - for USB 3.0 roothub emulation */
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#define PORT_DEV_REMOVE (1 << 30)
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/* Initiate a warm port reset - complete when PORT_WRC is '1' */
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#define PORT_WR (1 << 31)
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/* We mark duplicate entries with -1 */
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#define DUPLICATE_ENTRY ((u8)(-1))
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/* Port Power Management Status and Control - port_power_base bitmasks */
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/* Inactivity timer value for transitions into U1, in microseconds.
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* Timeout can be up to 127us. 0xFF means an infinite timeout.
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*/
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#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
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#define PORT_U1_TIMEOUT_MASK 0xff
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/* Inactivity timer value for transitions into U2 */
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#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
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#define PORT_U2_TIMEOUT_MASK (0xff << 8)
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/* Bits 24:31 for port testing */
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/* USB2 Protocol PORTSPMSC */
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#define PORT_L1S_MASK 7
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#define PORT_L1S_SUCCESS 1
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#define PORT_RWE (1 << 3)
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#define PORT_HIRD(p) (((p) & 0xf) << 4)
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#define PORT_HIRD_MASK (0xf << 4)
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#define PORT_L1DS_MASK (0xff << 8)
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#define PORT_L1DS(p) (((p) & 0xff) << 8)
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#define PORT_HLE (1 << 16)
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#define PORT_TEST_MODE_SHIFT 28
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/* USB3 Protocol PORTLI Port Link Information */
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#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
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#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
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/* USB2 Protocol PORTHLPMC */
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#define PORT_HIRDM(p)((p) & 3)
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#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
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#define PORT_BESLD(p)(((p) & 0xf) << 10)
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/* use 512 microseconds as USB2 LPM L1 default timeout. */
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#define XHCI_L1_TIMEOUT 512
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/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
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* Safe to use with mixed HIRD and BESL systems (host and device) and is used
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* by other operating systems.
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*
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* XHCI 1.0 errata 8/14/12 Table 13 notes:
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* "Software should choose xHC BESL/BESLD field values that do not violate a
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* device's resume latency requirements,
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* e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
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* or not program values < '4' if BLC = '0' and a BESL device is attached.
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*/
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#define XHCI_DEFAULT_BESL 4
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/*
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* USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
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* to complete link training. usually link trainig completes much faster
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* so check status 10 times with 36ms sleep in places we need to wait for
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* polling to complete.
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*/
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#define XHCI_PORT_POLLING_LFPS_TIME 36
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@ -22,6 +22,9 @@
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#include "xhci-ext-caps.h"
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#include "pci-quirks.h"
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#include "xhci-port.h"
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#include "xhci-caps.h"
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/* max buffer size for trace and debug messages */
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#define XHCI_MSG_MAX 500
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@ -62,90 +65,6 @@ struct xhci_cap_regs {
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/* Reserved up to (CAPLENGTH - 0x1C) */
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};
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/* hc_capbase bitmasks */
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/* bits 7:0 - how long is the Capabilities register */
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#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
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/* bits 31:16 */
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#define HC_VERSION(p) (((p) >> 16) & 0xffff)
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/* HCSPARAMS1 - hcs_params1 - bitmasks */
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/* bits 0:7, Max Device Slots */
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#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
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#define HCS_SLOTS_MASK 0xff
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/* bits 8:18, Max Interrupters */
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#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
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/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
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#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
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/* HCSPARAMS2 - hcs_params2 - bitmasks */
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/* bits 0:3, frames or uframes that SW needs to queue transactions
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* ahead of the HW to meet periodic deadlines */
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#define HCS_IST(p) (((p) >> 0) & 0xf)
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/* bits 4:7, max number of Event Ring segments */
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#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
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/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
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/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
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/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
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#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
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/* HCSPARAMS3 - hcs_params3 - bitmasks */
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/* bits 0:7, Max U1 to U0 latency for the roothub ports */
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#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
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/* bits 16:31, Max U2 to U0 latency for the roothub ports */
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#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
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/* HCCPARAMS - hcc_params - bitmasks */
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/* true: HC can use 64-bit address pointers */
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#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
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/* true: HC can do bandwidth negotiation */
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#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
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/* true: HC uses 64-byte Device Context structures
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* FIXME 64-byte context structures aren't supported yet.
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*/
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#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
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/* true: HC has port power switches */
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#define HCC_PPC(p) ((p) & (1 << 3))
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/* true: HC has port indicators */
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#define HCS_INDICATOR(p) ((p) & (1 << 4))
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/* true: HC has Light HC Reset Capability */
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#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
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/* true: HC supports latency tolerance messaging */
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#define HCC_LTC(p) ((p) & (1 << 6))
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/* true: no secondary Stream ID Support */
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#define HCC_NSS(p) ((p) & (1 << 7))
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/* true: HC supports Stopped - Short Packet */
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#define HCC_SPC(p) ((p) & (1 << 9))
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/* true: HC has Contiguous Frame ID Capability */
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#define HCC_CFC(p) ((p) & (1 << 11))
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/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
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#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
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/* Extended Capabilities pointer from PCI base - section 5.3.6 */
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#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
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#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
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/* db_off bitmask - bits 0:1 reserved */
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#define DBOFF_MASK (~0x3)
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/* run_regs_off bitmask - bits 0:4 reserved */
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#define RTSOFF_MASK (~0x1f)
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/* HCCPARAMS2 - hcc_params2 - bitmasks */
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/* true: HC supports U3 entry Capability */
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#define HCC2_U3C(p) ((p) & (1 << 0))
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/* true: HC supports Configure endpoint command Max exit latency too large */
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#define HCC2_CMC(p) ((p) & (1 << 1))
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/* true: HC supports Force Save context Capability */
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#define HCC2_FSC(p) ((p) & (1 << 2))
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/* true: HC supports Compliance Transition Capability */
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#define HCC2_CTC(p) ((p) & (1 << 3))
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/* true: HC support Large ESIT payload Capability > 48k */
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#define HCC2_LEC(p) ((p) & (1 << 4))
|
||||
/* true: HC support Configuration Information Capability */
|
||||
#define HCC2_CIC(p) ((p) & (1 << 5))
|
||||
/* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
|
||||
#define HCC2_ETC(p) ((p) & (1 << 6))
|
||||
|
||||
/* Number of registers per port */
|
||||
#define NUM_PORT_REGS 4
|
||||
|
||||
@ -291,181 +210,6 @@ struct xhci_op_regs {
|
||||
#define CONFIG_CIE (1 << 9)
|
||||
/* bits 10:31 - reserved and should be preserved */
|
||||
|
||||
/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
|
||||
/* true: device connected */
|
||||
#define PORT_CONNECT (1 << 0)
|
||||
/* true: port enabled */
|
||||
#define PORT_PE (1 << 1)
|
||||
/* bit 2 reserved and zeroed */
|
||||
/* true: port has an over-current condition */
|
||||
#define PORT_OC (1 << 3)
|
||||
/* true: port reset signaling asserted */
|
||||
#define PORT_RESET (1 << 4)
|
||||
/* Port Link State - bits 5:8
|
||||
* A read gives the current link PM state of the port,
|
||||
* a write with Link State Write Strobe set sets the link state.
|
||||
*/
|
||||
#define PORT_PLS_MASK (0xf << 5)
|
||||
#define XDEV_U0 (0x0 << 5)
|
||||
#define XDEV_U1 (0x1 << 5)
|
||||
#define XDEV_U2 (0x2 << 5)
|
||||
#define XDEV_U3 (0x3 << 5)
|
||||
#define XDEV_DISABLED (0x4 << 5)
|
||||
#define XDEV_RXDETECT (0x5 << 5)
|
||||
#define XDEV_INACTIVE (0x6 << 5)
|
||||
#define XDEV_POLLING (0x7 << 5)
|
||||
#define XDEV_RECOVERY (0x8 << 5)
|
||||
#define XDEV_HOT_RESET (0x9 << 5)
|
||||
#define XDEV_COMP_MODE (0xa << 5)
|
||||
#define XDEV_TEST_MODE (0xb << 5)
|
||||
#define XDEV_RESUME (0xf << 5)
|
||||
|
||||
/* true: port has power (see HCC_PPC) */
|
||||
#define PORT_POWER (1 << 9)
|
||||
/* bits 10:13 indicate device speed:
|
||||
* 0 - undefined speed - port hasn't be initialized by a reset yet
|
||||
* 1 - full speed
|
||||
* 2 - low speed
|
||||
* 3 - high speed
|
||||
* 4 - super speed
|
||||
* 5-15 reserved
|
||||
*/
|
||||
#define DEV_SPEED_MASK (0xf << 10)
|
||||
#define XDEV_FS (0x1 << 10)
|
||||
#define XDEV_LS (0x2 << 10)
|
||||
#define XDEV_HS (0x3 << 10)
|
||||
#define XDEV_SS (0x4 << 10)
|
||||
#define XDEV_SSP (0x5 << 10)
|
||||
#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
|
||||
#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
|
||||
#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
|
||||
#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
|
||||
#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
|
||||
#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
|
||||
#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
|
||||
#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
|
||||
|
||||
/* Bits 20:23 in the Slot Context are the speed for the device */
|
||||
#define SLOT_SPEED_FS (XDEV_FS << 10)
|
||||
#define SLOT_SPEED_LS (XDEV_LS << 10)
|
||||
#define SLOT_SPEED_HS (XDEV_HS << 10)
|
||||
#define SLOT_SPEED_SS (XDEV_SS << 10)
|
||||
#define SLOT_SPEED_SSP (XDEV_SSP << 10)
|
||||
/* Port Indicator Control */
|
||||
#define PORT_LED_OFF (0 << 14)
|
||||
#define PORT_LED_AMBER (1 << 14)
|
||||
#define PORT_LED_GREEN (2 << 14)
|
||||
#define PORT_LED_MASK (3 << 14)
|
||||
/* Port Link State Write Strobe - set this when changing link state */
|
||||
#define PORT_LINK_STROBE (1 << 16)
|
||||
/* true: connect status change */
|
||||
#define PORT_CSC (1 << 17)
|
||||
/* true: port enable change */
|
||||
#define PORT_PEC (1 << 18)
|
||||
/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
|
||||
* into an enabled state, and the device into the default state. A "warm" reset
|
||||
* also resets the link, forcing the device through the link training sequence.
|
||||
* SW can also look at the Port Reset register to see when warm reset is done.
|
||||
*/
|
||||
#define PORT_WRC (1 << 19)
|
||||
/* true: over-current change */
|
||||
#define PORT_OCC (1 << 20)
|
||||
/* true: reset change - 1 to 0 transition of PORT_RESET */
|
||||
#define PORT_RC (1 << 21)
|
||||
/* port link status change - set on some port link state transitions:
|
||||
* Transition Reason
|
||||
* ------------------------------------------------------------------------------
|
||||
* - U3 to Resume Wakeup signaling from a device
|
||||
* - Resume to Recovery to U0 USB 3.0 device resume
|
||||
* - Resume to U0 USB 2.0 device resume
|
||||
* - U3 to Recovery to U0 Software resume of USB 3.0 device complete
|
||||
* - U3 to U0 Software resume of USB 2.0 device complete
|
||||
* - U2 to U0 L1 resume of USB 2.1 device complete
|
||||
* - U0 to U0 (???) L1 entry rejection by USB 2.1 device
|
||||
* - U0 to disabled L1 entry error with USB 2.1 device
|
||||
* - Any state to inactive Error on USB 3.0 port
|
||||
*/
|
||||
#define PORT_PLC (1 << 22)
|
||||
/* port configure error change - port failed to configure its link partner */
|
||||
#define PORT_CEC (1 << 23)
|
||||
#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
|
||||
PORT_RC | PORT_PLC | PORT_CEC)
|
||||
|
||||
|
||||
/* Cold Attach Status - xHC can set this bit to report device attached during
|
||||
* Sx state. Warm port reset should be perfomed to clear this bit and move port
|
||||
* to connected state.
|
||||
*/
|
||||
#define PORT_CAS (1 << 24)
|
||||
/* wake on connect (enable) */
|
||||
#define PORT_WKCONN_E (1 << 25)
|
||||
/* wake on disconnect (enable) */
|
||||
#define PORT_WKDISC_E (1 << 26)
|
||||
/* wake on over-current (enable) */
|
||||
#define PORT_WKOC_E (1 << 27)
|
||||
/* bits 28:29 reserved */
|
||||
/* true: device is non-removable - for USB 3.0 roothub emulation */
|
||||
#define PORT_DEV_REMOVE (1 << 30)
|
||||
/* Initiate a warm port reset - complete when PORT_WRC is '1' */
|
||||
#define PORT_WR (1 << 31)
|
||||
|
||||
/* We mark duplicate entries with -1 */
|
||||
#define DUPLICATE_ENTRY ((u8)(-1))
|
||||
|
||||
/* Port Power Management Status and Control - port_power_base bitmasks */
|
||||
/* Inactivity timer value for transitions into U1, in microseconds.
|
||||
* Timeout can be up to 127us. 0xFF means an infinite timeout.
|
||||
*/
|
||||
#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
|
||||
#define PORT_U1_TIMEOUT_MASK 0xff
|
||||
/* Inactivity timer value for transitions into U2 */
|
||||
#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
|
||||
#define PORT_U2_TIMEOUT_MASK (0xff << 8)
|
||||
/* Bits 24:31 for port testing */
|
||||
|
||||
/* USB2 Protocol PORTSPMSC */
|
||||
#define PORT_L1S_MASK 7
|
||||
#define PORT_L1S_SUCCESS 1
|
||||
#define PORT_RWE (1 << 3)
|
||||
#define PORT_HIRD(p) (((p) & 0xf) << 4)
|
||||
#define PORT_HIRD_MASK (0xf << 4)
|
||||
#define PORT_L1DS_MASK (0xff << 8)
|
||||
#define PORT_L1DS(p) (((p) & 0xff) << 8)
|
||||
#define PORT_HLE (1 << 16)
|
||||
#define PORT_TEST_MODE_SHIFT 28
|
||||
|
||||
/* USB3 Protocol PORTLI Port Link Information */
|
||||
#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
|
||||
#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
|
||||
|
||||
/* USB2 Protocol PORTHLPMC */
|
||||
#define PORT_HIRDM(p)((p) & 3)
|
||||
#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
|
||||
#define PORT_BESLD(p)(((p) & 0xf) << 10)
|
||||
|
||||
/* use 512 microseconds as USB2 LPM L1 default timeout. */
|
||||
#define XHCI_L1_TIMEOUT 512
|
||||
|
||||
/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
|
||||
* Safe to use with mixed HIRD and BESL systems (host and device) and is used
|
||||
* by other operating systems.
|
||||
*
|
||||
* XHCI 1.0 errata 8/14/12 Table 13 notes:
|
||||
* "Software should choose xHC BESL/BESLD field values that do not violate a
|
||||
* device's resume latency requirements,
|
||||
* e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
|
||||
* or not program values < '4' if BLC = '0' and a BESL device is attached.
|
||||
*/
|
||||
#define XHCI_DEFAULT_BESL 4
|
||||
|
||||
/*
|
||||
* USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
|
||||
* to complete link training. usually link trainig completes much faster
|
||||
* so check status 10 times with 36ms sleep in places we need to wait for
|
||||
* polling to complete.
|
||||
*/
|
||||
#define XHCI_PORT_POLLING_LFPS_TIME 36
|
||||
|
||||
/**
|
||||
* struct xhci_intr_reg - Interrupt Register Set
|
||||
* @irq_pending: IMAN - Interrupt Management Register. Used to enable
|
||||
|
||||
Loading…
Reference in New Issue
Block a user