From c3ab84efbd05936cfac87ef6801e03534dc4b0b7 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Tue, 5 Dec 2023 07:58:20 -0800 Subject: [PATCH] drm/xe: Expand XE_REG_OPTION_MASKED documentation Expand documentation and add an example to make clear this isn't about generic masks in registers. Also, fix the doc regarding read operations: the mask part has no effect on them. Reviewed-by: Ashutosh Dixit Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20231205155820.2133813-1-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/regs/xe_reg_defs.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h index 6e20fc2de9ff..c50e7650c09a 100644 --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h @@ -60,7 +60,16 @@ struct xe_reg_mcr { /** * XE_REG_OPTION_MASKED - Register is "masked", with upper 16 bits marking the - * read/written bits on the lower 16 bits. + * written bits on the lower 16 bits. + * + * It only applies to registers explicitly marked in bspec with + * "Access: Masked". Registers with this option can have write operations to + * specific lower bits by setting the corresponding upper bits. Other bits will + * not be affected. This allows register writes without needing a RMW cycle and + * without caching in software the register value. + * + * Example: a write with value 0x00010001 will set bit 0 and all other bits + * retain their previous values. * * To be used with XE_REG(). XE_REG_MCR() and XE_REG_INITIALIZER() */