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Device Tree and Multiplatform support for U300:

Browse Source 
- Add devicetree support to timer, pinctrl (probe), I2C block,
   watchdog, DMA controller and clocks.
 - Piecewise add a device tree containing all peripherals.
 - Delete the ATAG boot path.
 - Delete redundant platform data and board files.
 - Convert to multiplatform.
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Merge tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/soc

From Linus Walleij:

Device Tree and Multiplatform support for U300:
- Add devicetree support to timer, pinctrl (probe), I2C block,
  watchdog, DMA controller and clocks.
- Piecewise add a device tree containing all peripherals.
- Delete the ATAG boot path.
- Delete redundant platform data and board files.
- Convert to multiplatform.

* tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: (40 commits)
  ARM: u300: switch to using syscon regmap for board
  ARM: u300: Update MMC configs for u300 defconfig
  spi: pl022: use DMA by default when probing from DT
  pinctrl: get rid of all platform data for coh901
  ARM: u300: convert MMC/SD clock to device tree
  ARM: u300: move the gated system controller clocks to DT
  i2c: stu300: do not request a specific clock name
  clk: move the U300 fixed and fixed-factor to DT
  ARM: u300: remove register definition file
  ARM: u300: add syscon node
  ARM: u300 use module_spi_driver to register driver
  ARM: u300: delete remnant machine headers
  ARM: u300: convert to multiplatform
  ARM: u300: localize <mach/u300-regs.h>
  ARM: u300: delete <mach/irqs.h>
  ARM: u300: delete <mach/hardware.h>
  ARM: u300: push down syscon registers
  ARM: u300: remove deps from debug macro
  ARM: u300: move debugmacro to debug includes
  ARM: u300: delete all static board data
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-06-20 01:51:18 +02:00
commit c3b693d1d6
40 changed files with 1786 additions and 2219 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
Documentation/devicetree/bindings/arm/ste-u300.txt Normal file
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@ -0,0 +1,46 @@
ST-Ericsson U300 Device Tree Bindings
For various board the "board" node may contain specific properties
that pertain to this particular board, such as board-specific GPIOs
or board power regulator supplies.
Required root node property:
compatible="stericsson,u300";
Required node: syscon
This contains the system controller.
- compatible: must be "stericsson,u300-syscon".
- reg: the base address and size of the system controller.
Boards with the U300 SoC include:
S365 "Small Board U365":
Required node: s365
This contains the board-specific information.
- compatible: must be "stericsson,s365".
- vana15-supply: the regulator supplying the 1.5V to drive the
board.
- syscon: a pointer to the syscon node so we can acccess the
syscon registers to set the board as self-powered.
Example:
/ {
model = "ST-Ericsson U300";
compatible = "stericsson,u300";
#address-cells = <1>;
#size-cells = <1>;
s365 {
compatible = "stericsson,s365";
vana15-supply = <&ab3100_ldo_d_reg>;
syscon = <&syscon>;
};
syscon: syscon@c0011000 {
compatible = "stericsson,u300-syscon";
reg = <0xc0011000 0x1000>;
};
};

80
Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt Normal file
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@ -0,0 +1,80 @@
Clock bindings for ST-Ericsson U300 System Controller Clocks
Bindings for the gated system controller clocks:
Required properties:
- compatible: must be "stericsson,u300-syscon-clk"
- #clock-cells: must be <0>
- clock-type: specifies the type of clock:
0 = slow clock
1 = fast clock
2 = rest/remaining clock
- clock-id: specifies the clock in the type range
Optional properties:
- clocks: parent clock(s)
The available clocks per type are as follows:
Type: ID: Clock:
-------------------
0 0 Slow peripheral bridge clock
0 1 UART0 clock
0 4 GPIO clock
0 6 RTC clock
0 7 Application timer clock
0 8 Access timer clock
1 0 Fast peripheral bridge clock
1 1 I2C bus 0 clock
1 2 I2C bus 1 clock
1 5 MMC interface peripheral (silicon) clock
1 6 SPI clock
2 3 CPU clock
2 4 DMA controller clock
2 5 External Memory Interface (EMIF) clock
2 6 NAND flask interface clock
2 8 XGAM graphics engine clock
2 9 Shared External Memory Interface (SEMI) clock
2 10 AHB Subsystem Bridge clock
2 12 Interrupt controller clock
Example:
gpio_clk: gpio_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <4>;
clocks = <&slow_clk>;
};
gpio: gpio@c0016000 {
compatible = "stericsson,gpio-coh901";
(...)
clocks = <&gpio_clk>;
};
Bindings for the MMC/SD card clock:
Required properties:
- compatible: must be "stericsson,u300-syscon-mclk"
- #clock-cells: must be <0>
Optional properties:
- clocks: parent clock(s)
mmc_mclk: mmc_mclk {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-mclk";
clocks = <&mmc_pclk>;
};
mmcsd: mmcsd@c0001000 {
compatible = "arm,pl18x", "arm,primecell";
clocks = <&mmc_pclk>, <&mmc_mclk>;
clock-names = "apb_pclk", "mclk";
(...)
};

32
Documentation/devicetree/bindings/dma/ste-coh901318.txt Normal file
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@ -0,0 +1,32 @@
ST-Ericsson COH 901 318 DMA Controller
This is a DMA controller which has begun as a fork of the
ARM PL08x PrimeCell VHDL code.
Required properties:
- compatible: should be "stericsson,coh901318"
- reg: register locations and length
- interrupts: the single DMA IRQ
- #dma-cells: must be set to <1>, as the channels on the
COH 901 318 are simple and identified by a single number
- dma-channels: the number of DMA channels handled
Example:
dmac: dma-controller@c00020000 {
compatible = "stericsson,coh901318";
reg = <0xc0020000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <2>;
#dma-cells = <1>;
dma-channels = <40>;
};
Consumers example:
uart0: serial@c0013000 {
compatible = "...";
(...)
dmas = <&dmac 17 &dmac 18>;
dma-names = "tx", "rx";
};

7
Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt Normal file
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@ -0,0 +1,7 @@
ST-Ericsson COH 901 571/3 GPIO controller
Required properties:
- compatible: Compatible property value should be "stericsson,gpio-coh901"
- reg: Physical base address of the controller and length of memory mapped
region.
- interrupts: the 0...n interrupts assigned to the different GPIO ports/banks.

15
Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt Normal file
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@ -0,0 +1,15 @@
ST Microelectronics DDC I2C
Required properties :
- compatible : Must be "st,ddci2c"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- #address-cells = <1>;
- #size-cells = <0>;
Optional properties:
- Child nodes conforming to i2c bus binding
Examples :

18
Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt Normal file
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@ -0,0 +1,18 @@
ST-Ericsson U300 apptimer
Required properties:
- compatible : should be "stericsson,u300-apptimer"
- reg : Specifies base physical address and size of the registers.
- interrupts : A list of 4 interrupts; one for each subtimer. These
are, in order: OS (operating system), DD (device driver) both
adopted for EPOC/Symbian with two specific IRQs for these tasks,
then GP1 and GP2, which are general-purpose timers.
Example:
timer {
compatible = "stericsson,u300-apptimer";
reg = <0xc0014000 0x1000>;
interrupts = <24 25 26 27>;
};

19
Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt Normal file
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@ -0,0 +1,19 @@
ST-Ericsson COH 901 327 Watchdog timer
Required properties:
- compatible: must be "stericsson,coh901327".
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: the interrupt used for the watchdog timeout warning.
Optional properties:
- timeout-sec: contains the watchdog timeout in seconds.
Example:
watchdog: watchdog@c0012000 {
compatible = "stericsson,coh901327";
reg = <0xc0012000 0x1000>;
interrupts = <3>;
timeout-sec = <60>;
};

19
arch/arm/Kconfig
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@ -815,23 +815,6 @@ config ARCH_SHARK
Support for the StrongARM based Digital DNARD machine, also known Support for the StrongARM based Digital DNARD machine, also known
as "Shark" (<http://www.shark-linux.de/shark.html>). as "Shark" (<http://www.shark-linux.de/shark.html>).
config ARCH_U300
bool "ST-Ericsson U300 Series"
depends on MMU
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select ARM_PATCH_PHYS_VIRT
select ARM_VIC
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select COMMON_CLK
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select HAVE_TCM
select SPARSE_IRQ
help
Support for ST-Ericsson U300 series mobile platforms.
config ARCH_DAVINCI config ARCH_DAVINCI
bool "TI DaVinci" bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_HAS_HOLES_MEMORYMODEL
@ -2045,7 +2028,7 @@ config CRASH_DUMP
config AUTO_ZRELADDR config AUTO_ZRELADDR
bool "Auto calculation of the decompressed kernel image address" bool "Auto calculation of the decompressed kernel image address"
depends on !ZBOOT_ROM && !ARCH_U300 depends on !ZBOOT_ROM
help help
ZRELADDR is the physical address where the decompressed kernel ZRELADDR is the physical address where the decompressed kernel
image will be placed. If AUTO_ZRELADDR is selected, the address image will be placed. If AUTO_ZRELADDR is selected, the address

8
arch/arm/Kconfig.debug
View File

@ -482,6 +482,13 @@ choice
Say Y here if you want the debug print routines to direct Say Y here if you want the debug print routines to direct
their output to the uart1 port on SiRFmarco devices. their output to the uart1 port on SiRFmarco devices.
config DEBUG_U300_UART
bool "Kernel low-level debugging messages via U300 UART0"
depends on ARCH_U300
help
Say Y here if you want the debug print routines to direct
their output to the uart port on U300 devices.
config DEBUG_UX500_UART config DEBUG_UX500_UART
depends on ARCH_U8500 depends on ARCH_U8500
bool "Use Ux500 UART for low-level debug" bool "Use Ux500 UART for low-level debug"
@ -685,6 +692,7 @@ config DEBUG_LL_INCLUDE
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
default "debug/tegra.S" if DEBUG_TEGRA_UART default "debug/tegra.S" if DEBUG_TEGRA_UART
default "debug/u300.S" if DEBUG_U300_UART
default "debug/ux500.S" if DEBUG_UX500_UART default "debug/ux500.S" if DEBUG_UX500_UART
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1

1
arch/arm/boot/dts/Makefile
View File

@ -201,6 +201,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra114-pluto.dtb tegra114-pluto.dtb
dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
versatile-pb.dtb versatile-pb.dtb
dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
vexpress-v2p-ca9.dtb \ vexpress-v2p-ca9.dtb \
vexpress-v2p-ca15-tc1.dtb \ vexpress-v2p-ca15-tc1.dtb \

473
arch/arm/boot/dts/ste-u300.dts Normal file
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@ -0,0 +1,473 @@
/*
* Device Tree for the ST-Ericsson U300 Machine and SoC
*/
/dts-v1/;
/include/ "skeleton.dtsi"
/ {
model = "ST-Ericsson U300";
compatible = "stericsson,u300";
#address-cells = <1>;
#size-cells = <1>;
chosen {
bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk";
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
memory {
reg = <0x48000000 0x03c00000>;
};
s365 {
compatible = "stericsson,s365";
vana15-supply = <&ab3100_ldo_d_reg>;
syscon = <&syscon>;
};
syscon: syscon@c0011000 {
compatible = "stericsson,u300-syscon", "syscon";
reg = <0xc0011000 0x1000>;
clk32: app_32_clk@32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
pll13: pll13@13M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <13000000>;
};
/* Slow bridge clocks under PLL13 */
slow_clk: slow_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <0>;
clocks = <&pll13>;
};
uart0_clk: uart0_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <1>;
clocks = <&slow_clk>;
};
gpio_clk: gpio_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <4>;
clocks = <&slow_clk>;
};
rtc_clk: rtc_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <6>;
clocks = <&slow_clk>;
};
apptimer_clk: app_tmr_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <7>;
clocks = <&slow_clk>;
};
acc_tmr_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <8>;
clocks = <&slow_clk>;
};
pll208: pll208@208M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <208000000>;
};
app208: app_208_clk@208M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&pll208>;
};
cpu_clk@208M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <3>;
clocks = <&app208>;
};
app104: app_104_clk@104M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
clock-mult = <1>;
clocks = <&pll208>;
};
semi_clk@104M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <9>;
clocks = <&app104>;
};
app52: app_52_clk@52M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <4>;
clock-mult = <1>;
clocks = <&pll208>;
};
/* AHB subsystem clocks */
ahb_clk: ahb_subsys_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <10>;
clocks = <&app52>;
};
intcon_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <12>;
clocks = <&ahb_clk>;
};
emif_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <5>;
clocks = <&ahb_clk>;
};
dmac_clk: dmac_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <4>;
clocks = <&app52>;
};
fsmc_clk: fsmc_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <6>;
clocks = <&app52>;
};
xgam_clk: xgam_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <8>;
clocks = <&app52>;
};
app26: app_26_clk@26M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
clock-mult = <1>;
clocks = <&app52>;
};
/* Fast bridge clocks */
fast_clk: fast_clk@26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <1>; /* Fast */
clock-id = <0>;
clocks = <&app26>;
};
i2c0_clk: i2c0_clk@26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <1>; /* Fast */
clock-id = <1>;
clocks = <&fast_clk>;
};
i2c1_clk: i2c1_clk@26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <1>; /* Fast */
clock-id = <2>;
clocks = <&fast_clk>;
};
mmc_pclk: mmc_p_clk@26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <1>; /* Fast */
clock-id = <5>;
clocks = <&fast_clk>;
};
mmc_mclk: mmc_mclk {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-mclk";
clocks = <&mmc_pclk>;
};
spi_clk: spi_p_clk@26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <1>; /* Fast */
clock-id = <6>;
clocks = <&fast_clk>;
};
};
timer: timer@c0014000 {
compatible = "stericsson,u300-apptimer";
reg = <0xc0014000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <24 25 26 27>;
clocks = <&apptimer_clk>;
};
gpio: gpio@c0016000 {
compatible = "stericsson,gpio-coh901";
reg = <0xc0016000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <0 1 2 18 21 22 23>;
clocks = <&gpio_clk>;
interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
"gpio4", "gpio5", "gpio6";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
pinctrl: pinctrl@c0011000 {
compatible = "stericsson,pinctrl-u300";
reg = <0xc0011000 0x1000>;
};
watchdog: watchdog@c0012000 {
compatible = "stericsson,coh901327";
reg = <0xc0012000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <3>;
clocks = <&clk32>;
};
rtc: rtc@c0017000 {
compatible = "stericsson,coh901331";
reg = <0xc0017000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <10>;
clocks = <&rtc_clk>;
};
dmac: dma-controller@c00020000 {
compatible = "stericsson,coh901318";
reg = <0xc0020000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <2>;
#dma-cells = <1>;
dma-channels = <40>;
clocks = <&dmac_clk>;
};
/* A NAND flash of 128 MiB */
fsmc: flash@40000000 {
compatible = "stericsson,fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x9f800000 0x1000>, /* FSMC Register*/
<0x80000000 0x4000>, /* NAND Base DATA */
<0x80020000 0x4000>, /* NAND Base ADDR */
<0x80010000 0x4000>; /* NAND Base CMD */
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
nand-skip-bbtscan;
clocks = <&fsmc_clk>;
partition@0 {
label = "boot records";
reg = <0x0 0x20000>;
};
partition@20000 {
label = "free";
reg = <0x20000 0x7e0000>;
};
partition@800000 {
label = "platform";
reg = <0x800000 0xf800000>;
};
};
i2c0: i2c@c0004000 {
compatible = "st,ddci2c";
reg = <0xc0004000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <8>;
clocks = <&i2c0_clk>;
#address-cells = <1>;
#size-cells = <0>;
ab3100: ab3100@0x48 {
compatible = "stericsson,ab3100";
reg = <0x48>;
interrupt-parent = <&vica>;
interrupts = <0>; /* EXT0 IRQ */
ab3100-regulators {
compatible = "stericsson,ab3100-regulators";
ab3100_ldo_a_reg: ab3100_ldo_a {
regulator-compatible = "ab3100_ldo_a";
startup-delay-us = <200>;
regulator-always-on;
regulator-boot-on;
};
ab3100_ldo_c_reg: ab3100_ldo_c {
regulator-compatible = "ab3100_ldo_c";
startup-delay-us = <200>;
};
ab3100_ldo_d_reg: ab3100_ldo_d {
regulator-compatible = "ab3100_ldo_d";
startup-delay-us = <200>;
};
ab3100_ldo_e_reg: ab3100_ldo_e {
regulator-compatible = "ab3100_ldo_e";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <200>;
regulator-always-on;
regulator-boot-on;
};
ab3100_ldo_f_reg: ab3100_ldo_f {
regulator-compatible = "ab3100_ldo_f";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
startup-delay-us = <600>;
regulator-always-on;
regulator-boot-on;
};
ab3100_ldo_g_reg: ab3100_ldo_g {
regulator-compatible = "ab3100_ldo_g";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2850000>;
startup-delay-us = <400>;
};
ab3100_ldo_h_reg: ab3100_ldo_h {
regulator-compatible = "ab3100_ldo_h";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2750000>;
startup-delay-us = <200>;
};
ab3100_ldo_k_reg: ab3100_ldo_k {
regulator-compatible = "ab3100_ldo_k";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2750000>;
startup-delay-us = <200>;
};
ab3100_ext_reg: ab3100_ext {
regulator-compatible = "ab3100_ext";
};
ab3100_buck_reg: ab3100_buck {
regulator-compatible = "ab3100_buck";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <1000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
i2c1: i2c@c0005000 {
compatible = "st,ddci2c";
reg = <0xc0005000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <9>;
clocks = <&i2c1_clk>;
#address-cells = <1>;
#size-cells = <0>;
fwcam0: fwcam@0x10 {
reg = <0x10>;
};
fwcam1: fwcam@0x5d {
reg = <0x5d>;
};
};
amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
vica: interrupt-controller@a0001000 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xa0001000 0x20>;
};
vicb: interrupt-controller@a0002000 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xa0002000 0x20>;
};
uart0: serial@c0013000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xc0013000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <22>;
clocks = <&uart0_clk>, <&uart0_clk>;
clock-names = "apb_pclk", "uart0_clk";
dmas = <&dmac 17 &dmac 18>;
dma-names = "tx", "rx";
};
uart1: serial@c0007000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xc0007000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <20>;
dmas = <&dmac 38 &dmac 39>;
dma-names = "tx", "rx";
};
mmcsd: mmcsd@c0001000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0xc0001000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <6 7>;
clocks = <&mmc_pclk>, <&mmc_mclk>;
clock-names = "apb_pclk", "mclk";
max-frequency = <24000000>;
bus-width = <4>; // SD-card slot
mmc-cap-mmc-highspeed;
mmc-cap-sd-highspeed;
cd-gpios = <&gpio 12 0x4>;
cd-inverted;
vmmc-supply = <&ab3100_ldo_g_reg>;
dmas = <&dmac 14>;
dma-names = "rx";
};
spi: ssp@c0006000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xc0006000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <23>;
clocks = <&spi_clk>, <&spi_clk>;
clock-names = "apb_pclk", "spi_clk";
dmas = <&dmac 27 &dmac 28>;
dma-names = "tx", "rx";
num-cs = <3>;
#address-cells = <1>;
#size-cells = <0>;
spi-dummy@1 {
compatible = "arm,pl022-dummy";
reg = <1>;
spi-max-frequency = <20000000>;
};
};
};
};

14
arch/arm/configs/u300_defconfig
View File

@ -1,7 +1,8 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set # CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set # CONFIG_SWAP is not set
CONFIG_SYSVIPC=y CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14 CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y CONFIG_EXPERT=y
# CONFIG_AIO is not set # CONFIG_AIO is not set
@ -11,12 +12,9 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_LBDAF is not set # CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_CFQ is not set # CONFIG_IOSCHED_CFQ is not set
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_U300=y CONFIG_ARCH_U300=y
CONFIG_MACH_U300=y
CONFIG_MACH_U300_BS335=y
CONFIG_MACH_U300_SPIDUMMY=y CONFIG_MACH_U300_SPIDUMMY=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y CONFIG_PREEMPT=y
CONFIG_AEABI=y CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_TEXT=0x0
@ -44,14 +42,15 @@ CONFIG_I2C=y
# CONFIG_HWMON is not set # CONFIG_HWMON is not set
CONFIG_WATCHDOG=y CONFIG_WATCHDOG=y
CONFIG_REGULATOR=y CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_FB=y CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set # CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set # CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y CONFIG_MMC=y
CONFIG_MMC_CLKGATE=y CONFIG_MMC_UNSAFE_RESUME=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_ARMMMCI=y CONFIG_MMC_ARMMMCI=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set # CONFIG_RTC_HCTOSYS is not set
@ -70,4 +69,3 @@ CONFIG_DEBUG_FS=y
CONFIG_TIMER_STATS=y CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_PREEMPT is not set # CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y CONFIG_DEBUG_INFO=y
# CONFIG_CRC32 is not set

9
arch/arm/mach-u300/include/mach/debug-macro.S → arch/arm/include/debug/u300.S
View File

@ -1,14 +1,11 @@
/* /*
* * Copyright (C) 2006-2013 ST-Ericsson AB
* arch-arm/mach-u300/include/mach/debug-macro.S
*
*
* Copyright (C) 2006-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2 * License terms: GNU General Public License (GPL) version 2
* Debugging macro include header. * Debugging macro include header.
* Author: Linus Walleij <linus.walleij@stericsson.com> * Author: Linus Walleij <linus.walleij@stericsson.com>
*/ */
#include <mach/hardware.h> #define U300_SLOW_PER_PHYS_BASE 0xc0010000
#define U300_SLOW_PER_VIRT_BASE 0xff000000
.macro addruart, rp, rv, tmp .macro addruart, rp, rv, tmp
/* If we move the address using MMU, use this. */ /* If we move the address using MMU, use this. */

32
arch/arm/mach-u300/Kconfig
View File

@ -1,24 +1,46 @@
if ARCH_U300
menu "ST-Ericsson AB U300/U335 Platform" menu "ST-Ericsson AB U300/U335 Platform"
comment "ST-Ericsson Mobile Platform Products" comment "ST-Ericsson Mobile Platform Products"
config MACH_U300 config ARCH_U300
bool "U300" bool "ST-Ericsson U300 Series"
depends on MMU
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select ARM_PATCH_PHYS_VIRT
select ARM_VIC
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF
select COMMON_CLK
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select HAVE_TCM
select PINCTRL select PINCTRL
select PINCTRL_COH901 select PINCTRL_COH901
select PINCTRL_U300 select PINCTRL_U300
select SPARSE_IRQ
select MFD_SYSCON
select USE_OF
help
Support for ST-Ericsson U300 series mobile platforms.
comment "ST-Ericsson U300/U335 Feature Selections" comment "ST-Ericsson U300/U335 Feature Selections"
config MACH_U300
depends on ARCH_U300
bool "U300"
default y
config U300_DEBUG config U300_DEBUG
depends on ARCH_U300
bool "Debug support for U300" bool "Debug support for U300"
depends on PM depends on PM
help help
Debug support for U300 in sysfs, procfs etc. Debug support for U300 in sysfs, procfs etc.
config MACH_U300_SPIDUMMY config MACH_U300_SPIDUMMY
depends on ARCH_U300
bool "SSP/SPI dummy chip" bool "SSP/SPI dummy chip"
select SPI select SPI
select SPI_MASTER select SPI_MASTER
@ -31,5 +53,3 @@ config MACH_U300_SPIDUMMY
SPI framework and ARM PL022 support. SPI framework and ARM PL022 support.
endmenu endmenu
endif

2
arch/arm/mach-u300/Makefile
View File

@ -7,7 +7,5 @@ obj-m :=
obj-n := obj-n :=
obj- := obj- :=
obj-$(CONFIG_SPI_PL022) += spi.o
obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o
obj-$(CONFIG_I2C_STU300) += i2c.o
obj-$(CONFIG_REGULATOR_AB3100) += regulator.o obj-$(CONFIG_REGULATOR_AB3100) += regulator.o

759
arch/arm/mach-u300/core.c
View File

@ -9,46 +9,157 @@
* Author: Linus Walleij <linus.walleij@stericsson.com> * Author: Linus Walleij <linus.walleij@stericsson.com>
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/termios.h>
#include <linux/dmaengine.h>
#include <linux/amba/bus.h>
#include <linux/amba/mmci.h>
#include <linux/amba/serial.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/fsmc.h>
#include <linux/pinctrl/machine.h> #include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf-generic.h>
#include <linux/dma-mapping.h>
#include <linux/platform_data/clk-u300.h> #include <linux/platform_data/clk-u300.h>
#include <linux/platform_data/pinctrl-coh901.h> #include <linux/irqchip.h>
#include <linux/platform_data/dma-coh901318.h> #include <linux/of_address.h>
#include <linux/irqchip/arm-vic.h> #include <linux/of_platform.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <mach/hardware.h> /*
#include <mach/syscon.h> * These are the large blocks of memory allocated for I/O.
#include <mach/irqs.h> * the defines are used for setting up the I/O memory mapping.
*/
#include "timer.h" /* NAND Flash CS0 */
#include "spi.h" #define U300_NAND_CS0_PHYS_BASE 0x80000000
#include "i2c.h" /* NFIF */
#include "u300-gpio.h" #define U300_NAND_IF_PHYS_BASE 0x9f800000
/* ALE, CLE offset for FSMC NAND */
#define PLAT_NAND_CLE (1 << 16)
#define PLAT_NAND_ALE (1 << 17)
/* AHB Peripherals */
#define U300_AHB_PER_PHYS_BASE 0xa0000000
#define U300_AHB_PER_VIRT_BASE 0xff010000
/* FAST Peripherals */
#define U300_FAST_PER_PHYS_BASE 0xc0000000
#define U300_FAST_PER_VIRT_BASE 0xff020000
/* SLOW Peripherals */
#define U300_SLOW_PER_PHYS_BASE 0xc0010000
#define U300_SLOW_PER_VIRT_BASE 0xff000000
/* Boot ROM */
#define U300_BOOTROM_PHYS_BASE 0xffff0000
#define U300_BOOTROM_VIRT_BASE 0xffff0000
/* SEMI config base */
#define U300_SEMI_CONFIG_BASE 0x2FFE0000
/*
* AHB peripherals
*/
/* AHB Peripherals Bridge Controller */
#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
/* Vectored Interrupt Controller 0, servicing 32 interrupts */
#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
/* Vectored Interrupt Controller 1, servicing 32 interrupts */
#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
/* Memory Stick Pro (MSPRO) controller */
#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
/* EMIF Configuration Area */
#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
/*
* FAST peripherals
*/
/* FAST bridge control */
#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
/* MMC/SD controller */
#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
/* PCM I2S0 controller */
#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
/* PCM I2S1 controller */
#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
/* I2C0 controller */
#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
/* I2C1 controller */
#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
/* SPI controller */
#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
/* Fast UART1 on U335 only */
#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
/*
* SLOW peripherals
*/
/* SLOW bridge control */
#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
/* SYSCON */
#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
/* Watchdog */
#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
/* UART0 */
#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
/* APP side special timer */
#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
/* Keypad */
#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
/* GPIO */
#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
/* RTC */
#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
/* Bus tracer */
#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
/* Event handler (hardware queue) */
#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
/* Genric Timer */
#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
/* PPM */
#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
/*
* REST peripherals
*/
/* ISP (image signal processor) */
#define U300_ISP_BASE (0xA0008000)
/* DMA Controller base */
#define U300_DMAC_BASE (0xC0020000)
/* MSL Base */
#define U300_MSL_BASE (0xc0022000)
/* APEX Base */
#define U300_APEX_BASE (0xc0030000)
/* Video Encoder Base */
#define U300_VIDEOENC_BASE (0xc0080000)
/* XGAM Base */
#define U300_XGAM_BASE (0xd0000000)
/*
* SYSCON addresses applicable to the core machine.
*/
/* Chip ID register 16bit (R/-) */
#define U300_SYSCON_CIDR (0x400)
/* SMCR */
#define U300_SYSCON_SMCR (0x4d0)
#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
#define U300_SYSCON_CSDR (0x4f0)
#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
/* PRINT_CONTROL Print Control 16bit (R/-) */
#define U300_SYSCON_PCR (0x4f8)
#define U300_SYSCON_PCR_SERV_IND (0x0001)
/* BOOT_CONTROL 16bit (R/-) */
#define U300_SYSCON_BCR (0x4fc)
#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
static void __iomem *syscon_base;
/* /*
* Static I/O mappings that are needed for booting the U300 platforms. The * Static I/O mappings that are needed for booting the U300 platforms. The
@ -82,365 +193,6 @@ static void __init u300_map_io(void)
iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc)); iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
} }
/*
* Declaration of devices found on the U300 board and
* their respective memory locations.
*/
static struct amba_pl011_data uart0_plat_data = {
#ifdef CONFIG_COH901318
.dma_filter = coh901318_filter_id,
.dma_rx_param = (void *) U300_DMA_UART0_RX,
.dma_tx_param = (void *) U300_DMA_UART0_TX,
#endif
};
/* Slow device at 0x3000 offset */
static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
{ IRQ_U300_UART0 }, &uart0_plat_data);
/* The U335 have an additional UART1 on the APP CPU */
static struct amba_pl011_data uart1_plat_data = {
#ifdef CONFIG_COH901318
.dma_filter = coh901318_filter_id,
.dma_rx_param = (void *) U300_DMA_UART1_RX,
.dma_tx_param = (void *) U300_DMA_UART1_TX,
#endif
};
/* Fast device at 0x7000 offset */
static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
{ IRQ_U300_UART1 }, &uart1_plat_data);
/* AHB device at 0x4000 offset */
static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
/* Fast device at 0x6000 offset */
static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
{ IRQ_U300_SPI }, NULL);
/* Fast device at 0x1000 offset */
#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
static struct mmci_platform_data mmcsd_platform_data = {
/*
* Do not set ocr_mask or voltage translation function,
* we have a regulator we can control instead.
*/
.f_max = 24000000,
.gpio_wp = -1,
.gpio_cd = U300_GPIO_PIN_MMC_CD,
.cd_invert = true,
.capabilities = MMC_CAP_MMC_HIGHSPEED |
MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
#ifdef CONFIG_COH901318
.dma_filter = coh901318_filter_id,
.dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
/* Don't specify a TX channel, this RX channel is bidirectional */
#endif
};
static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
U300_MMCSD_IRQS, &mmcsd_platform_data);
/*
* The order of device declaration may be important, since some devices
* have dependencies on other devices being initialized first.
*/
static struct amba_device *amba_devs[] __initdata = {
&uart0_device,
&uart1_device,
&pl022_device,
&pl172_device,
&mmcsd_device,
};
/* Here follows a list of all hw resources that the platform devices
* allocate. Note, clock dependencies are not included
*/
static struct resource gpio_resources[] = {
{
.start = U300_GPIO_BASE,
.end = (U300_GPIO_BASE + SZ_4K - 1),
.flags = IORESOURCE_MEM,
},
{
.name = "gpio0",
.start = IRQ_U300_GPIO_PORT0,
.end = IRQ_U300_GPIO_PORT0,
.flags = IORESOURCE_IRQ,
},
{
.name = "gpio1",
.start = IRQ_U300_GPIO_PORT1,
.end = IRQ_U300_GPIO_PORT1,
.flags = IORESOURCE_IRQ,
},
{
.name = "gpio2",
.start = IRQ_U300_GPIO_PORT2,
.end = IRQ_U300_GPIO_PORT2,
.flags = IORESOURCE_IRQ,
},
{
.name = "gpio3",
.start = IRQ_U300_GPIO_PORT3,
.end = IRQ_U300_GPIO_PORT3,
.flags = IORESOURCE_IRQ,
},
{
.name = "gpio4",
.start = IRQ_U300_GPIO_PORT4,
.end = IRQ_U300_GPIO_PORT4,
.flags = IORESOURCE_IRQ,
},
{
.name = "gpio5",
.start = IRQ_U300_GPIO_PORT5,
.end = IRQ_U300_GPIO_PORT5,
.flags = IORESOURCE_IRQ,
},
{
.name = "gpio6",
.start = IRQ_U300_GPIO_PORT6,
.end = IRQ_U300_GPIO_PORT6,
.flags = IORESOURCE_IRQ,
},
};
static struct resource keypad_resources[] = {
{
.start = U300_KEYPAD_BASE,
.end = U300_KEYPAD_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "coh901461-press",
.start = IRQ_U300_KEYPAD_KEYBF,
.end = IRQ_U300_KEYPAD_KEYBF,
.flags = IORESOURCE_IRQ,
},
{
.name = "coh901461-release",
.start = IRQ_U300_KEYPAD_KEYBR,
.end = IRQ_U300_KEYPAD_KEYBR,
.flags = IORESOURCE_IRQ,
},
};
static struct resource rtc_resources[] = {
{
.start = U300_RTC_BASE,
.end = U300_RTC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_U300_RTC,
.end = IRQ_U300_RTC,
.flags = IORESOURCE_IRQ,
},
};
/*
* Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
* but these are not yet used by the driver.
*/
static struct resource fsmc_resources[] = {
{
.name = "nand_addr",
.start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
.end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "nand_cmd",
.start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
.end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "nand_data",
.start = U300_NAND_CS0_PHYS_BASE,
.end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "fsmc_regs",
.start = U300_NAND_IF_PHYS_BASE,
.end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct resource i2c0_resources[] = {
{
.start = U300_I2C0_BASE,
.end = U300_I2C0_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_U300_I2C0,
.end = IRQ_U300_I2C0,
.flags = IORESOURCE_IRQ,
},
};
static struct resource i2c1_resources[] = {
{
.start = U300_I2C1_BASE,
.end = U300_I2C1_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_U300_I2C1,
.end = IRQ_U300_I2C1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource wdog_resources[] = {
{
.start = U300_WDOG_BASE,
.end = U300_WDOG_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_U300_WDOG,
.end = IRQ_U300_WDOG,
.flags = IORESOURCE_IRQ,
}
};
static struct resource dma_resource[] = {
{
.start = U300_DMAC_BASE,
.end = U300_DMAC_BASE + PAGE_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_U300_DMA,
.end = IRQ_U300_DMA,
.flags = IORESOURCE_IRQ,
}
};
static struct resource pinctrl_resources[] = {
{
.start = U300_SYSCON_BASE,
.end = U300_SYSCON_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device wdog_device = {
.name = "coh901327_wdog",
.id = -1,
.num_resources = ARRAY_SIZE(wdog_resources),
.resource = wdog_resources,
};
static struct platform_device i2c0_device = {
.name = "stu300",
.id = 0,
.num_resources = ARRAY_SIZE(i2c0_resources),
.resource = i2c0_resources,
};
static struct platform_device i2c1_device = {
.name = "stu300",
.id = 1,
.num_resources = ARRAY_SIZE(i2c1_resources),
.resource = i2c1_resources,
};
static struct platform_device pinctrl_device = {
.name = "pinctrl-u300",
.id = -1,
.num_resources = ARRAY_SIZE(pinctrl_resources),
.resource = pinctrl_resources,
};
/*
* The different variants have a few different versions of the
* GPIO block, with different number of ports.
*/
static struct u300_gpio_platform u300_gpio_plat = {
.ports = 7,
.gpio_base = 0,
};
static struct platform_device gpio_device = {
.name = "u300-gpio",
.id = -1,
.num_resources = ARRAY_SIZE(gpio_resources),
.resource = gpio_resources,
.dev = {
.platform_data = &u300_gpio_plat,
},
};
static struct platform_device keypad_device = {
.name = "keypad",
.id = -1,
.num_resources = ARRAY_SIZE(keypad_resources),
.resource = keypad_resources,
};
static struct platform_device rtc_device = {
.name = "rtc-coh901331",
.id = -1,
.num_resources = ARRAY_SIZE(rtc_resources),
.resource = rtc_resources,
};
static struct mtd_partition u300_partitions[] = {
{
.name = "bootrecords",
.offset = 0,
.size = SZ_128K,
},
{
.name = "free",
.offset = SZ_128K,
.size = 8064 * SZ_1K,
},
{
.name = "platform",
.offset = 8192 * SZ_1K,
.size = 253952 * SZ_1K,
},
};
static struct fsmc_nand_platform_data nand_platform_data = {
.partitions = u300_partitions,
.nr_partitions = ARRAY_SIZE(u300_partitions),
.options = NAND_SKIP_BBTSCAN,
.width = FSMC_NAND_BW8,
};
static struct platform_device nand_device = {
.name = "fsmc-nand",
.id = -1,
.resource = fsmc_resources,
.num_resources = ARRAY_SIZE(fsmc_resources),
.dev = {
.platform_data = &nand_platform_data,
},
};
static struct platform_device dma_device = {
.name = "coh901318",
.id = -1,
.resource = dma_resource,
.num_resources = ARRAY_SIZE(dma_resource),
.dev = {
.coherent_dma_mask = ~0,
},
};
static unsigned long pin_pullup_conf[] = { static unsigned long pin_pullup_conf[] = {
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1), PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
}; };
@ -467,61 +219,6 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
pin_highz_conf), pin_highz_conf),
}; };
/*
* Notice that AMBA devices are initialized before platform devices.
*
*/
static struct platform_device *platform_devs[] __initdata = {
&dma_device,
&i2c0_device,
&i2c1_device,
&keypad_device,
&rtc_device,
&pinctrl_device,
&gpio_device,
&nand_device,
&wdog_device,
};
/*
* Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
* together so some interrupts are connected to the first one and some
* to the second one.
*/
static void __init u300_init_irq(void)
{
u32 mask[2] = {0, 0};
struct clk *clk;
int i;
/* initialize clocking early, we want to clock the INTCON */
u300_clk_init(U300_SYSCON_VBASE);
/* Bootstrap EMIF and SEMI clocks */
clk = clk_get_sys("pl172", NULL);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
clk = clk_get_sys("semi", NULL);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
/* Clock the interrupt controller */
clk = clk_get_sys("intcon", NULL);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
for (i = 0; i < U300_VIC_IRQS_END; i++)
set_bit(i, (unsigned long *) &mask[0]);
vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
mask[0], mask[0]);
vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
mask[1], mask[1]);
}
/*
* U300 platforms peripheral handling
*/
struct db_chip { struct db_chip {
u16 chipid; u16 chipid;
const char *name; const char *name;
@ -578,7 +275,7 @@ static void __init u300_init_check_chip(void)
const char unknown[] = "UNKNOWN"; const char unknown[] = "UNKNOWN";
/* Read out and print chip ID */ /* Read out and print chip ID */
val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR); val = readw(syscon_base + U300_SYSCON_CIDR);
/* This is in funky bigendian order... */ /* This is in funky bigendian order... */
val = (val & 0xFFU) << 8 | (val >> 8); val = (val & 0xFFU) << 8 | (val >> 8);
chip = db_chips; chip = db_chips;
@ -600,74 +297,6 @@ static void __init u300_init_check_chip(void)
} }
} }
/*
* Some devices and their resources require reserved physical memory from
* the end of the available RAM. This function traverses the list of devices
* and assigns actual addresses to these.
*/
static void __init u300_assign_physmem(void)
{
unsigned long curr_start = __pa(high_memory);
int i, j;
for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
for (j = 0; j < platform_devs[i]->num_resources; j++) {
struct resource *const res =
&platform_devs[i]->resource[j];
if (IORESOURCE_MEM == res->flags &&
0 == res->start) {
res->start = curr_start;
res->end += curr_start;
curr_start += resource_size(res);
printk(KERN_INFO "core.c: Mapping RAM " \
"%#x-%#x to device %s:%s\n",
res->start, res->end,
platform_devs[i]->name, res->name);
}
}
}
}
static void __init u300_init_machine(void)
{
int i;
u16 val;
/* Check what platform we run and print some status information */
u300_init_check_chip();
/* Initialize SPI device with some board specifics */
u300_spi_init(&pl022_device);
/* Register the AMBA devices in the AMBA bus abstraction layer */
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
u300_assign_physmem();
/* Initialize pinmuxing */
pinctrl_register_mappings(u300_pinmux_map,
ARRAY_SIZE(u300_pinmux_map));
/* Register subdevices on the I2C buses */
u300_i2c_register_board_devices();
/* Register the platform devices */
platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
/* Register subdevices on the SPI bus */
u300_spi_register_board_devices();
/* Enable SEMI self refresh */
val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
}
/* Forward declare this function from the watchdog */ /* Forward declare this function from the watchdog */
void coh901327_watchdog_reset(void); void coh901327_watchdog_reset(void);
@ -688,13 +317,99 @@ static void u300_restart(char mode, const char *cmd)
while (1); while (1);
} }
MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board") /* These are mostly to get the right device names for the clock lookups */
/* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
.atag_offset = 0x100, OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
"pinctrl-u300", NULL),
OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
"u300-gpio", NULL),
OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
"coh901327_wdog", NULL),
OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
"rtc-coh901331", NULL),
OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
"coh901318", NULL),
OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
"fsmc-nand", NULL),
OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
"uart0", NULL),
OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
"uart1", NULL),
OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
"pl022", NULL),
OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
"stu300.0", NULL),
OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
"stu300.1", NULL),
OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
"mmci", NULL),
{ /* sentinel */ },
};
static void __init u300_init_irq_dt(void)
{
struct device_node *syscon;
struct clk *clk;
syscon = of_find_node_by_path("/syscon@c0011000");
if (!syscon) {
pr_crit("could not find syscon node\n");
return;
}
syscon_base = of_iomap(syscon, 0);
if (!syscon_base) {
pr_crit("could not remap syscon\n");
return;
}
/* initialize clocking early, we want to clock the INTCON */
u300_clk_init(syscon_base);
/* Bootstrap EMIF and SEMI clocks */
clk = clk_get_sys("pl172", NULL);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
clk = clk_get_sys("semi", NULL);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
/* Clock the interrupt controller */
clk = clk_get_sys("intcon", NULL);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
irqchip_init();
}
static void __init u300_init_machine_dt(void)
{
u16 val;
/* Check what platform we run and print some status information */
u300_init_check_chip();
/* Initialize pinmuxing */
pinctrl_register_mappings(u300_pinmux_map,
ARRAY_SIZE(u300_pinmux_map));
of_platform_populate(NULL, of_default_bus_match_table,
u300_auxdata_lookup, NULL);
/* Enable SEMI self refresh */
val = readw(syscon_base + U300_SYSCON_SMCR) |
U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
writew(val, syscon_base + U300_SYSCON_SMCR);
}
static const char * u300_board_compat[] = {
"stericsson,u300",
NULL,
};
DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
.map_io = u300_map_io, .map_io = u300_map_io,
.nr_irqs = 0, .init_irq = u300_init_irq_dt,
.init_irq = u300_init_irq, .init_time = clocksource_of_init,
.init_time = u300_timer_init, .init_machine = u300_init_machine_dt,
.init_machine = u300_init_machine,
.restart = u300_restart, .restart = u300_restart,
.dt_compat = u300_board_compat,
MACHINE_END MACHINE_END

20
arch/arm/mach-u300/dummyspichip.c
View File

@ -263,28 +263,22 @@ static int pl022_dummy_remove(struct spi_device *spi)
return 0; return 0;
} }
static const struct of_device_id pl022_dummy_dt_match[] = {
{ .compatible = "arm,pl022-dummy" },
{},
};
static struct spi_driver pl022_dummy_driver = { static struct spi_driver pl022_dummy_driver = {
.driver = { .driver = {
.name = "spi-dummy", .name = "spi-dummy",
.owner = THIS_MODULE, .owner = THIS_MODULE,
.of_match_table = pl022_dummy_dt_match,
}, },
.probe = pl022_dummy_probe, .probe = pl022_dummy_probe,
.remove = pl022_dummy_remove, .remove = pl022_dummy_remove,
}; };
static int __init pl022_init_dummy(void) module_spi_driver(pl022_dummy_driver);
{
return spi_register_driver(&pl022_dummy_driver);
}
static void __exit pl022_exit_dummy(void)
{
spi_unregister_driver(&pl022_dummy_driver);
}
module_init(pl022_init_dummy);
module_exit(pl022_exit_dummy);
MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver"); MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver");
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");

285
arch/arm/mach-u300/i2c.c
View File

@ -1,285 +0,0 @@
/*
* arch/arm/mach-u300/i2c.c
*
* Copyright (C) 2009-2012 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
*
* Register board i2c devices
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/mfd/ab3100.h>
#include <linux/regulator/machine.h>
#include <linux/amba/bus.h>
#include <mach/irqs.h>
/*
* Initial settings of ab3100 registers.
* Common for below LDO regulator settings are that
* bit 7-5 controls voltage. Bit 4 turns regulator ON(1) or OFF(0).
* Bit 3-2 controls sleep enable and bit 1-0 controls sleep mode.
*/
/* LDO_A 0x16: 2.75V, ON, SLEEP_A, SLEEP OFF GND */
#define LDO_A_SETTING 0x16
/* LDO_C 0x10: 2.65V, ON, SLEEP_A or B, SLEEP full power */
#define LDO_C_SETTING 0x10
/* LDO_D 0x10: 2.65V, ON, sleep mode not used */
#define LDO_D_SETTING 0x10
/* LDO_E 0x10: 1.8V, ON, SLEEP_A or B, SLEEP full power */
#define LDO_E_SETTING 0x10
/* LDO_E SLEEP 0x00: 1.8V, not used, SLEEP_A or B, not used */
#define LDO_E_SLEEP_SETTING 0x00
/* LDO_F 0xD0: 2.5V, ON, SLEEP_A or B, SLEEP full power */
#define LDO_F_SETTING 0xD0
/* LDO_G 0x00: 2.85V, OFF, SLEEP_A or B, SLEEP full power */
#define LDO_G_SETTING 0x00
/* LDO_H 0x18: 2.75V, ON, SLEEP_B, SLEEP full power */
#define LDO_H_SETTING 0x18
/* LDO_K 0x00: 2.75V, OFF, SLEEP_A or B, SLEEP full power */
#define LDO_K_SETTING 0x00
/* LDO_EXT 0x00: Voltage not set, OFF, not used, not used */
#define LDO_EXT_SETTING 0x00
/* BUCK 0x7D: 1.2V, ON, SLEEP_A and B, SLEEP low power */
#define BUCK_SETTING 0x7D
/* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */
#define BUCK_SLEEP_SETTING 0xAC
#ifdef CONFIG_AB3100_CORE
static struct regulator_consumer_supply supply_ldo_c[] = {
{
.dev_name = "ab3100-codec",
.supply = "vaudio", /* Powers the codec */
},
};
/*
* This one needs to be a supply so we can turn it off
* in order to shut down the system.
*/
static struct regulator_consumer_supply supply_ldo_d[] = {
{
.supply = "vana15", /* Powers the SoC (CPU etc) */
},
};
static struct regulator_consumer_supply supply_ldo_g[] = {
{
.dev_name = "mmci",
.supply = "vmmc", /* Powers MMC/SD card */
},
};
static struct regulator_consumer_supply supply_ldo_h[] = {
{
.dev_name = "xgam_pdi",
.supply = "vdisp", /* Powers camera, display etc */
},
};
static struct regulator_consumer_supply supply_ldo_k[] = {
{
.dev_name = "irda",
.supply = "vir", /* Power IrDA */
},
};
/*
* This is a placeholder for whoever wish to use the
* external power.
*/
static struct regulator_consumer_supply supply_ldo_ext[] = {
{
.supply = "vext", /* External power */
},
};
/* Preset (hardware defined) voltages for these regulators */
#define LDO_A_VOLTAGE 2750000
#define LDO_C_VOLTAGE 2650000
#define LDO_D_VOLTAGE 2650000
static struct ab3100_platform_data ab3100_plf_data = {
.reg_constraints = {
/* LDO A routing and constraints */
{
.constraints = {
.name = "vrad",
.min_uV = LDO_A_VOLTAGE,
.max_uV = LDO_A_VOLTAGE,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.always_on = 1,
.boot_on = 1,
},
},
/* LDO C routing and constraints */
{
.constraints = {
.min_uV = LDO_C_VOLTAGE,
.max_uV = LDO_C_VOLTAGE,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_c),
.consumer_supplies = supply_ldo_c,
},
/* LDO D routing and constraints */
{
.constraints = {
.min_uV = LDO_D_VOLTAGE,
.max_uV = LDO_D_VOLTAGE,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
/*
* Actually this is boot_on but we need
* to reference count it externally to
* be able to shut down the system.
*/
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_d),
.consumer_supplies = supply_ldo_d,
},
/* LDO E routing and constraints */
{
.constraints = {
.name = "vio",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.always_on = 1,
.boot_on = 1,
},
},
/* LDO F routing and constraints */
{
.constraints = {
.name = "vana25",
.min_uV = 2500000,
.max_uV = 2500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.always_on = 1,
.boot_on = 1,
},
},
/* LDO G routing and constraints */
{
.constraints = {
.min_uV = 1500000,
.max_uV = 2850000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_g),
.consumer_supplies = supply_ldo_g,
},
/* LDO H routing and constraints */
{
.constraints = {
.min_uV = 1200000,
.max_uV = 2750000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_h),
.consumer_supplies = supply_ldo_h,
},
/* LDO K routing and constraints */
{
.constraints = {
.min_uV = 1800000,
.max_uV = 2750000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_k),
.consumer_supplies = supply_ldo_k,
},
/* External regulator interface. No fixed voltage specified.
* If we knew the voltage of the external regulator and it
* was connected on the board, we could add the (fixed)
* voltage for it here.
*/
{
.constraints = {
.min_uV = 0,
.max_uV = 0,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_ext),
.consumer_supplies = supply_ldo_ext,
},
/* Buck converter routing and constraints */
{
.constraints = {
.name = "vcore",
.min_uV = 1200000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.boot_on = 1,
},
},
},
.reg_initvals = {
LDO_A_SETTING,
LDO_C_SETTING,
LDO_E_SETTING,
LDO_E_SLEEP_SETTING,
LDO_F_SETTING,
LDO_G_SETTING,
LDO_H_SETTING,
LDO_K_SETTING,
LDO_EXT_SETTING,
BUCK_SETTING,
BUCK_SLEEP_SETTING,
LDO_D_SETTING,
},
};
#endif
static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
#ifdef CONFIG_AB3100_CORE
{
.type = "ab3100",
.addr = 0x48,
.irq = IRQ_U300_IRQ0_EXT,
.platform_data = &ab3100_plf_data,
},
#else
{ },
#endif
};
static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
{
.type = "fwcam",
.addr = 0x10,
},
{
.type = "fwcam",
.addr = 0x5d,
},
};
void __init u300_i2c_register_board_devices(void)
{
i2c_register_board_info(0, bus0_i2c_board_info,
ARRAY_SIZE(bus0_i2c_board_info));
/*
* This makes the core shut down all unused regulators
* after all the initcalls have completed.
*/
regulator_has_full_constraints();
i2c_register_board_info(1, bus1_i2c_board_info,
ARRAY_SIZE(bus1_i2c_board_info));
}

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arch/arm/mach-u300/i2c.h
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/*
* arch/arm/mach-u300/i2c.h
*
* Copyright (C) 2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
*
* Register board i2c devices
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef MACH_U300_I2C_H
#define MACH_U300_I2C_H
#ifdef CONFIG_I2C_STU300
void __init u300_i2c_register_board_devices(void);
#else
/* Compile out this stuff if no I2C adapter is available */
static inline void __init u300_i2c_register_board_devices(void)
{
}
#endif
#endif

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arch/arm/mach-u300/include/mach/hardware.h
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/*
* arch/arm/mach-u300/include/mach/hardware.h
*/
#include <asm/sizes.h>
#include <mach/u300-regs.h>

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arch/arm/mach-u300/include/mach/irqs.h
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/*
*
* arch/arm/mach-u300/include/mach/irqs.h
*
*
* Copyright (C) 2006-2012 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* IRQ channel definitions for the U300 platforms.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
#define IRQ_U300_INTCON0_START 32
#define IRQ_U300_INTCON1_START 64
/* These are on INTCON0 - 30 lines */
#define IRQ_U300_IRQ0_EXT 32
#define IRQ_U300_IRQ1_EXT 33
#define IRQ_U300_DMA 34
#define IRQ_U300_VIDEO_ENC_0 35
#define IRQ_U300_VIDEO_ENC_1 36
#define IRQ_U300_AAIF_RX 37
#define IRQ_U300_AAIF_TX 38
#define IRQ_U300_AAIF_VGPIO 39
#define IRQ_U300_AAIF_WAKEUP 40
#define IRQ_U300_PCM_I2S0_FRAME 41
#define IRQ_U300_PCM_I2S0_FIFO 42
#define IRQ_U300_PCM_I2S1_FRAME 43
#define IRQ_U300_PCM_I2S1_FIFO 44
#define IRQ_U300_XGAM_GAMCON 45
#define IRQ_U300_XGAM_CDI 46
#define IRQ_U300_XGAM_CDICON 47
#define IRQ_U300_XGAM_PDI 49
#define IRQ_U300_XGAM_PDICON 50
#define IRQ_U300_XGAM_GAMEACC 51
#define IRQ_U300_XGAM_MCIDCT 52
#define IRQ_U300_APEX 53
#define IRQ_U300_UART0 54
#define IRQ_U300_SPI 55
#define IRQ_U300_TIMER_APP_OS 56
#define IRQ_U300_TIMER_APP_DD 57
#define IRQ_U300_TIMER_APP_GP1 58
#define IRQ_U300_TIMER_APP_GP2 59
#define IRQ_U300_TIMER_OS 60
#define IRQ_U300_TIMER_MS 61
#define IRQ_U300_KEYPAD_KEYBF 62
#define IRQ_U300_KEYPAD_KEYBR 63
/* These are on INTCON1 - 32 lines */
#define IRQ_U300_GPIO_PORT0 64
#define IRQ_U300_GPIO_PORT1 65
#define IRQ_U300_GPIO_PORT2 66
/* These are for DB3150, DB3200 and DB3350 */
#define IRQ_U300_WDOG 67
#define IRQ_U300_EVHIST 68
#define IRQ_U300_MSPRO 69
#define IRQ_U300_MMCSD_MCIINTR0 70
#define IRQ_U300_MMCSD_MCIINTR1 71
#define IRQ_U300_I2C0 72
#define IRQ_U300_I2C1 73
#define IRQ_U300_RTC 74
#define IRQ_U300_NFIF 75
#define IRQ_U300_NFIF2 76
/* The DB3350-specific interrupt lines */
#define IRQ_U300_ISP_F0 77
#define IRQ_U300_ISP_F1 78
#define IRQ_U300_ISP_F2 79
#define IRQ_U300_ISP_F3 80
#define IRQ_U300_ISP_F4 81
#define IRQ_U300_GPIO_PORT3 82
#define IRQ_U300_SYSCON_PLL_LOCK 83
#define IRQ_U300_UART1 84
#define IRQ_U300_GPIO_PORT4 85
#define IRQ_U300_GPIO_PORT5 86
#define IRQ_U300_GPIO_PORT6 87
#define U300_VIC_IRQS_END 88
#endif

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arch/arm/mach-u300/include/mach/syscon.h
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/*
*
* arch/arm/mach-u300/include/mach/syscon.h
*
*
* Copyright (C) 2008-2012 ST-Ericsson AB
*
* Author: Rickard Andersson <rickard.andersson@stericsson.com>
*/
#ifndef __MACH_SYSCON_H
#define __MACH_SYSCON_H
/*
* All register defines for SYSCON registers that concerns individual
* block clocks and reset lines are registered here. This is because
* we don't want any other file to try to fool around with this stuff.
*/
/* APP side SYSCON registers */
/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
/* CLK Control Register 16bit (R/W) */
#define U300_SYSCON_CCR (0x0000)
#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
/* CLK Status Register 16bit (R/W) */
#define U300_SYSCON_CSR (0x0004)
#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
/* Reset lines for SLOW devices 16bit (R/W) */
#define U300_SYSCON_RSR (0x0014)
#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
/* Reset lines for FAST devices 16bit (R/W) */
#define U300_SYSCON_RFR (0x0018)
#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
/* Reset lines for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_RRR (0x001c)
#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
/* Clock enable for SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CESR (0x0020)
#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
/* Clock enable for FAST peripherals 16bit (R/W) */
#define U300_SYSCON_CEFR (0x0024)
#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
/* Clock enable for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CERR (0x0028)
#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
/* Single block clock enable 16bit (-/W) */
#define U300_SYSCON_SBCER (0x002c)
#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
/* Single block clock disable 16bit (-/W) */
#define U300_SYSCON_SBCDR (0x0030)
/* Same values as above for SBCER */
/* Clock force SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CFSR (0x003c)
#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
/* Clock force FAST peripherals 16bit (R/W) */
#define U300_SYSCON_CFFR (0x40)
/* Values not defined. Define if you want to use them. */
/* Clock force the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CFRR (0x44)
#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
/* PLL208 Frequency Control 16bit (R/W) */
#define U300_SYSCON_PFCR (0x48)
#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
/* Power Management Control 16bit (R/W) */
#define U300_SYSCON_PMCR (0x50)
#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
/*
* All other clocking registers moved to clock.c!
*/
/* Reset Out 16bit (R/W) */
#define U300_SYSCON_RCR (0x6c)
#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
/* EMIF Slew Rate Control 16bit (R/W) */
#define U300_SYSCON_SRCLR (0x70)
#define U300_SYSCON_SRCLR_MASK (0x03FF)
#define U300_SYSCON_SRCLR_VALUE (0x03FF)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
/* EMIF Clock Control Register 16bit (R/W) */
#define U300_SYSCON_ECCR (0x0078)
#define U300_SYSCON_ECCR_MASK (0x000F)
#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
/* Step one for killing the applications system 16bit (-/W) */
#define U300_SYSCON_KA1R (0x0080)
#define U300_SYSCON_KA1R_MASK (0xFFFF)
#define U300_SYSCON_KA1R_VALUE (0xFFFF)
/* Step two for killing the application system 16bit (-/W) */
#define U300_SYSCON_KA2R (0x0084)
#define U300_SYSCON_KA2R_MASK (0xFFFF)
#define U300_SYSCON_KA2R_VALUE (0xFFFF)
/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
#define U300_SYSCON_MMF0R (0x90)
#define U300_SYSCON_MMF0R_MASK (0x00FF)
#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
#define U300_SYSCON_MMF1R (0x94)
#define U300_SYSCON_MMF1R_MASK (0x00FF)
#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
/* AAIF control register 16 bit (R/W) */
#define U300_SYSCON_AAIFCR (0x98)
#define U300_SYSCON_AAIFCR_MASK (0x0003)
#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003)
#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000)
#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001)
#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002)
#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003)
/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
#define U300_SYSCON_MMCR (0x9C)
#define U300_SYSCON_MMCR_MASK (0x0003)
#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
/* Pull up/down control (R/W) */
#define U300_SYSCON_PUCR (0x104)
#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE (0x0200)
#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE (0x0100)
#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080)
#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040)
#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F)
/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
#define U300_SYSCON_S0CCR (0x120)
#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
#define U300_SYSCON_S1CCR (0x124)
#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
#define U300_SYSCON_S2CCR (0x128)
#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
#define U300_SYSCON_MCR (0x12c)
#define U300_SYSCON_MCR_FIELD_MASK (0x00FF)
#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0)
#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000)
#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040)
#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0)
#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030)
#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000)
#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010)
#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020)
#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030)
#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C)
#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000)
#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004)
#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008)
#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C)
#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002)
#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001)
/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
#define U300_SYSCON_PICR (0x0130)
#define U300_SYSCON_PICR_MASK (0x00FF)
#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
#define U300_SYSCON_PISR (0x0134)
#define U300_SYSCON_PISR_MASK (0x000F)
#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
#define U300_SYSCON_PICLR (0x0138)
#define U300_SYSCON_PICLR_MASK (0x000F)
#define U300_SYSCON_PICLR_RWMASK (0x0000)
#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
/* CAMIF_CONTROL 16 bit (-/W) */
#define U300_SYSCON_CICR (0x013C)
#define U300_SYSCON_CICR_MASK (0x0FFF)
#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK (0x0F00)
#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1 (0x0C00)
#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0 (0x0300)
#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK (0x00F0)
#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1 (0x00C0)
#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0 (0x0030)
#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK (0x000F)
#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1 (0x000C)
#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0 (0x0003)
/* Clock activity observability register 0 */
#define U300_SYSCON_C0OAR (0x140)
#define U300_SYSCON_C0OAR_MASK (0xFFFF)
#define U300_SYSCON_C0OAR_VALUE (0xFFFF)
#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
#define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
#define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
/* Clock activity observability register 1 */
#define U300_SYSCON_C1OAR (0x144)
#define U300_SYSCON_C1OAR_MASK (0x3FFE)
#define U300_SYSCON_C1OAR_VALUE (0x3FFE)
#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
#define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
#define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
#define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
/* Clock activity observability register 2 */
#define U300_SYSCON_C2OAR (0x148)
#define U300_SYSCON_C2OAR_MASK (0x0FFF)
#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
/* Chip ID register 16bit (R/-) */
#define U300_SYSCON_CIDR (0x400)
/* Video IRQ clear 16bit (R/W) */
#define U300_SYSCON_VICR (0x404)
#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002)
#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001)
/* SMCR */
#define U300_SYSCON_SMCR (0x4d0)
#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
#define U300_SYSCON_CSDR (0x4f0)
#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
/* PRINT_CONTROL Print Control 16bit (R/-) */
#define U300_SYSCON_PCR (0x4f8)
#define U300_SYSCON_PCR_SERV_IND (0x0001)
/* BOOT_CONTROL 16bit (R/-) */
#define U300_SYSCON_BCR (0x4fc)
#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
/* CPU clock defines */
/**
* CPU high frequency in MHz
*/
#define SYSCON_CPU_CLOCK_HIGH 208
/**
* CPU medium frequency in MHz
*/
#define SYSCON_CPU_CLOCK_MEDIUM 52
/**
* CPU low frequency in MHz
*/
#define SYSCON_CPU_CLOCK_LOW 13
/* EMIF clock defines */
/**
* EMIF high frequency in MHz
*/
#define SYSCON_EMIF_CLOCK_HIGH 104
/**
* EMIF medium frequency in MHz
*/
#define SYSCON_EMIF_CLOCK_MEDIUM 52
/**
* EMIF low frequency in MHz
*/
#define SYSCON_EMIF_CLOCK_LOW 13
/* AHB clock defines */
/**
* AHB high frequency in MHz
*/
#define SYSCON_AHB_CLOCK_HIGH 52
/**
* AHB medium frequency in MHz
*/
#define SYSCON_AHB_CLOCK_MEDIUM 26
/**
* AHB low frequency in MHz
*/
#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */
enum syscon_busmaster {
SYSCON_BM_DMAC,
SYSCON_BM_XGAM,
SYSCON_BM_VIDEO_ENC
};
/* Selectr a resistor or a set of resistors */
enum syscon_pull_up_down {
SYSCON_PU_KEY_IN_EN,
SYSCON_PU_EMIF_1_8_BIT_EN,
SYSCON_PU_EMIF_1_16_BIT_EN,
SYSCON_PU_EMIF_1_NFIF_READY_EN,
SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
};
/*
* Note that this array must match the order of the array "clk_reg"
* in syscon.c
*/
enum syscon_clk {
SYSCON_CLKCONTROL_SLOW_BRIDGE,
SYSCON_CLKCONTROL_UART,
SYSCON_CLKCONTROL_BTR,
SYSCON_CLKCONTROL_EH,
SYSCON_CLKCONTROL_GPIO,
SYSCON_CLKCONTROL_KEYPAD,
SYSCON_CLKCONTROL_APP_TIMER,
SYSCON_CLKCONTROL_ACC_TIMER,
SYSCON_CLKCONTROL_FAST_BRIDGE,
SYSCON_CLKCONTROL_I2C0,
SYSCON_CLKCONTROL_I2C1,
SYSCON_CLKCONTROL_I2S0,
SYSCON_CLKCONTROL_I2S1,
SYSCON_CLKCONTROL_MMC,
SYSCON_CLKCONTROL_SPI,
SYSCON_CLKCONTROL_I2S0_CORE,
SYSCON_CLKCONTROL_I2S1_CORE,
SYSCON_CLKCONTROL_UART1,
SYSCON_CLKCONTROL_AAIF,
SYSCON_CLKCONTROL_AHB,
SYSCON_CLKCONTROL_APEX,
SYSCON_CLKCONTROL_CPU,
SYSCON_CLKCONTROL_DMA,
SYSCON_CLKCONTROL_EMIF,
SYSCON_CLKCONTROL_NAND_IF,
SYSCON_CLKCONTROL_VIDEO_ENC,
SYSCON_CLKCONTROL_XGAM,
SYSCON_CLKCONTROL_SEMI,
SYSCON_CLKCONTROL_AHB_SUBSYS,
SYSCON_CLKCONTROL_MSPRO
};
enum syscon_sysclk_mode {
SYSCON_SYSCLK_DISABLED,
SYSCON_SYSCLK_M_CLK,
SYSCON_SYSCLK_ACC_FSM,
SYSCON_SYSCLK_PLL60_48,
SYSCON_SYSCLK_PLL60_60,
SYSCON_SYSCLK_ACC_PLL208,
SYSCON_SYSCLK_APP_PLL13,
SYSCON_SYSCLK_APP_FSM,
SYSCON_SYSCLK_RTC,
SYSCON_SYSCLK_APP_PLL208
};
enum syscon_sysclk_req {
SYSCON_SYSCLKREQ_DISABLED,
SYSCON_SYSCLKREQ_ACTIVE_LOW,
SYSCON_SYSCLKREQ_MONITOR
};
enum syscon_clk_mode {
SYSCON_CLKMODE_OFF,
SYSCON_CLKMODE_DEFAULT,
SYSCON_CLKMODE_LOW,
SYSCON_CLKMODE_MEDIUM,
SYSCON_CLKMODE_HIGH,
SYSCON_CLKMODE_PERMANENT,
SYSCON_CLKMODE_ON,
};
enum syscon_call_mode {
SYSCON_CLKCALL_NOWAIT,
SYSCON_CLKCALL_WAIT,
};
int syscon_dc_on(bool keep_power_on);
int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
bool active);
bool syscon_get_busmaster_active_state(void);
int syscon_set_sleep_mask(enum syscon_clk,
bool sleep_ctrl);
int syscon_config_sysclk(u32 sysclk,
enum syscon_sysclk_mode sysclkmode,
bool inverse,
u32 divisor,
enum syscon_sysclk_req sysclkreq);
bool syscon_can_turn_off_semi_clock(void);
/* This function is restricted to core.c */
int syscon_request_normal_power(bool req);
/* This function is restricted to be used by platform_speed.c */
int syscon_speed_request(enum syscon_call_mode wait_mode,
enum syscon_clk_mode req_clk_mode);
#endif /* __MACH_SYSCON_H */

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arch/arm/mach-u300/include/mach/timex.h
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/*
*
* arch/arm/mach-u300/include/mach/timex.h
*
*
* Copyright (C) 2006-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Platform tick rate definition.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef __MACH_TIMEX_H
#define __MACH_TIMEX_H
/* This is for the APP OS GP1 (General Purpose 1) timer */
#define CLOCK_TICK_RATE 1000000
#endif

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arch/arm/mach-u300/include/mach/u300-regs.h
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/*
*
* arch/arm/mach-u300/include/mach/u300-regs.h
*
*
* Copyright (C) 2006-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Basic register address definitions in physical memory and
* some block definitions for core devices like the timer.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef __MACH_U300_REGS_H
#define __MACH_U300_REGS_H
/*
* These are the large blocks of memory allocated for I/O.
* the defines are used for setting up the I/O memory mapping.
*/
/* NAND Flash CS0 */
#define U300_NAND_CS0_PHYS_BASE 0x80000000
/* NFIF */
#define U300_NAND_IF_PHYS_BASE 0x9f800000
/* ALE, CLE offset for FSMC NAND */
#define PLAT_NAND_CLE (1 << 16)
#define PLAT_NAND_ALE (1 << 17)
/* AHB Peripherals */
#define U300_AHB_PER_PHYS_BASE 0xa0000000
#define U300_AHB_PER_VIRT_BASE 0xff010000
/* FAST Peripherals */
#define U300_FAST_PER_PHYS_BASE 0xc0000000
#define U300_FAST_PER_VIRT_BASE 0xff020000
/* SLOW Peripherals */
#define U300_SLOW_PER_PHYS_BASE 0xc0010000
#define U300_SLOW_PER_VIRT_BASE 0xff000000
/* Boot ROM */
#define U300_BOOTROM_PHYS_BASE 0xffff0000
#define U300_BOOTROM_VIRT_BASE 0xffff0000
/* SEMI config base */
#define U300_SEMI_CONFIG_BASE 0x2FFE0000
/*
* AHB peripherals
*/
/* AHB Peripherals Bridge Controller */
#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
/* Vectored Interrupt Controller 0, servicing 32 interrupts */
#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
/* Vectored Interrupt Controller 1, servicing 32 interrupts */
#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
/* Memory Stick Pro (MSPRO) controller */
#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
/* EMIF Configuration Area */
#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
/*
* FAST peripherals
*/
/* FAST bridge control */
#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
/* MMC/SD controller */
#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
/* PCM I2S0 controller */
#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
/* PCM I2S1 controller */
#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
/* I2C0 controller */
#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
/* I2C1 controller */
#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
/* SPI controller */
#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
/* Fast UART1 on U335 only */
#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
/*
* SLOW peripherals
*/
/* SLOW bridge control */
#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
/* SYSCON */
#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
/* Watchdog */
#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
/* UART0 */
#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
/* APP side special timer */
#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
/* Keypad */
#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
/* GPIO */
#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
/* RTC */
#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
/* Bus tracer */
#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
/* Event handler (hardware queue) */
#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
/* Genric Timer */
#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
/* PPM */
#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
/*
* REST peripherals
*/
/* ISP (image signal processor) */
#define U300_ISP_BASE (0xA0008000)
/* DMA Controller base */
#define U300_DMAC_BASE (0xC0020000)
/* MSL Base */
#define U300_MSL_BASE (0xc0022000)
/* APEX Base */
#define U300_APEX_BASE (0xc0030000)
/* Video Encoder Base */
#define U300_VIDEOENC_BASE (0xc0080000)
/* XGAM Base */
#define U300_XGAM_BASE (0xd0000000)
#endif

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arch/arm/mach-u300/include/mach/uncompress.h
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/*
* arch/arm/mach-u300/include/mach/uncompress.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define AMBA_UART_DR (*(volatile unsigned char *)0xc0013000)
#define AMBA_UART_LCRH (*(volatile unsigned char *)0xc001302C)
#define AMBA_UART_CR (*(volatile unsigned char *)0xc0013030)
#define AMBA_UART_FR (*(volatile unsigned char *)0xc0013018)
/*
* This does not append a newline
*/
static inline void putc(int c)
{
while (AMBA_UART_FR & (1 << 5))
barrier();
AMBA_UART_DR = c;
}
static inline void flush(void)
{
while (AMBA_UART_FR & (1 << 3))
barrier();
}
/*
* nothing to do
*/
#define arch_decomp_setup()

67
arch/arm/mach-u300/regulator.c
View File

@ -10,11 +10,18 @@
#include <linux/device.h> #include <linux/device.h>
#include <linux/signal.h> #include <linux/signal.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/consumer.h> #include <linux/regulator/consumer.h>
/* Those are just for writing in syscon */ #include <linux/mfd/syscon.h>
#include <linux/io.h> #include <linux/regmap.h>
#include <mach/hardware.h>
#include <mach/syscon.h> /* Power Management Control 16bit (R/W) */
#define U300_SYSCON_PMCR (0x50)
#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
/* /*
* Regulators that power the board and chip and which are * Regulators that power the board and chip and which are
@ -47,13 +54,28 @@ void u300_pm_poweroff(void)
/* /*
* Hog the regulators needed to power up the board. * Hog the regulators needed to power up the board.
*/ */
static int __init u300_init_boardpower(void) static int __init __u300_init_boardpower(struct platform_device *pdev)
{ {
struct device_node *np = pdev->dev.of_node;
struct device_node *syscon_np;
struct regmap *regmap;
int err; int err;
u32 val;
pr_info("U300: setting up board power\n"); pr_info("U300: setting up board power\n");
main_power_15 = regulator_get(NULL, "vana15");
syscon_np = of_parse_phandle(np, "syscon", 0);
if (!syscon_np) {
pr_crit("U300: no syscon node\n");
return -ENODEV;
}
regmap = syscon_node_to_regmap(syscon_np);
if (!regmap) {
pr_crit("U300: could not locate syscon regmap\n");
return -ENODEV;
}
main_power_15 = regulator_get(&pdev->dev, "vana15");
if (IS_ERR(main_power_15)) { if (IS_ERR(main_power_15)) {
pr_err("could not get vana15"); pr_err("could not get vana15");
return PTR_ERR(main_power_15); return PTR_ERR(main_power_15);
@ -72,9 +94,8 @@ static int __init u300_init_boardpower(void)
* the rest of the U300 power management is implemented. * the rest of the U300 power management is implemented.
*/ */
pr_info("U300: disable system controller pull-up\n"); pr_info("U300: disable system controller pull-up\n");
val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR); regmap_update_bits(regmap, U300_SYSCON_PMCR,
val &= ~U300_SYSCON_PMCR_DCON_ENABLE; U300_SYSCON_PMCR_DCON_ENABLE, 0);
writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
/* Register globally exported PM poweroff hook */ /* Register globally exported PM poweroff hook */
pm_power_off = u300_pm_poweroff; pm_power_off = u300_pm_poweroff;
@ -82,7 +103,31 @@ static int __init u300_init_boardpower(void)
return 0; return 0;
} }
static int __init s365_board_probe(struct platform_device *pdev)
{
return __u300_init_boardpower(pdev);
}
static const struct of_device_id s365_board_match[] = {
{ .compatible = "stericsson,s365" },
{},
};
static struct platform_driver s365_board_driver = {
.driver = {
.name = "s365-board",
.owner = THIS_MODULE,
.of_match_table = s365_board_match,
},
};
/* /*
* So at module init time we hog the regulator! * So at module init time we hog the regulator!
*/ */
module_init(u300_init_boardpower); static int __init u300_init_boardpower(void)
{
return platform_driver_probe(&s365_board_driver,
s365_board_probe);
}
device_initcall(u300_init_boardpower);

102
arch/arm/mach-u300/spi.c
View File

@ -1,102 +0,0 @@
/*
* arch/arm/mach-u300/spi.c
*
* Copyright (C) 2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
*
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/spi/spi.h>
#include <linux/amba/pl022.h>
#include <linux/platform_data/dma-coh901318.h>
#include <linux/err.h>
/*
* The following is for the actual devices on the SSP/SPI bus
*/
#ifdef CONFIG_MACH_U300_SPIDUMMY
static void select_dummy_chip(u32 chipselect)
{
pr_debug("CORE: %s called with CS=0x%x (%s)\n",
__func__,
chipselect,
chipselect ? "unselect chip" : "select chip");
/*
* Here you would write the chip select value to the GPIO pins if
* this was a real chip (but this is a loopback dummy).
*/
}
struct pl022_config_chip dummy_chip_info = {
/* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
.com_mode = DMA_TRANSFER,
.iface = SSP_INTERFACE_MOTOROLA_SPI,
/* We can only act as master but SSP_SLAVE is possible in theory */
.hierarchy = SSP_MASTER,
/* 0 = drive TX even as slave, 1 = do not drive TX as slave */
.slave_tx_disable = 0,
.rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
.tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
.ctrl_len = SSP_BITS_12,
.wait_state = SSP_MWIRE_WAIT_ZERO,
.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
/*
* This is where you insert a call to a function to enable CS
* (usually GPIO) for a certain chip.
*/
.cs_control = select_dummy_chip,
};
#endif
static struct spi_board_info u300_spi_devices[] = {
#ifdef CONFIG_MACH_U300_SPIDUMMY
{
/* A dummy chip used for loopback tests */
.modalias = "spi-dummy",
/* Really dummy, pass in additional chip config here */
.platform_data = NULL,
/* This defines how the controller shall handle the device */
.controller_data = &dummy_chip_info,
/* .irq - no external IRQ routed from this device */
.max_speed_hz = 1000000,
.bus_num = 0, /* Only one bus on this chip */
.chip_select = 0,
/* Means SPI_CS_HIGH, change if e.g low CS */
.mode = SPI_MODE_1 | SPI_LOOP,
},
#endif
};
static struct pl022_ssp_controller ssp_platform_data = {
/* If you have several SPI buses this varies, we have only bus 0 */
.bus_id = 0,
/*
* On the APP CPU GPIO 4, 5 and 6 are connected as generic
* chip selects for SPI. (Same on U330, U335 and U365.)
* TODO: make sure the GPIO driver can select these properly
* and do padmuxing accordingly too.
*/
.num_chipselect = 3,
#ifdef CONFIG_COH901318
.enable_dma = 1,
.dma_filter = coh901318_filter_id,
.dma_rx_param = (void *) U300_DMA_SPI_RX,
.dma_tx_param = (void *) U300_DMA_SPI_TX,
#else
.enable_dma = 0,
#endif
};
void __init u300_spi_init(struct amba_device *adev)
{
adev->dev.platform_data = &ssp_platform_data;
}
void __init u300_spi_register_board_devices(void)
{
/* Register any SPI devices */
spi_register_board_info(u300_spi_devices, ARRAY_SIZE(u300_spi_devices));
}

26
arch/arm/mach-u300/spi.h
View File

@ -1,26 +0,0 @@
/*
* arch/arm/mach-u300/spi.h
*
* Copyright (C) 2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
*
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef SPI_H
#define SPI_H
#include <linux/amba/bus.h>
#ifdef CONFIG_SPI_PL022
void __init u300_spi_init(struct amba_device *adev);
void __init u300_spi_register_board_devices(void);
#else
/* Compile out SPI support if PL022 is not selected */
static inline void __init u300_spi_init(struct amba_device *adev)
{
}
static inline void __init u300_spi_register_board_devices(void)
{
}
#endif
#endif

113
arch/arm/mach-u300/timer.c
View File

@ -18,17 +18,15 @@
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/delay.h>
#include <mach/hardware.h> #include <linux/of_address.h>
#include <mach/irqs.h> #include <linux/of_irq.h>
/* Generic stuff */ /* Generic stuff */
#include <asm/sched_clock.h> #include <asm/sched_clock.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include "timer.h"
/* /*
* APP side special timer registers * APP side special timer registers
* This timer contains four timers which can fire an interrupt each. * This timer contains four timers which can fire an interrupt each.
@ -189,6 +187,8 @@
#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
#define US_PER_TICK ((1000000 + (HZ/2)) / HZ) #define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
static void __iomem *u300_timer_base;
/* /*
* The u300_set_mode() function is always called first, if we * The u300_set_mode() function is always called first, if we
* have oneshot timer active, the oneshot scheduling function * have oneshot timer active, the oneshot scheduling function
@ -201,28 +201,28 @@ static void u300_set_mode(enum clock_event_mode mode,
case CLOCK_EVT_MODE_PERIODIC: case CLOCK_EVT_MODE_PERIODIC:
/* Disable interrupts on GPT1 */ /* Disable interrupts on GPT1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Disable GP1 while we're reprogramming it. */ /* Disable GP1 while we're reprogramming it. */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); u300_timer_base + U300_TIMER_APP_DGPT1);
/* /*
* Set the periodic mode to a certain number of ticks per * Set the periodic mode to a certain number of ticks per
* jiffy. * jiffy.
*/ */
writel(TICKS_PER_JIFFY, writel(TICKS_PER_JIFFY,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); u300_timer_base + U300_TIMER_APP_GPT1TC);
/* /*
* Set continuous mode, so the timer keeps triggering * Set continuous mode, so the timer keeps triggering
* interrupts. * interrupts.
*/ */
writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS, writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); u300_timer_base + U300_TIMER_APP_SGPT1M);
/* Enable timer interrupts */ /* Enable timer interrupts */
writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Then enable the OS timer again */ /* Then enable the OS timer again */
writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); u300_timer_base + U300_TIMER_APP_EGPT1);
break; break;
case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_ONESHOT:
/* Just break; here? */ /* Just break; here? */
@ -233,33 +233,33 @@ static void u300_set_mode(enum clock_event_mode mode,
*/ */
/* Disable interrupts on GPT1 */ /* Disable interrupts on GPT1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Disable GP1 while we're reprogramming it. */ /* Disable GP1 while we're reprogramming it. */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); u300_timer_base + U300_TIMER_APP_DGPT1);
/* /*
* Expire far in the future, u300_set_next_event() will be * Expire far in the future, u300_set_next_event() will be
* called soon... * called soon...
*/ */
writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
/* We run one shot per tick here! */ /* We run one shot per tick here! */
writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); u300_timer_base + U300_TIMER_APP_SGPT1M);
/* Enable interrupts for this timer */ /* Enable interrupts for this timer */
writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Enable timer */ /* Enable timer */
writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); u300_timer_base + U300_TIMER_APP_EGPT1);
break; break;
case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_SHUTDOWN:
/* Disable interrupts on GP1 */ /* Disable interrupts on GP1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Disable GP1 */ /* Disable GP1 */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); u300_timer_base + U300_TIMER_APP_DGPT1);
break; break;
case CLOCK_EVT_MODE_RESUME: case CLOCK_EVT_MODE_RESUME:
/* Ignore this call */ /* Ignore this call */
@ -281,27 +281,27 @@ static int u300_set_next_event(unsigned long cycles,
{ {
/* Disable interrupts on GPT1 */ /* Disable interrupts on GPT1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Disable GP1 while we're reprogramming it. */ /* Disable GP1 while we're reprogramming it. */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); u300_timer_base + U300_TIMER_APP_DGPT1);
/* Reset the General Purpose timer 1. */ /* Reset the General Purpose timer 1. */
writel(U300_TIMER_APP_RGPT1_TIMER_RESET, writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); u300_timer_base + U300_TIMER_APP_RGPT1);
/* IRQ in n * cycles */ /* IRQ in n * cycles */
writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
/* /*
* We run one shot per tick here! (This is necessary to reconfigure, * We run one shot per tick here! (This is necessary to reconfigure,
* the timer will tilt if you don't!) * the timer will tilt if you don't!)
*/ */
writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); u300_timer_base + U300_TIMER_APP_SGPT1M);
/* Enable timer interrupts */ /* Enable timer interrupts */
writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); u300_timer_base + U300_TIMER_APP_GPT1IE);
/* Then enable the OS timer again */ /* Then enable the OS timer again */
writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); u300_timer_base + U300_TIMER_APP_EGPT1);
return 0; return 0;
} }
@ -320,8 +320,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
{ {
struct clock_event_device *evt = &clockevent_u300_1mhz; struct clock_event_device *evt = &clockevent_u300_1mhz;
/* ACK/Clear timer IRQ for the APP GPT1 Timer */ /* ACK/Clear timer IRQ for the APP GPT1 Timer */
writel(U300_TIMER_APP_GPT1IA_IRQ_ACK, writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA); u300_timer_base + U300_TIMER_APP_GPT1IA);
evt->event_handler(evt); evt->event_handler(evt);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
@ -342,65 +343,88 @@ static struct irqaction u300_timer_irq = {
static u32 notrace u300_read_sched_clock(void) static u32 notrace u300_read_sched_clock(void)
{ {
return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
} }
static unsigned long u300_read_current_timer(void)
{
return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
}
static struct delay_timer u300_delay_timer;
/* /*
* This sets up the system timers, clock source and clock event. * This sets up the system timers, clock source and clock event.
*/ */
void __init u300_timer_init(void) static void __init u300_timer_init_of(struct device_node *np)
{ {
struct resource irq_res;
int irq;
struct clk *clk; struct clk *clk;
unsigned long rate; unsigned long rate;
u300_timer_base = of_iomap(np, 0);
if (!u300_timer_base)
panic("could not ioremap system timer\n");
/* Get the IRQ for the GP1 timer */
irq = of_irq_to_resource(np, 2, &irq_res);
if (irq <= 0)
panic("no IRQ for system timer\n");
pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
/* Clock the interrupt controller */ /* Clock the interrupt controller */
clk = clk_get_sys("apptimer", NULL); clk = of_clk_get(np, 0);
BUG_ON(IS_ERR(clk)); BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk); clk_prepare_enable(clk);
rate = clk_get_rate(clk); rate = clk_get_rate(clk);
setup_sched_clock(u300_read_sched_clock, 32, rate); setup_sched_clock(u300_read_sched_clock, 32, rate);
u300_delay_timer.read_current_timer = &u300_read_current_timer;
u300_delay_timer.freq = rate;
register_current_timer_delay(&u300_delay_timer);
/* /*
* Disable the "OS" and "DD" timers - these are designed for Symbian! * Disable the "OS" and "DD" timers - these are designed for Symbian!
* Example usage in cnh1601578 cpu subsystem pd_timer_app.c * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
*/ */
writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE, writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC); u300_timer_base + U300_TIMER_APP_CRC);
writel(U300_TIMER_APP_ROST_TIMER_RESET, writel(U300_TIMER_APP_ROST_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST); u300_timer_base + U300_TIMER_APP_ROST);
writel(U300_TIMER_APP_DOST_TIMER_DISABLE, writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST); u300_timer_base + U300_TIMER_APP_DOST);
writel(U300_TIMER_APP_RDDT_TIMER_RESET, writel(U300_TIMER_APP_RDDT_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT); u300_timer_base + U300_TIMER_APP_RDDT);
writel(U300_TIMER_APP_DDDT_TIMER_DISABLE, writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT); u300_timer_base + U300_TIMER_APP_DDDT);
/* Reset the General Purpose timer 1. */ /* Reset the General Purpose timer 1. */
writel(U300_TIMER_APP_RGPT1_TIMER_RESET, writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); u300_timer_base + U300_TIMER_APP_RGPT1);
/* Set up the IRQ handler */ /* Set up the IRQ handler */
setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq); setup_irq(irq, &u300_timer_irq);
/* Reset the General Purpose timer 2 */ /* Reset the General Purpose timer 2 */
writel(U300_TIMER_APP_RGPT2_TIMER_RESET, writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2); u300_timer_base + U300_TIMER_APP_RGPT2);
/* Set this timer to run around forever */ /* Set this timer to run around forever */
writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC); writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
/* Set continuous mode so it wraps around */ /* Set continuous mode so it wraps around */
writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS, writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M); u300_timer_base + U300_TIMER_APP_SGPT2M);
/* Disable timer interrupts */ /* Disable timer interrupts */
writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE, writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE); u300_timer_base + U300_TIMER_APP_GPT2IE);
/* Then enable the GP2 timer to use as a free running us counter */ /* Then enable the GP2 timer to use as a free running us counter */
writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); u300_timer_base + U300_TIMER_APP_EGPT2);
/* Use general purpose timer 2 as clock source */ /* Use general purpose timer 2 as clock source */
if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC, if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
"GPT2", rate, 300, 32, clocksource_mmio_readl_up)) "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
pr_err("timer: failed to initialize U300 clock source\n"); pr_err("timer: failed to initialize U300 clock source\n");
@ -413,3 +437,6 @@ void __init u300_timer_init(void)
* used by hrtimers! * used by hrtimers!
*/ */
} }
CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
u300_timer_init_of);

1
arch/arm/mach-u300/timer.h
View File

@ -1 +0,0 @@
extern void u300_timer_init(void);

70
arch/arm/mach-u300/u300-gpio.h
View File

@ -1,70 +0,0 @@
/*
* Individual pin assignments for the B335/S335.
* Notice that the actual usage of these pins depends on the
* PAD MUX settings, that is why the same number can potentially
* appear several times. In the reference design each pin is only
* used for one purpose. These were determined by inspecting the
* S365 schematic.
*/
#define U300_GPIO_PIN_UART_RX 0
#define U300_GPIO_PIN_UART_TX 1
#define U300_GPIO_PIN_UART_CTS 2
#define U300_GPIO_PIN_UART_RTS 3
#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */
#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */
#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */
#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */
#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */
#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */
#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */
#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */
#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */
#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */
#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */
#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */
#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */
#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */
#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */
#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */
#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */
#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */
#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */
#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */
#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */
#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */
#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */
#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */
#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */
#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */
#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */
#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */
#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */
#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */
#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */
#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */
#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */
#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */
#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */
#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */
#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */
#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */
#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */
#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */
#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */
#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */
#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */
#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */
#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */

718
drivers/clk/clk-u300.c
View File

@ -11,7 +11,349 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <mach/syscon.h> #include <linux/of.h>
/* APP side SYSCON registers */
/* CLK Control Register 16bit (R/W) */
#define U300_SYSCON_CCR (0x0000)
#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
/* CLK Status Register 16bit (R/W) */
#define U300_SYSCON_CSR (0x0004)
#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
/* Reset lines for SLOW devices 16bit (R/W) */
#define U300_SYSCON_RSR (0x0014)
#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
/* Reset lines for FAST devices 16bit (R/W) */
#define U300_SYSCON_RFR (0x0018)
#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
/* Reset lines for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_RRR (0x001c)
#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
/* Clock enable for SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CESR (0x0020)
#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
/* Clock enable for FAST peripherals 16bit (R/W) */
#define U300_SYSCON_CEFR (0x0024)
#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
/* Clock enable for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CERR (0x0028)
#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
/* Single block clock enable 16bit (-/W) */
#define U300_SYSCON_SBCER (0x002c)
#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
/* Single block clock disable 16bit (-/W) */
#define U300_SYSCON_SBCDR (0x0030)
/* Same values as above for SBCER */
/* Clock force SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CFSR (0x003c)
#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
/* Clock force FAST peripherals 16bit (R/W) */
#define U300_SYSCON_CFFR (0x40)
/* Values not defined. Define if you want to use them. */
/* Clock force the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CFRR (0x44)
#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
/* PLL208 Frequency Control 16bit (R/W) */
#define U300_SYSCON_PFCR (0x48)
#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
/* Power Management Control 16bit (R/W) */
#define U300_SYSCON_PMCR (0x50)
#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
/* Reset Out 16bit (R/W) */
#define U300_SYSCON_RCR (0x6c)
#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
/* EMIF Slew Rate Control 16bit (R/W) */
#define U300_SYSCON_SRCLR (0x70)
#define U300_SYSCON_SRCLR_MASK (0x03FF)
#define U300_SYSCON_SRCLR_VALUE (0x03FF)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
/* EMIF Clock Control Register 16bit (R/W) */
#define U300_SYSCON_ECCR (0x0078)
#define U300_SYSCON_ECCR_MASK (0x000F)
#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
#define U300_SYSCON_MMF0R (0x90)
#define U300_SYSCON_MMF0R_MASK (0x00FF)
#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
#define U300_SYSCON_MMF1R (0x94)
#define U300_SYSCON_MMF1R_MASK (0x00FF)
#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
#define U300_SYSCON_MMCR (0x9C)
#define U300_SYSCON_MMCR_MASK (0x0003)
#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
#define U300_SYSCON_S0CCR (0x120)
#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
#define U300_SYSCON_S1CCR (0x124)
#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
#define U300_SYSCON_S2CCR (0x128)
#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
#define U300_SYSCON_PICR (0x0130)
#define U300_SYSCON_PICR_MASK (0x00FF)
#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
#define U300_SYSCON_PISR (0x0134)
#define U300_SYSCON_PISR_MASK (0x000F)
#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
#define U300_SYSCON_PICLR (0x0138)
#define U300_SYSCON_PICLR_MASK (0x000F)
#define U300_SYSCON_PICLR_RWMASK (0x0000)
#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
/* Clock activity observability register 0 */
#define U300_SYSCON_C0OAR (0x140)
#define U300_SYSCON_C0OAR_MASK (0xFFFF)
#define U300_SYSCON_C0OAR_VALUE (0xFFFF)
#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
#define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
#define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
/* Clock activity observability register 1 */
#define U300_SYSCON_C1OAR (0x144)
#define U300_SYSCON_C1OAR_MASK (0x3FFE)
#define U300_SYSCON_C1OAR_VALUE (0x3FFE)
#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
#define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
#define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
#define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
/* Clock activity observability register 2 */
#define U300_SYSCON_C2OAR (0x148)
#define U300_SYSCON_C2OAR_MASK (0x0FFF)
#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
/* /*
* The clocking hierarchy currently looks like this. * The clocking hierarchy currently looks like this.
@ -386,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
return clk; return clk;
} }
#define U300_CLK_TYPE_SLOW 0
#define U300_CLK_TYPE_FAST 1
#define U300_CLK_TYPE_REST 2
/**
* struct u300_clock - defines the bits and pieces for a certain clock
* @type: the clock type, slow fast or rest
* @id: the bit in the slow/fast/rest register for this clock
* @hw_ctrld: whether the clock is hardware controlled
* @clk_val: a value to poke in the one-write enable/disable registers
*/
struct u300_clock {
u8 type;
u8 id;
bool hw_ctrld;
u16 clk_val;
};
struct u300_clock const __initconst u300_clk_lookup[] = {
{
.type = U300_CLK_TYPE_REST,
.id = 3,
.hw_ctrld = true,
.clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
},
{
.type = U300_CLK_TYPE_REST,
.id = 4,
.hw_ctrld = true,
.clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
},
{
.type = U300_CLK_TYPE_REST,
.id = 5,
.hw_ctrld = false,
.clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
},
{
.type = U300_CLK_TYPE_REST,
.id = 6,
.hw_ctrld = false,
.clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
},
{
.type = U300_CLK_TYPE_REST,
.id = 8,
.hw_ctrld = true,
.clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
},
{
.type = U300_CLK_TYPE_REST,
.id = 9,
.hw_ctrld = false,
.clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
},
{
.type = U300_CLK_TYPE_REST,
.id = 10,
.hw_ctrld = true,
.clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
},
{
.type = U300_CLK_TYPE_REST,
.id = 12,
.hw_ctrld = false,
/* INTCON: cannot be enabled, just taken out of reset */
.clk_val = 0xFFFFU,
},
{
.type = U300_CLK_TYPE_FAST,
.id = 0,
.hw_ctrld = true,
.clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
},
{
.type = U300_CLK_TYPE_FAST,
.id = 1,
.hw_ctrld = false,
.clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
},
{
.type = U300_CLK_TYPE_FAST,
.id = 2,
.hw_ctrld = false,
.clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
},
{
.type = U300_CLK_TYPE_FAST,
.id = 5,
.hw_ctrld = false,
.clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
},
{
.type = U300_CLK_TYPE_FAST,
.id = 6,
.hw_ctrld = false,
.clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
},
{
.type = U300_CLK_TYPE_SLOW,
.id = 0,
.hw_ctrld = true,
.clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
},
{
.type = U300_CLK_TYPE_SLOW,
.id = 1,
.hw_ctrld = false,
.clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
},
{
.type = U300_CLK_TYPE_SLOW,
.id = 4,
.hw_ctrld = false,
.clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
},
{
.type = U300_CLK_TYPE_SLOW,
.id = 6,
.hw_ctrld = true,
/* No clock enable register bit */
.clk_val = 0xFFFFU,
},
{
.type = U300_CLK_TYPE_SLOW,
.id = 7,
.hw_ctrld = false,
.clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
},
{
.type = U300_CLK_TYPE_SLOW,
.id = 8,
.hw_ctrld = false,
.clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
},
};
static void __init of_u300_syscon_clk_init(struct device_node *np)
{
struct clk *clk = ERR_PTR(-EINVAL);
const char *clk_name = np->name;
const char *parent_name;
void __iomem *res_reg;
void __iomem *en_reg;
u32 clk_type;
u32 clk_id;
int i;
if (of_property_read_u32(np, "clock-type", &clk_type)) {
pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
__func__, clk_name);
return;
}
if (of_property_read_u32(np, "clock-id", &clk_id)) {
pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
__func__, clk_name);
return;
}
parent_name = of_clk_get_parent_name(np, 0);
switch (clk_type) {
case U300_CLK_TYPE_SLOW:
res_reg = syscon_vbase + U300_SYSCON_RSR;
en_reg = syscon_vbase + U300_SYSCON_CESR;
break;
case U300_CLK_TYPE_FAST:
res_reg = syscon_vbase + U300_SYSCON_RFR;
en_reg = syscon_vbase + U300_SYSCON_CEFR;
break;
case U300_CLK_TYPE_REST:
res_reg = syscon_vbase + U300_SYSCON_RRR;
en_reg = syscon_vbase + U300_SYSCON_CERR;
break;
default:
pr_err("unknown clock type %x specified\n", clk_type);
return;
}
for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
const struct u300_clock *u3clk = &u300_clk_lookup[i];
if (u3clk->type == clk_type && u3clk->id == clk_id)
clk = syscon_clk_register(NULL,
clk_name, parent_name,
0, u3clk->hw_ctrld,
res_reg, u3clk->id,
en_reg, u3clk->id,
u3clk->clk_val);
}
if (!IS_ERR(clk)) {
of_clk_add_provider(np, of_clk_src_simple_get, clk);
/*
* Some few system clocks - device tree does not
* represent clocks without a corresponding device node.
* for now we add these three clocks here.
*/
if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
clk_register_clkdev(clk, NULL, "pl172");
if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
clk_register_clkdev(clk, NULL, "semi");
if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
clk_register_clkdev(clk, NULL, "intcon");
}
}
/** /**
* struct clk_mclk - U300 MCLK clock (MMC/SD clock) * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
* @hw: corresponding clock hardware entry * @hw: corresponding clock hardware entry
@ -590,10 +1139,41 @@ mclk_clk_register(struct device *dev, const char *name,
return clk; return clk;
} }
static void __init of_u300_syscon_mclk_init(struct device_node *np)
{
struct clk *clk = ERR_PTR(-EINVAL);
const char *clk_name = np->name;
const char *parent_name;
parent_name = of_clk_get_parent_name(np, 0);
clk = mclk_clk_register(NULL, clk_name, parent_name, false);
if (!IS_ERR(clk))
of_clk_add_provider(np, of_clk_src_simple_get, clk);
}
static const __initconst struct of_device_id u300_clk_match[] = {
{
.compatible = "fixed-clock",
.data = of_fixed_clk_setup,
},
{
.compatible = "fixed-factor-clock",
.data = of_fixed_factor_clk_setup,
},
{
.compatible = "stericsson,u300-syscon-clk",
.data = of_u300_syscon_clk_init,
},
{
.compatible = "stericsson,u300-syscon-mclk",
.data = of_u300_syscon_mclk_init,
},
};
void __init u300_clk_init(void __iomem *base) void __init u300_clk_init(void __iomem *base)
{ {
u16 val; u16 val;
struct clk *clk;
syscon_vbase = base; syscon_vbase = base;
@ -610,137 +1190,5 @@ void __init u300_clk_init(void __iomem *base)
val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE; val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
writew(val, syscon_vbase + U300_SYSCON_PMCR); writew(val, syscon_vbase + U300_SYSCON_PMCR);
/* These are always available (RTC and PLL13) */ of_clk_init(u300_clk_match);
clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
CLK_IS_ROOT, 32768);
/* The watchdog sits directly on the 32 kHz clock */
clk_register_clkdev(clk, NULL, "coh901327_wdog");
clk = clk_register_fixed_rate(NULL, "pll13", NULL,
CLK_IS_ROOT, 13000000);
/* These derive from PLL208 */
clk = clk_register_fixed_rate(NULL, "pll208", NULL,
CLK_IS_ROOT, 208000000);
clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
0, 1, 1);
clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
0, 1, 2);
clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
0, 1, 4);
/* The 52 MHz is divided down to 26 MHz */
clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
0, 1, 2);
/* Directly on the AMBA interconnect */
clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
syscon_vbase + U300_SYSCON_RRR, 3,
syscon_vbase + U300_SYSCON_CERR, 3,
U300_SYSCON_SBCER_CPU_CLK_EN);
clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
syscon_vbase + U300_SYSCON_RRR, 4,
syscon_vbase + U300_SYSCON_CERR, 4,
U300_SYSCON_SBCER_DMAC_CLK_EN);
clk_register_clkdev(clk, NULL, "dma");
clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
syscon_vbase + U300_SYSCON_RRR, 6,
syscon_vbase + U300_SYSCON_CERR, 6,
U300_SYSCON_SBCER_NANDIF_CLK_EN);
clk_register_clkdev(clk, NULL, "fsmc-nand");
clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
syscon_vbase + U300_SYSCON_RRR, 8,
syscon_vbase + U300_SYSCON_CERR, 8,
U300_SYSCON_SBCER_XGAM_CLK_EN);
clk_register_clkdev(clk, NULL, "xgam");
clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
syscon_vbase + U300_SYSCON_RRR, 9,
syscon_vbase + U300_SYSCON_CERR, 9,
U300_SYSCON_SBCER_SEMI_CLK_EN);
clk_register_clkdev(clk, NULL, "semi");
/* AHB bridge clocks */
clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
syscon_vbase + U300_SYSCON_RRR, 10,
syscon_vbase + U300_SYSCON_CERR, 10,
U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
syscon_vbase + U300_SYSCON_RRR, 12,
syscon_vbase + U300_SYSCON_CERR, 12,
/* Cannot be enabled, just taken out of reset */
0xFFFFU);
clk_register_clkdev(clk, NULL, "intcon");
clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
syscon_vbase + U300_SYSCON_RRR, 5,
syscon_vbase + U300_SYSCON_CERR, 5,
U300_SYSCON_SBCER_EMIF_CLK_EN);
clk_register_clkdev(clk, NULL, "pl172");
/* FAST bridge clocks */
clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
syscon_vbase + U300_SYSCON_RFR, 0,
syscon_vbase + U300_SYSCON_CEFR, 0,
U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
syscon_vbase + U300_SYSCON_RFR, 1,
syscon_vbase + U300_SYSCON_CEFR, 1,
U300_SYSCON_SBCER_I2C0_CLK_EN);
clk_register_clkdev(clk, NULL, "stu300.0");
clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
syscon_vbase + U300_SYSCON_RFR, 2,
syscon_vbase + U300_SYSCON_CEFR, 2,
U300_SYSCON_SBCER_I2C1_CLK_EN);
clk_register_clkdev(clk, NULL, "stu300.1");
clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
syscon_vbase + U300_SYSCON_RFR, 5,
syscon_vbase + U300_SYSCON_CEFR, 5,
U300_SYSCON_SBCER_MMC_CLK_EN);
clk_register_clkdev(clk, "apb_pclk", "mmci");
clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
syscon_vbase + U300_SYSCON_RFR, 6,
syscon_vbase + U300_SYSCON_CEFR, 6,
U300_SYSCON_SBCER_SPI_CLK_EN);
/* The SPI has no external clock for the outward bus, uses the pclk */
clk_register_clkdev(clk, NULL, "pl022");
clk_register_clkdev(clk, "apb_pclk", "pl022");
/* SLOW bridge clocks */
clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
syscon_vbase + U300_SYSCON_RSR, 0,
syscon_vbase + U300_SYSCON_CESR, 0,
U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
syscon_vbase + U300_SYSCON_RSR, 1,
syscon_vbase + U300_SYSCON_CESR, 1,
U300_SYSCON_SBCER_UART_CLK_EN);
/* Same clock is used for APB and outward bus */
clk_register_clkdev(clk, NULL, "uart0");
clk_register_clkdev(clk, "apb_pclk", "uart0");
clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
syscon_vbase + U300_SYSCON_RSR, 4,
syscon_vbase + U300_SYSCON_CESR, 4,
U300_SYSCON_SBCER_GPIO_CLK_EN);
clk_register_clkdev(clk, NULL, "u300-gpio");
clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
syscon_vbase + U300_SYSCON_RSR, 5,
syscon_vbase + U300_SYSCON_CESR, 6,
U300_SYSCON_SBCER_KEYPAD_CLK_EN);
clk_register_clkdev(clk, NULL, "coh901461-keypad");
clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
syscon_vbase + U300_SYSCON_RSR, 6,
/* No clock enable register bit */
NULL, 0, 0xFFFFU);
clk_register_clkdev(clk, NULL, "rtc-coh901331");
clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
syscon_vbase + U300_SYSCON_RSR, 7,
syscon_vbase + U300_SYSCON_CESR, 7,
U300_SYSCON_SBCER_APP_TMR_CLK_EN);
clk_register_clkdev(clk, NULL, "apptimer");
clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
syscon_vbase + U300_SYSCON_RSR, 8,
syscon_vbase + U300_SYSCON_CESR, 8,
U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
clk_register_clkdev(clk, NULL, "timer");
/* Then this special MMC/SD clock */
clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
clk_register_clkdev(clk, NULL, "mmci");
} }

43
drivers/dma/coh901318.c
View File

@ -22,6 +22,7 @@
#include <linux/uaccess.h> #include <linux/uaccess.h>
#include <linux/debugfs.h> #include <linux/debugfs.h>
#include <linux/platform_data/dma-coh901318.h> #include <linux/platform_data/dma-coh901318.h>
#include <linux/of_dma.h>
#include "coh901318.h" #include "coh901318.h"
#include "dmaengine.h" #include "dmaengine.h"
@ -1788,6 +1789,35 @@ bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
} }
EXPORT_SYMBOL(coh901318_filter_id); EXPORT_SYMBOL(coh901318_filter_id);
struct coh901318_filter_args {
struct coh901318_base *base;
unsigned int ch_nr;
};
static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
{
struct coh901318_filter_args *args = data;
if (&args->base->dma_slave == chan->device &&
args->ch_nr == to_coh901318_chan(chan)->id)
return true;
return false;
}
static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
struct of_dma *ofdma)
{
struct coh901318_filter_args args = {
.base = ofdma->of_dma_data,
.ch_nr = dma_spec->args[0],
};
dma_cap_mask_t cap;
dma_cap_zero(cap);
dma_cap_set(DMA_SLAVE, cap);
return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
}
/* /*
* DMA channel allocation * DMA channel allocation
*/ */
@ -2735,12 +2765,19 @@ static int __init coh901318_probe(struct platform_device *pdev)
if (err) if (err)
goto err_register_memcpy; goto err_register_memcpy;
err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
base);
if (err)
goto err_register_of_dma;
platform_set_drvdata(pdev, base); platform_set_drvdata(pdev, base);
dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n", dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
(u32) base->virtbase); (u32) base->virtbase);
return err; return err;
err_register_of_dma:
dma_async_device_unregister(&base->dma_memcpy);
err_register_memcpy: err_register_memcpy:
dma_async_device_unregister(&base->dma_slave); dma_async_device_unregister(&base->dma_slave);
err_register_slave: err_register_slave:
@ -2752,17 +2789,23 @@ static int coh901318_remove(struct platform_device *pdev)
{ {
struct coh901318_base *base = platform_get_drvdata(pdev); struct coh901318_base *base = platform_get_drvdata(pdev);
of_dma_controller_free(pdev->dev.of_node);
dma_async_device_unregister(&base->dma_memcpy); dma_async_device_unregister(&base->dma_memcpy);
dma_async_device_unregister(&base->dma_slave); dma_async_device_unregister(&base->dma_slave);
coh901318_pool_destroy(&base->pool); coh901318_pool_destroy(&base->pool);
return 0; return 0;
} }
static const struct of_device_id coh901318_dt_match[] = {
{ .compatible = "stericsson,coh901318" },
{},
};
static struct platform_driver coh901318_driver = { static struct platform_driver coh901318_driver = {
.remove = coh901318_remove, .remove = coh901318_remove,
.driver = { .driver = {
.name = "coh901318", .name = "coh901318",
.of_match_table = coh901318_dt_match,
}, },
}; };

16
drivers/i2c/busses/i2c-stu300.c
View File

@ -17,6 +17,7 @@
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/of_i2c.h>
/* the name of this kernel module */ /* the name of this kernel module */
#define NAME "stu300" #define NAME "stu300"
@ -867,7 +868,6 @@ stu300_probe(struct platform_device *pdev)
struct resource *res; struct resource *res;
int bus_nr; int bus_nr;
int ret = 0; int ret = 0;
char clk_name[] = "I2C0";
dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL); dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
if (!dev) { if (!dev) {
@ -876,8 +876,7 @@ stu300_probe(struct platform_device *pdev)
} }
bus_nr = pdev->id; bus_nr = pdev->id;
clk_name[3] += (char)bus_nr; dev->clk = devm_clk_get(&pdev->dev, NULL);
dev->clk = devm_clk_get(&pdev->dev, clk_name);
if (IS_ERR(dev->clk)) { if (IS_ERR(dev->clk)) {
dev_err(&pdev->dev, "could not retrieve i2c bus clock\n"); dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
return PTR_ERR(dev->clk); return PTR_ERR(dev->clk);
@ -923,6 +922,7 @@ stu300_probe(struct platform_device *pdev)
adap->nr = bus_nr; adap->nr = bus_nr;
adap->algo = &stu300_algo; adap->algo = &stu300_algo;
adap->dev.parent = &pdev->dev; adap->dev.parent = &pdev->dev;
adap->dev.of_node = pdev->dev.of_node;
i2c_set_adapdata(adap, dev); i2c_set_adapdata(adap, dev);
/* i2c device drivers may be active on return from add_adapter() */ /* i2c device drivers may be active on return from add_adapter() */
@ -934,6 +934,10 @@ stu300_probe(struct platform_device *pdev)
} }
platform_set_drvdata(pdev, dev); platform_set_drvdata(pdev, dev);
dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n",
dev->virtbase, dev->irq);
of_i2c_register_devices(adap);
return 0; return 0;
} }
@ -978,11 +982,17 @@ stu300_remove(struct platform_device *pdev)
return 0; return 0;
} }
static const struct of_device_id stu300_dt_match[] = {
{ .compatible = "st,ddci2c" },
{},
};
static struct platform_driver stu300_i2c_driver = { static struct platform_driver stu300_i2c_driver = {
.driver = { .driver = {
.name = NAME, .name = NAME,
.owner = THIS_MODULE, .owner = THIS_MODULE,
.pm = STU300_I2C_PM, .pm = STU300_I2C_PM,
.of_match_table = stu300_dt_match,
}, },
.remove = __exit_p(stu300_remove), .remove = __exit_p(stu300_remove),

35
drivers/pinctrl/pinctrl-coh901.c
View File

@ -22,7 +22,6 @@
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_data/pinctrl-coh901.h>
#include "pinctrl-coh901.h" #include "pinctrl-coh901.h"
#define U300_GPIO_PORT_STRIDE (0x30) #define U300_GPIO_PORT_STRIDE (0x30)
@ -58,8 +57,9 @@
#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
/* 8 bits per port, no version has more than 7 ports */ /* 8 bits per port, no version has more than 7 ports */
#define U300_GPIO_NUM_PORTS 7
#define U300_GPIO_PINS_PER_PORT 8 #define U300_GPIO_PINS_PER_PORT 8
#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7) #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
struct u300_gpio { struct u300_gpio {
struct gpio_chip chip; struct gpio_chip chip;
@ -111,9 +111,6 @@ struct u300_gpio_confdata {
int outval; int outval;
}; };
/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
#define BS335_GPIO_NUM_PORTS 7
#define U300_FLOATING_INPUT { \ #define U300_FLOATING_INPUT { \
.bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
.output = false, \ .output = false, \
@ -136,7 +133,7 @@ struct u300_gpio_confdata {
/* Initial configuration */ /* Initial configuration */
static const struct __initconst u300_gpio_confdata static const struct __initconst u300_gpio_confdata
bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
/* Port 0, pins 0-7 */ /* Port 0, pins 0-7 */
{ {
U300_FLOATING_INPUT, U300_FLOATING_INPUT,
@ -630,13 +627,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
} }
} }
static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio, static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
struct u300_gpio_platform *plat)
{ {
int i, j; int i, j;
/* Write default config and values to all pins */ /* Write default config and values to all pins */
for (i = 0; i < plat->ports; i++) { for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
for (j = 0; j < 8; j++) { for (j = 0; j < 8; j++) {
const struct u300_gpio_confdata *conf; const struct u300_gpio_confdata *conf;
int offset = (i*8) + j; int offset = (i*8) + j;
@ -693,7 +689,6 @@ static struct coh901_pinpair coh901_pintable[] = {
static int __init u300_gpio_probe(struct platform_device *pdev) static int __init u300_gpio_probe(struct platform_device *pdev)
{ {
struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
struct u300_gpio *gpio; struct u300_gpio *gpio;
struct resource *memres; struct resource *memres;
int err = 0; int err = 0;
@ -707,9 +702,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
return -ENOMEM; return -ENOMEM;
gpio->chip = u300_gpio_chip; gpio->chip = u300_gpio_chip;
gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT; gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
gpio->chip.dev = &pdev->dev; gpio->chip.dev = &pdev->dev;
gpio->chip.base = plat->gpio_base; gpio->chip.base = 0;
gpio->dev = &pdev->dev; gpio->dev = &pdev->dev;
memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@ -750,11 +745,11 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
((val & 0x0000FE00) >> 9) * 8); ((val & 0x0000FE00) >> 9) * 8);
writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
gpio->base + U300_GPIO_CR); gpio->base + U300_GPIO_CR);
u300_gpio_init_coh901571(gpio, plat); u300_gpio_init_coh901571(gpio);
/* Add each port with its IRQ separately */ /* Add each port with its IRQ separately */
INIT_LIST_HEAD(&gpio->port_list); INIT_LIST_HEAD(&gpio->port_list);
for (portno = 0 ; portno < plat->ports; portno++) { for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
struct u300_gpio_port *port = struct u300_gpio_port *port =
kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL); kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
@ -768,8 +763,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
port->number = portno; port->number = portno;
port->gpio = gpio; port->gpio = gpio;
port->irq = platform_get_irq_byname(pdev, port->irq = platform_get_irq(pdev, portno);
port->name);
dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq, dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq,
port->name); port->name);
@ -806,6 +800,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
} }
dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
#ifdef CONFIG_OF_GPIO
gpio->chip.of_node = pdev->dev.of_node;
#endif
err = gpiochip_add(&gpio->chip); err = gpiochip_add(&gpio->chip);
if (err) { if (err) {
dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
@ -860,9 +857,15 @@ static int __exit u300_gpio_remove(struct platform_device *pdev)
return 0; return 0;
} }
static const struct of_device_id u300_gpio_match[] = {
{ .compatible = "stericsson,gpio-coh901" },
{},
};
static struct platform_driver u300_gpio_driver = { static struct platform_driver u300_gpio_driver = {
.driver = { .driver = {
.name = "u300-gpio", .name = "u300-gpio",
.of_match_table = u300_gpio_match,
}, },
.remove = __exit_p(u300_gpio_remove), .remove = __exit_p(u300_gpio_remove),
}; };

7
drivers/pinctrl/pinctrl-u300.c
View File

@ -1105,10 +1105,17 @@ static int u300_pmx_remove(struct platform_device *pdev)
return 0; return 0;
} }
static const struct of_device_id u300_pinctrl_match[] = {
{ .compatible = "stericsson,pinctrl-u300" },
{},
};
static struct platform_driver u300_pmx_driver = { static struct platform_driver u300_pmx_driver = {
.driver = { .driver = {
.name = DRIVER_NAME, .name = DRIVER_NAME,
.owner = THIS_MODULE, .owner = THIS_MODULE,
.of_match_table = u300_pinctrl_match,
}, },
.probe = u300_pmx_probe, .probe = u300_pmx_probe,
.remove = u300_pmx_remove, .remove = u300_pmx_remove,

6
drivers/rtc/rtc-coh901331.c
View File

@ -274,11 +274,17 @@ static void coh901331_shutdown(struct platform_device *pdev)
clk_disable_unprepare(rtap->clk); clk_disable_unprepare(rtap->clk);
} }
static const struct of_device_id coh901331_dt_match[] = {
{ .compatible = "stericsson,coh901331" },
{},
};
static struct platform_driver coh901331_driver = { static struct platform_driver coh901331_driver = {
.driver = { .driver = {
.name = "rtc-coh901331", .name = "rtc-coh901331",
.owner = THIS_MODULE, .owner = THIS_MODULE,
.pm = &coh901331_pm_ops, .pm = &coh901331_pm_ops,
.of_match_table = coh901331_dt_match,
}, },
.remove = __exit_p(coh901331_remove), .remove = __exit_p(coh901331_remove),
.shutdown = coh901331_shutdown, .shutdown = coh901331_shutdown,

1
drivers/spi/spi-pl022.c
View File

@ -2083,6 +2083,7 @@ pl022_platform_data_dt_get(struct device *dev)
} }
pd->bus_id = -1; pd->bus_id = -1;
pd->enable_dma = 1;
of_property_read_u32(np, "num-cs", &tmp); of_property_read_u32(np, "num-cs", &tmp);
pd->num_chipselect = tmp; pd->num_chipselect = tmp;
of_property_read_u32(np, "pl022,autosuspend-delay", of_property_read_u32(np, "pl022,autosuspend-delay",

12
drivers/watchdog/coh901327_wdt.c
View File

@ -354,9 +354,9 @@ static int __init coh901327_probe(struct platform_device *pdev)
clk_disable(clk); clk_disable(clk);
if (margin < 1 || margin > 327) ret = watchdog_init_timeout(&coh901327_wdt, margin, &pdev->dev);
margin = 60; if (ret < 0)
coh901327_wdt.timeout = margin; coh901327_wdt.timeout = 60;
ret = watchdog_register_device(&coh901327_wdt); ret = watchdog_register_device(&coh901327_wdt);
if (ret == 0) if (ret == 0)
@ -441,10 +441,16 @@ void coh901327_watchdog_reset(void)
/* Return and await doom */ /* Return and await doom */
} }
static const struct of_device_id coh901327_dt_match[] = {
{ .compatible = "stericsson,coh901327" },
{},
};
static struct platform_driver coh901327_driver = { static struct platform_driver coh901327_driver = {
.driver = { .driver = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
.name = "coh901327_wdog", .name = "coh901327_wdog",
.of_match_table = coh901327_dt_match,
}, },
.remove = __exit_p(coh901327_remove), .remove = __exit_p(coh901327_remove),
.suspend = coh901327_suspend, .suspend = coh901327_suspend,

22
include/linux/platform_data/pinctrl-coh901.h
View File

@ -1,22 +0,0 @@
/*
* Copyright (C) 2007-2012 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* GPIO block resgister definitions and inline macros for
* U300 GPIO COH 901 335 or COH 901 571/3
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef __MACH_U300_GPIO_U300_H
#define __MACH_U300_GPIO_U300_H
/**
* struct u300_gpio_platform - U300 GPIO platform data
* @ports: number of GPIO block ports
* @gpio_base: first GPIO number for this block (use a free range)
*/
struct u300_gpio_platform {
u8 ports;
int gpio_base;
};
#endif /* __MACH_U300_GPIO_U300_H */