hpsa: add more ioaccel2 error handling, including underrun statuses.
improve ioaccel2 error handling, including better handling of underrun statuses Reviewed-by: Scott Teel <scott.teel@pmcs.com> Reviewed-by: Kevin Barnett <kevin.barnett@pmcs.com> Signed-off-by: Joe Handzik <joseph.t.handzik@hp.com> Signed-off-by: Don Brace <don.brace@pmcs.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: James Bottomley <JBottomley@Odin.com>
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@ -1863,6 +1863,7 @@ static int handle_ioaccel_mode2_error(struct ctlr_info *h,
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{
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int data_len;
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int retry = 0;
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u32 ioaccel2_resid = 0;
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switch (c2->error_data.serv_response) {
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case IOACCEL2_SERV_RESPONSE_COMPLETE:
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@ -1921,11 +1922,31 @@ static int handle_ioaccel_mode2_error(struct ctlr_info *h,
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}
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break;
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case IOACCEL2_SERV_RESPONSE_FAILURE:
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/* don't expect to get here. */
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dev_warn(&h->pdev->dev,
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"unexpected delivery or target failure, status = 0x%02x\n",
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c2->error_data.status);
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retry = 1;
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switch (c2->error_data.status) {
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case IOACCEL2_STATUS_SR_IO_ERROR:
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case IOACCEL2_STATUS_SR_IO_ABORTED:
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case IOACCEL2_STATUS_SR_OVERRUN:
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retry = 1;
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break;
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case IOACCEL2_STATUS_SR_UNDERRUN:
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cmd->result = (DID_OK << 16); /* host byte */
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cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
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ioaccel2_resid = get_unaligned_le32(
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&c2->error_data.resid_cnt[0]);
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scsi_set_resid(cmd, ioaccel2_resid);
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break;
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case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
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case IOACCEL2_STATUS_SR_INVALID_DEVICE:
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case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
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/* We will get an event from ctlr to trigger rescan */
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retry = 1;
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break;
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default:
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retry = 1;
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dev_warn(&h->pdev->dev,
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"unexpected delivery or target failure, status = 0x%02x\n",
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c2->error_data.status);
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}
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break;
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case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
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break;
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@ -532,6 +532,12 @@ struct io_accel2_scsi_response {
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#define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28
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#define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40
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#define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E
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#define IOACCEL2_STATUS_SR_IO_ERROR 0x01
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#define IOACCEL2_STATUS_SR_IO_ABORTED 0x02
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#define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE 0x03
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#define IOACCEL2_STATUS_SR_INVALID_DEVICE 0x04
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#define IOACCEL2_STATUS_SR_UNDERRUN 0x51
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#define IOACCEL2_STATUS_SR_OVERRUN 0x75
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u8 data_present; /* low 2 bits */
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#define IOACCEL2_NO_DATAPRESENT 0x000
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#define IOACCEL2_RESPONSE_DATAPRESENT 0x001
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