clk: renesas: Updates for v6.8 (take two)
- Add interrupt controller and Ethernet clocks and resets on RZ/G3S, - Check reset monitor registers on RZ/G2L-alike SoCs. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZXxBPgAKCRCKwlD9ZEnx cHOdAPwLyw82xWzHj0lw0lxxMuBqDjewdg4BZMX8PpAxSD8krgD/W4oeBqKijlGh cCuuvH5Y4H5DoOR25uEsY807r7YZPAA= =TN05 -----END PGP SIGNATURE----- Merge tag 'renesas-clk-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S - Check reset monitor registers on Renesas RZ/G2L-alike SoCs * tag 'renesas-clk-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1 clk: renesas: rzg2l: Check reset monitor registers clk: renesas: r9a08g045: Add IA55 pclk and its reset
This commit is contained in:
commit
c46104f0c5
@ -181,13 +181,16 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
|
||||
DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS,
|
||||
dtable_1_32, 0, 0, 0, NULL),
|
||||
DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2),
|
||||
DEF_FIXED("ZT", R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1),
|
||||
DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2),
|
||||
DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),
|
||||
DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3),
|
||||
DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2),
|
||||
};
|
||||
|
||||
static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
|
||||
DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
|
||||
DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
|
||||
DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
|
||||
DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
|
||||
DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
|
||||
@ -202,6 +205,12 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
|
||||
DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
|
||||
DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
|
||||
DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
|
||||
DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0),
|
||||
DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0),
|
||||
DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8),
|
||||
DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),
|
||||
DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),
|
||||
DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
|
||||
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
|
||||
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
|
||||
};
|
||||
@ -209,9 +218,12 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
|
||||
static const struct rzg2l_reset r9a08g045_resets[] = {
|
||||
DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
|
||||
DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
|
||||
DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),
|
||||
DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
|
||||
DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
|
||||
DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
|
||||
DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
|
||||
DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
|
||||
DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
|
||||
DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
|
||||
DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
|
||||
@ -220,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
|
||||
|
||||
static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_BASE + R9A08G045_GIC600_GICCLK,
|
||||
MOD_CLK_BASE + R9A08G045_IA55_PCLK,
|
||||
MOD_CLK_BASE + R9A08G045_IA55_CLK,
|
||||
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
|
||||
};
|
||||
|
@ -1416,12 +1416,27 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
|
||||
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int reg = info->resets[id].off;
|
||||
u32 value = BIT(info->resets[id].bit) << 16;
|
||||
u32 mask = BIT(info->resets[id].bit);
|
||||
s8 monbit = info->resets[id].monbit;
|
||||
u32 value = mask << 16;
|
||||
|
||||
dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
|
||||
|
||||
writel(value, priv->base + CLK_RST_R(reg));
|
||||
return 0;
|
||||
|
||||
if (info->has_clk_mon_regs) {
|
||||
reg = CLK_MRST_R(reg);
|
||||
} else if (monbit >= 0) {
|
||||
reg = CPG_RST_MON;
|
||||
mask = BIT(monbit);
|
||||
} else {
|
||||
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
|
||||
udelay(35);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return readl_poll_timeout_atomic(priv->base + reg, value,
|
||||
value & mask, 10, 200);
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
|
||||
@ -1430,14 +1445,28 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
|
||||
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int reg = info->resets[id].off;
|
||||
u32 dis = BIT(info->resets[id].bit);
|
||||
u32 value = (dis << 16) | dis;
|
||||
u32 mask = BIT(info->resets[id].bit);
|
||||
s8 monbit = info->resets[id].monbit;
|
||||
u32 value = (mask << 16) | mask;
|
||||
|
||||
dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
|
||||
CLK_RST_R(reg));
|
||||
|
||||
writel(value, priv->base + CLK_RST_R(reg));
|
||||
return 0;
|
||||
|
||||
if (info->has_clk_mon_regs) {
|
||||
reg = CLK_MRST_R(reg);
|
||||
} else if (monbit >= 0) {
|
||||
reg = CPG_RST_MON;
|
||||
mask = BIT(monbit);
|
||||
} else {
|
||||
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
|
||||
udelay(35);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return readl_poll_timeout_atomic(priv->base + reg, value,
|
||||
!(value & mask), 10, 200);
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
|
||||
@ -1449,9 +1478,6 @@ static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
|
||||
udelay(35);
|
||||
|
||||
return rzg2l_cpg_deassert(rcdev, id);
|
||||
}
|
||||
|
||||
@ -1460,18 +1486,21 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
|
||||
{
|
||||
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int reg = info->resets[id].off;
|
||||
u32 bitmask = BIT(info->resets[id].bit);
|
||||
s8 monbit = info->resets[id].monbit;
|
||||
unsigned int reg;
|
||||
u32 bitmask;
|
||||
|
||||
if (info->has_clk_mon_regs) {
|
||||
return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
|
||||
reg = CLK_MRST_R(info->resets[id].off);
|
||||
bitmask = BIT(info->resets[id].bit);
|
||||
} else if (monbit >= 0) {
|
||||
u32 monbitmask = BIT(monbit);
|
||||
|
||||
return !!(readl(priv->base + CPG_RST_MON) & monbitmask);
|
||||
reg = CPG_RST_MON;
|
||||
bitmask = BIT(monbit);
|
||||
} else {
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
return -ENOTSUPP;
|
||||
|
||||
return !!(readl(priv->base + reg) & bitmask);
|
||||
}
|
||||
|
||||
static const struct reset_control_ops rzg2l_cpg_reset_ops = {
|
||||
|
Loading…
x
Reference in New Issue
Block a user