x86: KVM: svm: remove hardcoded instruction length from intercepts
Various intercepts hard-code the respective instruction lengths to optimize skip_emulated_instruction(): when next_rip is pre-set we skip kvm_emulate_instruction(vcpu, EMULTYPE_SKIP). The optimization is, however, incorrect: different (redundant) prefixes could be used to enlarge the instruction. We can't really avoid decoding. svm->next_rip is not used when CPU supports 'nrips' (X86_FEATURE_NRIPS) feature: next RIP is provided in VMCB. The feature is not really new (Opteron G3s had it already) and the change should have zero affect. Remove manual svm->next_rip setting with hard-coded instruction lengths. The only case where we now use svm->next_rip is EXIT_IOIO: the instruction length is provided to us by hardware. Hardcoded RIP advancement remains in vmrun_interception(), this is going to be taken care of separately. Reported-by: Jim Mattson <jmattson@google.com> Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -2900,13 +2900,11 @@ static int nop_on_interception(struct vcpu_svm *svm)
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static int halt_interception(struct vcpu_svm *svm)
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{
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svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
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return kvm_emulate_halt(&svm->vcpu);
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}
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static int vmmcall_interception(struct vcpu_svm *svm)
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{
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svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
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return kvm_emulate_hypercall(&svm->vcpu);
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}
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@ -3694,7 +3692,6 @@ static int vmload_interception(struct vcpu_svm *svm)
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nested_vmcb = map.hva;
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svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
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ret = kvm_skip_emulated_instruction(&svm->vcpu);
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nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
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@ -3721,7 +3718,6 @@ static int vmsave_interception(struct vcpu_svm *svm)
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nested_vmcb = map.hva;
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svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
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ret = kvm_skip_emulated_instruction(&svm->vcpu);
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nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
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@ -3772,7 +3768,6 @@ static int stgi_interception(struct vcpu_svm *svm)
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if (vgif_enabled(svm))
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clr_intercept(svm, INTERCEPT_STGI);
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svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
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ret = kvm_skip_emulated_instruction(&svm->vcpu);
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kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
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@ -3788,7 +3783,6 @@ static int clgi_interception(struct vcpu_svm *svm)
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if (nested_svm_check_permissions(svm))
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return 1;
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svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
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ret = kvm_skip_emulated_instruction(&svm->vcpu);
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disable_gif(svm);
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@ -3813,7 +3807,6 @@ static int invlpga_interception(struct vcpu_svm *svm)
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/* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
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kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
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svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
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return kvm_skip_emulated_instruction(&svm->vcpu);
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}
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@ -3836,7 +3829,6 @@ static int xsetbv_interception(struct vcpu_svm *svm)
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u32 index = kvm_rcx_read(&svm->vcpu);
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if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
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svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
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return kvm_skip_emulated_instruction(&svm->vcpu);
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}
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@ -3918,7 +3910,6 @@ fail:
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static int cpuid_interception(struct vcpu_svm *svm)
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{
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svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
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return kvm_emulate_cpuid(&svm->vcpu);
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}
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@ -4248,7 +4239,6 @@ static int rdmsr_interception(struct vcpu_svm *svm)
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kvm_rax_write(&svm->vcpu, msr_info.data & 0xffffffff);
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kvm_rdx_write(&svm->vcpu, msr_info.data >> 32);
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svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
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return kvm_skip_emulated_instruction(&svm->vcpu);
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}
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}
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@ -4454,7 +4444,6 @@ static int wrmsr_interception(struct vcpu_svm *svm)
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return 1;
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} else {
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trace_kvm_msr_write(ecx, data);
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svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
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return kvm_skip_emulated_instruction(&svm->vcpu);
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}
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}
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