interconnect: qcom: sc8180x: Drop IP0 interconnects
Similar to the sdx55 and sc7180, let's drop the MASTER_IPA_CORE and SLAVE_IPA_CORE interconnects for this platofm. There are no actual users of this intercoonect. The IP0 resource will be handled by clk-rpmh driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230109002935.244320-7-dmitry.baryshkov@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
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@ -1081,6 +1081,7 @@ EXPORT_SYMBOL_GPL(icc_provider_del);
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static const struct of_device_id __maybe_unused ignore_list[] = {
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static const struct of_device_id __maybe_unused ignore_list[] = {
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{ .compatible = "qcom,sc7180-ipa-virt" },
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{ .compatible = "qcom,sc7180-ipa-virt" },
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{ .compatible = "qcom,sc8180x-ipa-virt" },
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{ .compatible = "qcom,sdx55-ipa-virt" },
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{ .compatible = "qcom,sdx55-ipa-virt" },
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{ .compatible = "qcom,sm8150-ipa-virt" },
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{ .compatible = "qcom,sm8150-ipa-virt" },
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{ .compatible = "qcom,sm8250-ipa-virt" },
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{ .compatible = "qcom,sm8250-ipa-virt" },
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@ -469,15 +469,6 @@ static struct qcom_icc_node mas_qxm_ecc = {
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.links = { SC8180X_SLAVE_LLCC }
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.links = { SC8180X_SLAVE_LLCC }
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};
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};
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static struct qcom_icc_node mas_ipa_core_master = {
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.name = "mas_ipa_core_master",
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.id = SC8180X_MASTER_IPA_CORE,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8180X_SLAVE_IPA_CORE }
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};
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static struct qcom_icc_node mas_llcc_mc = {
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static struct qcom_icc_node mas_llcc_mc = {
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.name = "mas_llcc_mc",
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.name = "mas_llcc_mc",
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.id = SC8180X_MASTER_LLCC,
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.id = SC8180X_MASTER_LLCC,
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@ -1201,13 +1192,6 @@ static struct qcom_icc_node slv_srvc_gemnoc1 = {
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.buswidth = 4
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.buswidth = 4
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};
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};
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static struct qcom_icc_node slv_ipa_core_slave = {
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.name = "slv_ipa_core_slave",
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.id = SC8180X_SLAVE_IPA_CORE,
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.channels = 1,
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.buswidth = 8
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};
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static struct qcom_icc_node slv_ebi = {
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static struct qcom_icc_node slv_ebi = {
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.name = "slv_ebi",
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.name = "slv_ebi",
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.id = SC8180X_SLAVE_EBI_CH0,
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.id = SC8180X_SLAVE_EBI_CH0,
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@ -1524,11 +1508,6 @@ static struct qcom_icc_bcm bcm_co2 = {
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.nodes = { &mas_qnm_npu }
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.nodes = { &mas_qnm_npu }
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};
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};
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static struct qcom_icc_bcm bcm_ip0 = {
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.name = "IP0",
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.nodes = { &slv_ipa_core_slave }
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};
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static struct qcom_icc_bcm bcm_sn3 = {
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static struct qcom_icc_bcm bcm_sn3 = {
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.name = "SN3",
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.name = "SN3",
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.keepalive = true,
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.keepalive = true,
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@ -1604,10 +1583,6 @@ static struct qcom_icc_bcm * const gem_noc_bcms[] = {
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&bcm_sh3,
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&bcm_sh3,
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};
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};
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static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
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&bcm_ip0,
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};
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static struct qcom_icc_bcm * const mc_virt_bcms[] = {
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static struct qcom_icc_bcm * const mc_virt_bcms[] = {
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&bcm_mc0,
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&bcm_mc0,
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&bcm_acv,
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&bcm_acv,
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@ -1766,11 +1741,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
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[SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1,
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[SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1,
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};
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};
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static struct qcom_icc_node * const ipa_virt_nodes[] = {
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[MASTER_IPA_CORE] = &mas_ipa_core_master,
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[SLAVE_IPA_CORE] = &slv_ipa_core_slave,
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};
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static struct qcom_icc_node * const mc_virt_nodes[] = {
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static struct qcom_icc_node * const mc_virt_nodes[] = {
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[MASTER_LLCC] = &mas_llcc_mc,
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[MASTER_LLCC] = &mas_llcc_mc,
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[SLAVE_EBI_CH0] = &slv_ebi,
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[SLAVE_EBI_CH0] = &slv_ebi,
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@ -1857,13 +1827,6 @@ static const struct qcom_icc_desc sc8180x_gem_noc = {
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.num_bcms = ARRAY_SIZE(gem_noc_bcms),
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.num_bcms = ARRAY_SIZE(gem_noc_bcms),
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};
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};
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static const struct qcom_icc_desc sc8180x_ipa_virt = {
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.nodes = ipa_virt_nodes,
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.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
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.bcms = ipa_virt_bcms,
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.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
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};
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static const struct qcom_icc_desc sc8180x_mc_virt = {
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static const struct qcom_icc_desc sc8180x_mc_virt = {
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.nodes = mc_virt_nodes,
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.nodes = mc_virt_nodes,
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.num_nodes = ARRAY_SIZE(mc_virt_nodes),
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.num_nodes = ARRAY_SIZE(mc_virt_nodes),
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@ -1913,7 +1876,6 @@ static const struct of_device_id qnoc_of_match[] = {
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{ .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc },
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{ .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc },
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{ .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc },
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{ .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc },
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{ .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc },
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{ .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc },
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{ .compatible = "qcom,sc8180x-ipa-virt", .data = &sc8180x_ipa_virt },
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{ .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt },
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{ .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt },
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{ .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc },
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{ .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc },
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{ .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt },
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{ .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt },
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@ -51,7 +51,7 @@
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#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41
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#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41
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#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42
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#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42
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#define SC8180X_MASTER_ECC 43
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#define SC8180X_MASTER_ECC 43
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#define SC8180X_MASTER_IPA_CORE 44
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/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */
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#define SC8180X_MASTER_LLCC 45
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#define SC8180X_MASTER_LLCC 45
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#define SC8180X_MASTER_CNOC_MNOC_CFG 46
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#define SC8180X_MASTER_CNOC_MNOC_CFG 46
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#define SC8180X_MASTER_CAMNOC_HF0 47
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#define SC8180X_MASTER_CAMNOC_HF0 47
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@ -146,7 +146,7 @@
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#define SC8180X_SLAVE_LLCC 136
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#define SC8180X_SLAVE_LLCC 136
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#define SC8180X_SLAVE_SERVICE_GEM_NOC 137
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#define SC8180X_SLAVE_SERVICE_GEM_NOC 137
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#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138
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#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138
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#define SC8180X_SLAVE_IPA_CORE 139
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/* 139 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
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#define SC8180X_SLAVE_EBI_CH0 140
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#define SC8180X_SLAVE_EBI_CH0 140
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#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141
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#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141
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#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142
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#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142
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