EDAC, amd64: Add Hygon Dhyana support
Add support for Hygon Dhyana CPU to EDAC. Signed-off-by: Pu Wen <puwen@hygon.cn> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: mchehab@kernel.org Cc: tglx@linutronix.de Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: thomas.lendacky@amd.com Cc: linux-edac@vger.kernel.org Link: https://lkml.kernel.org/r/9d71061301177822bc55b3bfd44f91057458d886.1537533369.git.puwen@hygon.cn
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@ -211,7 +211,7 @@ static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
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scrubval = scrubrates[i].scrubval;
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if (pvt->fam == 0x17) {
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if (pvt->fam == 0x17 || pvt->fam == 0x18) {
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__f17h_set_scrubval(pvt, scrubval);
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} else if (pvt->fam == 0x15 && pvt->model == 0x60) {
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f15h_select_dct(pvt, 0);
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@ -264,6 +264,7 @@ static int get_scrub_rate(struct mem_ctl_info *mci)
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break;
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case 0x17:
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case 0x18:
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amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
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if (scrubval & BIT(0)) {
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amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
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@ -1044,6 +1045,7 @@ static void determine_memory_type(struct amd64_pvt *pvt)
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goto ddr3;
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case 0x17:
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case 0x18:
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if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
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pvt->dram_type = MEM_LRDDR4;
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else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
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@ -3202,8 +3204,13 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
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pvt->ops = &family_types[F17_M10H_CPUS].ops;
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break;
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}
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/* fall through */
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case 0x18:
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fam_type = &family_types[F17_CPUS];
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pvt->ops = &family_types[F17_CPUS].ops;
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if (pvt->fam == 0x18)
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family_types[F17_CPUS].ctl_name = "F18h";
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break;
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default:
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@ -3442,6 +3449,7 @@ static const struct x86_cpu_id amd64_cpuids[] = {
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{ X86_VENDOR_AMD, 0x15, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
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{ X86_VENDOR_AMD, 0x16, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
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{ X86_VENDOR_AMD, 0x17, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
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{ X86_VENDOR_HYGON, 0x18, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
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{ }
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};
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MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);
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@ -1059,7 +1059,8 @@ static int __init mce_amd_init(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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if (c->x86_vendor != X86_VENDOR_AMD)
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if (c->x86_vendor != X86_VENDOR_AMD &&
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c->x86_vendor != X86_VENDOR_HYGON)
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return -ENODEV;
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fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
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@ -1113,6 +1114,7 @@ static int __init mce_amd_init(void)
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break;
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case 0x17:
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case 0x18:
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xec_mask = 0x3f;
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if (!boot_cpu_has(X86_FEATURE_SMCA)) {
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printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n");
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