bcma: add bcma_pmu_spuravoid_pllupdate()
This function is needed by brcmsmac. This code is based on code from the Broadcom SDK. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Hauke Mehrtens
John W. Linville
parent
6270d1c39c
commit
c586e10992
@ -3,7 +3,8 @@
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* ChipCommon Power Management Unit driver
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*
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* Copyright 2009, Michael Buesch <m@bues.ch>
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* Copyright 2007, Broadcom Corporation
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* Copyright 2007, 2011, Broadcom Corporation
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* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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@ -284,3 +285,183 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
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return bcma_pmu_get_clockcontrol(cc);
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}
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static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
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u32 value)
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{
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
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}
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void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
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{
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u32 tmp = 0;
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u8 phypll_offset = 0;
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u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
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u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM4749:
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case BCMA_CHIP_ID_BCM53572:
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/* 5357[ab]0, 43236[ab]0, and 6362b0 */
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/* BCM5357 needs to touch PLL1_PLLCTL[02],
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so offset PLL0_PLLCTL[02] by 6 */
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phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
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bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
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bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
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/* RMW only the P1 divider */
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
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BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
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tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
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tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
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/* RMW only the int feedback divider */
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
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BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
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tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
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tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
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tmp = 1 << 10;
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break;
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case BCMA_CHIP_ID_BCM4331:
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case BCMA_CHIP_ID_BCM43431:
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if (spuravoid == 2) {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x11500014);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x0FC00a08);
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} else if (spuravoid == 1) {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x11500014);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x0F600a08);
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} else {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x11100014);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x03000a08);
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}
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tmp = 1 << 10;
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break;
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case BCMA_CHIP_ID_BCM43224:
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case BCMA_CHIP_ID_BCM43225:
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case BCMA_CHIP_ID_BCM43421:
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if (spuravoid == 1) {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x11500010);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
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0x000C0C06);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x0F600a08);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
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0x00000000);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
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0x2001E920);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
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0x88888815);
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} else {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x11100010);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
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0x000c0c06);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x03000a08);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
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0x00000000);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
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0x200005c0);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
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0x88888815);
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}
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tmp = 1 << 10;
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break;
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case BCMA_CHIP_ID_BCM4716:
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case BCMA_CHIP_ID_BCM4748:
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case BCMA_CHIP_ID_BCM47162:
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if (spuravoid == 1) {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x11500060);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
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0x080C0C06);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x0F600000);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
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0x00000000);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
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0x2001E924);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
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0x88888815);
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} else {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x11100060);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
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0x080c0c06);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x03000000);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
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0x00000000);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
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0x200005c0);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
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0x88888815);
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}
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tmp = 3 << 9;
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break;
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case BCMA_CHIP_ID_BCM43227:
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case BCMA_CHIP_ID_BCM43228:
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case BCMA_CHIP_ID_BCM43428:
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/* LCNXN */
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/* PLL Settings for spur avoidance on/off mode,
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no on2 support for 43228A0 */
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if (spuravoid == 1) {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x01100014);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
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0x040C0C06);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x03140A08);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
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0x00333333);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
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0x202C2820);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
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0x88888815);
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} else {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x11100014);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
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0x040c0c06);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x03000a08);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
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0x00000000);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
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0x200005c0);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
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0x88888815);
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}
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tmp = 1 << 10;
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break;
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default:
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pr_err("unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
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bus->chipinfo.id);
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break;
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}
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tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
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bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
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}
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EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
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@ -308,6 +308,19 @@
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#define BCMA_CC_PPL_PCHI_OFF 5
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#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
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#define BCMA_CC_PMU_PLL_CTL0 0
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#define BCMA_CC_PMU_PLL_CTL1 1
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#define BCMA_CC_PMU_PLL_CTL2 2
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#define BCMA_CC_PMU_PLL_CTL3 3
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#define BCMA_CC_PMU_PLL_CTL4 4
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#define BCMA_CC_PMU_PLL_CTL5 5
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#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
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#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
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#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
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#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
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/* BCM4331 ChipControl numbers. */
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#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
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#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
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@ -420,5 +433,6 @@ extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
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u32 offset, u32 mask, u32 set);
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extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
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u32 offset, u32 mask, u32 set);
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extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
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#endif /* LINUX_BCMA_DRIVER_CC_H_ */
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