drm/amdgpu: cleanup conditional execution
First of all calculating the number of dw to patch into a conditional execution is not something HW generation specific. This is just standard ring buffer calculations. While at it also reduce the BUG_ON() into WARN_ON(). Then instead of a random bit pattern use 0 as default value for the number of dw skipped, this way it's not mandatory any more to patch the conditional execution. And last make the address to check a parameter of the conditional execution instead of getting this from the ring. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
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86e14a7386
commit
c68cbbfd54
@ -131,7 +131,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
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struct amdgpu_ib *ib = &ibs[0];
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struct dma_fence *tmp = NULL;
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bool need_ctx_switch;
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unsigned int patch_offset = ~0;
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struct amdgpu_vm *vm;
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uint64_t fence_ctx;
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uint32_t status = 0, alloc_size;
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@ -139,10 +138,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
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bool secure, init_shadow;
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u64 shadow_va, csa_va, gds_va;
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int vmid = AMDGPU_JOB_GET_VMID(job);
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bool need_pipe_sync = false;
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unsigned int cond_exec;
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unsigned int i;
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int r = 0;
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bool need_pipe_sync = false;
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if (num_ibs == 0)
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return -EINVAL;
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@ -228,7 +228,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
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init_shadow, vmid);
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if (ring->funcs->init_cond_exec)
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patch_offset = amdgpu_ring_init_cond_exec(ring);
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cond_exec = amdgpu_ring_init_cond_exec(ring,
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ring->cond_exe_gpu_addr);
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amdgpu_device_flush_hdp(adev, ring);
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@ -278,16 +279,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
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fence_flags | AMDGPU_FENCE_FLAG_64BIT);
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}
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if (ring->funcs->emit_gfx_shadow) {
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if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec) {
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amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0);
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if (ring->funcs->init_cond_exec) {
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unsigned int ce_offset = ~0;
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ce_offset = amdgpu_ring_init_cond_exec(ring);
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if (ce_offset != ~0 && ring->funcs->patch_cond_exec)
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amdgpu_ring_patch_cond_exec(ring, ce_offset);
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}
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amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr);
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}
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r = amdgpu_fence_emit(ring, f, job, fence_flags);
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@ -302,8 +296,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
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if (ring->funcs->insert_end)
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ring->funcs->insert_end(ring);
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if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
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amdgpu_ring_patch_cond_exec(ring, patch_offset);
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amdgpu_ring_patch_cond_exec(ring, cond_exec);
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ring->current_ctx = fence_ctx;
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if (vm && ring->funcs->emit_switch_buffer)
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@ -209,8 +209,7 @@ struct amdgpu_ring_funcs {
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void (*insert_end)(struct amdgpu_ring *ring);
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/* pad the indirect buffer to the necessary number of dw */
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void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
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unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
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void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
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unsigned (*init_cond_exec)(struct amdgpu_ring *ring, uint64_t addr);
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/* note usage for clock and power gating */
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void (*begin_use)(struct amdgpu_ring *ring);
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void (*end_use)(struct amdgpu_ring *ring);
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@ -327,8 +326,7 @@ struct amdgpu_ring {
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#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
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#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
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#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
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#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
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#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
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#define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a))
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#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
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#define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o)))
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#define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o)))
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@ -411,6 +409,30 @@ static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
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ring->count_dw -= count_dw;
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}
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/**
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* amdgpu_ring_patch_cond_exec - patch dw count of conditional execute
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* @ring: amdgpu_ring structure
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* @offset: offset returned by amdgpu_ring_init_cond_exec
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*
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* Calculate the dw count and patch it into a cond_exec command.
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*/
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static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring,
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unsigned int offset)
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{
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unsigned cur;
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if (!ring->funcs->init_cond_exec)
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return;
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WARN_ON(offset > ring->buf_mask);
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WARN_ON(ring->ring[offset] != 0);
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cur = (ring->wptr - 1) & ring->buf_mask;
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if (cur < offset)
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cur += ring->ring_size >> 2;
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ring->ring[offset] = cur - offset;
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}
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#define amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset) \
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(ring->is_mes_queue && ring->mes_ctx ? \
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(ring->mes_ctx->meta_data_gpu_addr + offset) : 0)
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@ -658,7 +658,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
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bool vm_flush_needed = job->vm_needs_flush;
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struct dma_fence *fence = NULL;
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bool pasid_mapping_needed = false;
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unsigned patch_offset = 0;
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unsigned int patch;
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int r;
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if (amdgpu_vmid_had_gpu_reset(adev, id)) {
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@ -685,7 +685,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
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amdgpu_ring_ib_begin(ring);
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if (ring->funcs->init_cond_exec)
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patch_offset = amdgpu_ring_init_cond_exec(ring);
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patch = amdgpu_ring_init_cond_exec(ring,
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ring->cond_exe_gpu_addr);
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if (need_pipe_sync)
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amdgpu_ring_emit_pipeline_sync(ring);
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@ -733,8 +734,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
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}
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dma_fence_put(fence);
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if (ring->funcs->patch_cond_exec)
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amdgpu_ring_patch_cond_exec(ring, patch_offset);
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amdgpu_ring_patch_cond_exec(ring, patch);
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/* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
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if (ring->funcs->emit_switch_buffer) {
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@ -546,34 +546,21 @@ static void vpe_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid,
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amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
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}
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static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring)
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static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring,
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uint64_t addr)
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{
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unsigned int ret;
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amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COND_EXE, 0));
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amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
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amdgpu_ring_write(ring, lower_32_bits(addr));
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amdgpu_ring_write(ring, upper_32_bits(addr));
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amdgpu_ring_write(ring, 1);
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ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
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amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
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ret = ring->wptr & ring->buf_mask;
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amdgpu_ring_write(ring, 0);
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return ret;
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}
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static void vpe_ring_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset)
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{
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unsigned int cur;
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WARN_ON_ONCE(offset > ring->buf_mask);
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WARN_ON_ONCE(ring->ring[offset] != 0x55aa55aa);
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cur = (ring->wptr - 1) & ring->buf_mask;
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if (cur > offset)
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ring->ring[offset] = cur - offset;
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else
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ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
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}
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static int vpe_ring_preempt_ib(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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@ -864,7 +851,6 @@ static const struct amdgpu_ring_funcs vpe_ring_funcs = {
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.test_ring = vpe_ring_test_ring,
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.test_ib = vpe_ring_test_ib,
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.init_cond_exec = vpe_ring_init_cond_exec,
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.patch_cond_exec = vpe_ring_patch_cond_exec,
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.preempt_ib = vpe_ring_preempt_ib,
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.begin_use = vpe_ring_begin_use,
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.end_use = vpe_ring_end_use,
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@ -8542,34 +8542,23 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, 0);
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}
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static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
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static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
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uint64_t addr)
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{
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unsigned int ret;
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amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
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amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
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amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
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amdgpu_ring_write(ring, lower_32_bits(addr));
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amdgpu_ring_write(ring, upper_32_bits(addr));
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/* discard following DWs if *cond_exec_gpu_addr==0 */
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amdgpu_ring_write(ring, 0);
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ret = ring->wptr & ring->buf_mask;
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amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
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/* patch dummy value later */
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amdgpu_ring_write(ring, 0);
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return ret;
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}
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static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset)
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{
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unsigned int cur;
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BUG_ON(offset > ring->buf_mask);
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BUG_ON(ring->ring[offset] != 0x55aa55aa);
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cur = (ring->wptr - 1) & ring->buf_mask;
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if (likely(cur > offset))
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ring->ring[offset] = cur - offset;
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else
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ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
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}
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static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
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{
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int i, r = 0;
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@ -9224,7 +9213,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
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.emit_switch_buffer = gfx_v10_0_ring_emit_sb,
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.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
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.init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
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.patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
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.preempt_ib = gfx_v10_0_ring_preempt_ib,
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.emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
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.emit_wreg = gfx_v10_0_ring_emit_wreg,
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@ -5533,33 +5533,23 @@ static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring,
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PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0);
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}
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static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
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static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
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uint64_t addr)
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{
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unsigned ret;
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amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
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amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
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amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
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amdgpu_ring_write(ring, lower_32_bits(addr));
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amdgpu_ring_write(ring, upper_32_bits(addr));
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/* discard following DWs if *cond_exec_gpu_addr==0 */
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amdgpu_ring_write(ring, 0);
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ret = ring->wptr & ring->buf_mask;
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amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
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/* patch dummy value later */
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amdgpu_ring_write(ring, 0);
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return ret;
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}
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static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
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{
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unsigned cur;
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BUG_ON(offset > ring->buf_mask);
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BUG_ON(ring->ring[offset] != 0x55aa55aa);
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cur = (ring->wptr - 1) & ring->buf_mask;
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if (likely(cur > offset))
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ring->ring[offset] = cur - offset;
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else
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ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
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}
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static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring)
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{
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int i, r = 0;
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@ -6153,7 +6143,6 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
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.emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,
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.emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow,
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.init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec,
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.patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec,
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.preempt_ib = gfx_v11_0_ring_preempt_ib,
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.emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl,
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.emit_wreg = gfx_v11_0_ring_emit_wreg,
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@ -6326,33 +6326,22 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
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amdgpu_ring_write(ring, 0);
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}
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static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
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static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
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uint64_t addr)
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{
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unsigned ret;
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amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
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amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
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amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
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amdgpu_ring_write(ring, lower_32_bits(addr));
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amdgpu_ring_write(ring, upper_32_bits(addr));
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/* discard following DWs if *cond_exec_gpu_addr==0 */
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amdgpu_ring_write(ring, 0);
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ret = ring->wptr & ring->buf_mask;
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amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
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/* patch dummy value later */
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amdgpu_ring_write(ring, 0);
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return ret;
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}
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static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
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{
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unsigned cur;
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BUG_ON(offset > ring->buf_mask);
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BUG_ON(ring->ring[offset] != 0x55aa55aa);
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cur = (ring->wptr & ring->buf_mask) - 1;
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if (likely(cur > offset))
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ring->ring[offset] = cur - offset;
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else
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ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
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}
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static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t reg_val_offs)
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{
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@ -6932,7 +6921,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
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.emit_switch_buffer = gfx_v8_ring_emit_sb,
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.emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
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.init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
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.patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
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.emit_wreg = gfx_v8_0_ring_emit_wreg,
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.soft_recovery = gfx_v8_0_ring_soft_recovery,
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.emit_mem_sync = gfx_v8_0_emit_mem_sync,
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@ -5610,31 +5610,21 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
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amdgpu_ring_write(ring, 0);
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}
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static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
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static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
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uint64_t addr)
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{
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unsigned ret;
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amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
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amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
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||||
amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
|
||||
amdgpu_ring_write(ring, lower_32_bits(addr));
|
||||
amdgpu_ring_write(ring, upper_32_bits(addr));
|
||||
/* discard following DWs if *cond_exec_gpu_addr==0 */
|
||||
amdgpu_ring_write(ring, 0);
|
||||
ret = ring->wptr & ring->buf_mask;
|
||||
amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
|
||||
/* patch dummy value later */
|
||||
amdgpu_ring_write(ring, 0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
|
||||
{
|
||||
unsigned cur;
|
||||
BUG_ON(offset > ring->buf_mask);
|
||||
BUG_ON(ring->ring[offset] != 0x55aa55aa);
|
||||
|
||||
cur = (ring->wptr - 1) & ring->buf_mask;
|
||||
if (likely(cur > offset))
|
||||
ring->ring[offset] = cur - offset;
|
||||
else
|
||||
ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
|
||||
}
|
||||
|
||||
static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
|
||||
uint32_t reg_val_offs)
|
||||
{
|
||||
@ -6908,7 +6898,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
|
||||
.emit_switch_buffer = gfx_v9_ring_emit_sb,
|
||||
.emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
|
||||
.init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
|
||||
.patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
|
||||
.preempt_ib = gfx_v9_0_ring_preempt_ib,
|
||||
.emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl,
|
||||
.emit_wreg = gfx_v9_0_ring_emit_wreg,
|
||||
@ -6963,7 +6952,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = {
|
||||
.emit_switch_buffer = gfx_v9_ring_emit_sb,
|
||||
.emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
|
||||
.init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
|
||||
.patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
|
||||
.emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl,
|
||||
.emit_wreg = gfx_v9_0_ring_emit_wreg,
|
||||
.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
|
||||
|
@ -249,35 +249,23 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
|
||||
static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring,
|
||||
uint64_t addr)
|
||||
{
|
||||
unsigned ret;
|
||||
|
||||
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
|
||||
amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
|
||||
amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
|
||||
amdgpu_ring_write(ring, lower_32_bits(addr));
|
||||
amdgpu_ring_write(ring, upper_32_bits(addr));
|
||||
amdgpu_ring_write(ring, 1);
|
||||
ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
|
||||
amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
|
||||
/* this is the offset we need patch later */
|
||||
ret = ring->wptr & ring->buf_mask;
|
||||
/* insert dummy here and patch it later */
|
||||
amdgpu_ring_write(ring, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
|
||||
unsigned offset)
|
||||
{
|
||||
unsigned cur;
|
||||
|
||||
BUG_ON(offset > ring->buf_mask);
|
||||
BUG_ON(ring->ring[offset] != 0x55aa55aa);
|
||||
|
||||
cur = (ring->wptr - 1) & ring->buf_mask;
|
||||
if (cur > offset)
|
||||
ring->ring[offset] = cur - offset;
|
||||
else
|
||||
ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
|
||||
}
|
||||
|
||||
/**
|
||||
* sdma_v5_0_ring_get_rptr - get the current read pointer
|
||||
*
|
||||
@ -1780,7 +1768,6 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
|
||||
.emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
|
||||
.emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
|
||||
.init_cond_exec = sdma_v5_0_ring_init_cond_exec,
|
||||
.patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
|
||||
.preempt_ib = sdma_v5_0_ring_preempt_ib,
|
||||
};
|
||||
|
||||
|
@ -89,35 +89,23 @@ static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3
|
||||
return base + internal_offset;
|
||||
}
|
||||
|
||||
static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
|
||||
static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring,
|
||||
uint64_t addr)
|
||||
{
|
||||
unsigned ret;
|
||||
|
||||
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
|
||||
amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
|
||||
amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
|
||||
amdgpu_ring_write(ring, lower_32_bits(addr));
|
||||
amdgpu_ring_write(ring, upper_32_bits(addr));
|
||||
amdgpu_ring_write(ring, 1);
|
||||
ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
|
||||
amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
|
||||
/* this is the offset we need patch later */
|
||||
ret = ring->wptr & ring->buf_mask;
|
||||
/* insert dummy here and patch it later */
|
||||
amdgpu_ring_write(ring, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
|
||||
unsigned offset)
|
||||
{
|
||||
unsigned cur;
|
||||
|
||||
BUG_ON(offset > ring->buf_mask);
|
||||
BUG_ON(ring->ring[offset] != 0x55aa55aa);
|
||||
|
||||
cur = (ring->wptr - 1) & ring->buf_mask;
|
||||
if (cur > offset)
|
||||
ring->ring[offset] = cur - offset;
|
||||
else
|
||||
ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
|
||||
}
|
||||
|
||||
/**
|
||||
* sdma_v5_2_ring_get_rptr - get the current read pointer
|
||||
*
|
||||
@ -1722,7 +1710,6 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
|
||||
.emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
|
||||
.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
|
||||
.init_cond_exec = sdma_v5_2_ring_init_cond_exec,
|
||||
.patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
|
||||
.preempt_ib = sdma_v5_2_ring_preempt_ib,
|
||||
};
|
||||
|
||||
|
@ -80,35 +80,23 @@ static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3
|
||||
return base + internal_offset;
|
||||
}
|
||||
|
||||
static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring)
|
||||
static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring,
|
||||
uint64_t addr)
|
||||
{
|
||||
unsigned ret;
|
||||
|
||||
amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
|
||||
amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
|
||||
amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
|
||||
amdgpu_ring_write(ring, lower_32_bits(addr));
|
||||
amdgpu_ring_write(ring, upper_32_bits(addr));
|
||||
amdgpu_ring_write(ring, 1);
|
||||
ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
|
||||
amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
|
||||
/* this is the offset we need patch later */
|
||||
ret = ring->wptr & ring->buf_mask;
|
||||
/* insert dummy here and patch it later */
|
||||
amdgpu_ring_write(ring, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
|
||||
unsigned offset)
|
||||
{
|
||||
unsigned cur;
|
||||
|
||||
BUG_ON(offset > ring->buf_mask);
|
||||
BUG_ON(ring->ring[offset] != 0x55aa55aa);
|
||||
|
||||
cur = (ring->wptr - 1) & ring->buf_mask;
|
||||
if (cur > offset)
|
||||
ring->ring[offset] = cur - offset;
|
||||
else
|
||||
ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
|
||||
}
|
||||
|
||||
/**
|
||||
* sdma_v6_0_ring_get_rptr - get the current read pointer
|
||||
*
|
||||
@ -1542,7 +1530,6 @@ static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
|
||||
.emit_reg_wait = sdma_v6_0_ring_emit_reg_wait,
|
||||
.emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
|
||||
.init_cond_exec = sdma_v6_0_ring_init_cond_exec,
|
||||
.patch_cond_exec = sdma_v6_0_ring_patch_cond_exec,
|
||||
.preempt_ib = sdma_v6_0_ring_preempt_ib,
|
||||
};
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user