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s390/bpf: Implement unconditional jump with 32-bit offset

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Implement the cpuv4 unconditional jump with 32-bit offset, which is
encoded as BPF_JMP32 | BPF_JA and stores the offset in the imm field.
Reuse the existing BPF_JMP | BPF_JA logic.

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Link: https://lore.kernel.org/r/20230919101336.2223655-8-iii@linux.ibm.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
This commit is contained in:
Ilya Leoshkevich 2023-09-19 12:09:09 +02:00 committed by Alexei Starovoitov
parent 90f426d35e
commit c690191e23
1 changed files with 9 additions and 3 deletions
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12
arch/s390/net/bpf_jit_comp.c
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@ -779,6 +779,7 @@ static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp,
int i, bool extra_pass, u32 stack_depth) int i, bool extra_pass, u32 stack_depth)
{ {
struct bpf_insn *insn = &fp->insnsi[i]; struct bpf_insn *insn = &fp->insnsi[i];
s16 branch_oc_off = insn->off;
u32 dst_reg = insn->dst_reg; u32 dst_reg = insn->dst_reg;
u32 src_reg = insn->src_reg; u32 src_reg = insn->src_reg;
int last, insn_count = 1; int last, insn_count = 1;
@ -1625,6 +1626,9 @@ static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp,
* instruction itself (loop) and for BPF with offset 0 we * instruction itself (loop) and for BPF with offset 0 we
* branch to the instruction behind the branch. * branch to the instruction behind the branch.
*/ */
case BPF_JMP32 | BPF_JA: /* if (true) */
branch_oc_off = imm;
fallthrough;
case BPF_JMP | BPF_JA: /* if (true) */ case BPF_JMP | BPF_JA: /* if (true) */
mask = 0xf000; /* j */ mask = 0xf000; /* j */
goto branch_oc; goto branch_oc;
@ -1793,14 +1797,16 @@ branch_xu:
break; break;
branch_oc: branch_oc:
if (!is_first_pass(jit) && if (!is_first_pass(jit) &&
can_use_rel(jit, addrs[i + off + 1])) { can_use_rel(jit, addrs[i + branch_oc_off + 1])) {
/* brc mask,off */ /* brc mask,off */
EMIT4_PCREL_RIC(0xa7040000, EMIT4_PCREL_RIC(0xa7040000,
mask >> 12, addrs[i + off + 1]); mask >> 12,
addrs[i + branch_oc_off + 1]);
} else { } else {
/* brcl mask,off */ /* brcl mask,off */
EMIT6_PCREL_RILC(0xc0040000, EMIT6_PCREL_RILC(0xc0040000,
mask >> 12, addrs[i + off + 1]); mask >> 12,
addrs[i + branch_oc_off + 1]);
} }
break; break;
} }