Staging: et131x: remove unused PCI identifiers
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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committed by
Greg Kroah-Hartman
parent
576b38e0cd
commit
c6c9f8cb38
@ -63,9 +63,6 @@
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#define TRUEPHY_SUCCESS 0
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#define TRUEPHY_SUCCESS 0
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#define TRUEPHY_FAILURE 1
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#define TRUEPHY_FAILURE 1
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typedef void *TRUEPHY_HANDLE;
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typedef void *TRUEPHY_PLATFORM_HANDLE;
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typedef void *TRUEPHY_OSAL_HANDLE;
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/* MI Register Addresses */
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/* MI Register Addresses */
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#define MI_CONTROL_REG 0
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#define MI_CONTROL_REG 0
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@ -742,28 +739,6 @@ typedef union _MI_LCR2_t {
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/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
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/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
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/* TruePHY headers */
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typedef struct _TRUEPHY_ACCESS_MI_REGS_ {
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TRUEPHY_HANDLE hTruePhy;
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int32_t nPhyId;
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u8 bReadWrite;
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u8 *pbyRegs;
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u8 *pwData;
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int32_t nRegCount;
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} TRUEPHY_ACCESS_MI_REGS, *PTRUEPHY_ACCESS_MI_REGS;
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/* TruePHY headers */
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typedef struct _TAG_TPAL_ACCESS_MI_REGS_ {
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u32 nPhyId;
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u8 bReadWrite;
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u32 nRegCount;
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u16 Data[4096];
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u8 Regs[4096];
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} TPAL_ACCESS_MI_REGS, *PTPAL_ACCESS_MI_REGS;
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typedef TRUEPHY_HANDLE TPAL_HANDLE;
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/* Forward declaration of the private adapter structure */
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/* Forward declaration of the private adapter structure */
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struct et131x_adapter;
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struct et131x_adapter;
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@ -61,54 +61,24 @@
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#include "et1310_address_map.h"
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#include "et1310_address_map.h"
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#define MAX_WOL_PACKET_SIZE 0x80
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#define MAX_WOL_MASK_SIZE (MAX_WOL_PACKET_SIZE / 8)
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#define NUM_WOL_PATTERNS 0x5
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#define CRC16_POLY 0x1021
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typedef struct _MP_POWER_MGMT {
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typedef struct _MP_POWER_MGMT {
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/* variable putting the phy into coma mode when boot up with no cable
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/* variable putting the phy into coma mode when boot up with no cable
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* plugged in after 5 seconds
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* plugged in after 5 seconds
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*/
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*/
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u8 TransPhyComaModeOnBoot;
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u8 TransPhyComaModeOnBoot;
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/* Array holding the five CRC values that the device is currently
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* using for WOL. This will be queried when a pattern is to be
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* removed.
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*/
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u32 localWolAndCrc0;
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u16 WOLPatternList[NUM_WOL_PATTERNS];
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u8 WOLMaskList[NUM_WOL_PATTERNS][MAX_WOL_MASK_SIZE];
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u32 WOLMaskSize[NUM_WOL_PATTERNS];
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/* IP address */
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union {
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u32 u32;
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u8 u8[4];
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} IPAddress;
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/* Current Power state of the adapter. */
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bool WOLState;
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bool WOLEnabled;
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bool Failed10Half;
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bool bFailedStateTransition;
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/* Next two used to save power information at power down. This
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/* Next two used to save power information at power down. This
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* information will be used during power up to set up parts of Power
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* information will be used during power up to set up parts of Power
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* Management in JAGCore
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* Management in JAGCore
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*/
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*/
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u32 tx_en;
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u32 rx_en;
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u16 PowerDownSpeed;
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u16 PowerDownSpeed;
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u8 PowerDownDuplex;
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u8 PowerDownDuplex;
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} MP_POWER_MGMT, *PMP_POWER_MGMT;
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} MP_POWER_MGMT, *PMP_POWER_MGMT;
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/* Forward declaration of the private adapter structure
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/* Forward declaration of the private adapter structure
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* ( IS THERE A WAY TO DO THIS WITH A TYPEDEF??? )
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*/
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*/
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struct et131x_adapter;
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struct et131x_adapter;
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u16 CalculateCCITCRC16(u8 *Pattern, u8 *Mask, u32 MaskSize);
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void EnablePhyComa(struct et131x_adapter *adapter);
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void EnablePhyComa(struct et131x_adapter *adapter);
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void DisablePhyComa(struct et131x_adapter *adapter);
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void DisablePhyComa(struct et131x_adapter *adapter);
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@ -61,7 +61,6 @@
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/* Packet and header sizes */
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/* Packet and header sizes */
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#define NIC_MIN_PACKET_SIZE 60
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#define NIC_MIN_PACKET_SIZE 60
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#define NIC_HEADER_SIZE ETH_HLEN /* 14 */
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/* Multicast list size */
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/* Multicast list size */
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#define NIC_MAX_MCAST_LIST 128
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#define NIC_MAX_MCAST_LIST 128
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@ -102,20 +101,13 @@
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#define fMP_ADAPTER_NOT_READY_MASK 0x3ff00000
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#define fMP_ADAPTER_NOT_READY_MASK 0x3ff00000
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/* Some offsets in PCI config space that are actually used. */
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/* Some offsets in PCI config space that are actually used. */
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#define ET1310_PCI_PM_CAPABILITY 0x40
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#define ET1310_PCI_PM_CSR 0x44
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#define ET1310_PCI_MAX_PYLD 0x4C
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#define ET1310_PCI_MAX_PYLD 0x4C
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#define ET1310_PCI_DEV_CTRL 0x50
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#define ET1310_PCI_DEV_STAT 0x52
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#define ET1310_NMI_DISABLE 0x61
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#define ET1310_NMI_DISABLE 0x61
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#define ET1310_PCI_MAC_ADDRESS 0xA4
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#define ET1310_PCI_MAC_ADDRESS 0xA4
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#define ET1310_PCI_EEPROM_STATUS 0xB2
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#define ET1310_PCI_EEPROM_STATUS 0xB2
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#define ET1310_PCI_PHY_INDEX_REG 0xB4
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#define ET1310_PCI_ACK_NACK 0xC0
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#define ET1310_PCI_ACK_NACK 0xC0
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#define ET1310_PCI_REPLAY 0xC2
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#define ET1310_PCI_REPLAY 0xC2
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#define ET1310_PCI_L0L1LATENCY 0xCF
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#define ET1310_PCI_L0L1LATENCY 0xCF
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#define ET1310_PCI_SEL_PHY_CTRL 0xE4
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#define ET1310_PCI_ADVANCED_ERR 0x100
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/* PCI Vendor/Product IDs */
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/* PCI Vendor/Product IDs */
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#define ET131X_PCI_VENDOR_ID 0x11C1 /* Agere Systems */
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#define ET131X_PCI_VENDOR_ID 0x11C1 /* Agere Systems */
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