perf vendor events arm64: Add common and uarch event JSON
Add a common and microarch JSON, which can be referenced from CPU JSONs. For now, brief and public description are as event brief event description from the ARMv8 ARM [0], D7-11. The list of events is not complete, as not all events will be referenced yet. Reference document is at the following: [0] https://documentation-service.arm.com/static/5fa3bd1eb209f547eebd4141?token= Signed-off-by: John Garry <john.garry@huawei.com> Acked-by: Will Deacon <will@kernel.org> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Nakamura, Shunsuke/中村 俊介 <nakamura.shun@fujitsu.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@openeuler.org Link: https://lore.kernel.org/r/1611835236-34696-3-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
John Garry
Arnaldo Carvalho de Melo
parent
2bf797be81
commit
c77669662f
248
tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json
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248
tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json
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[
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{
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"PublicDescription": "Instruction architecturally executed, Condition code check pass, software increment",
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"EventCode": "0x00",
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"EventName": "SW_INCR",
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"BriefDescription": "Instruction architecturally executed, Condition code check pass, software increment"
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},
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{
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"PublicDescription": "Level 1 instruction cache refill",
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"EventCode": "0x01",
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"EventName": "L1I_CACHE_REFILL",
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"BriefDescription": "Level 1 instruction cache refill"
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},
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{
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"PublicDescription": "Attributable Level 1 instruction TLB refill",
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"EventCode": "0x02",
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"EventName": "L1I_TLB_REFILL",
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"BriefDescription": "Attributable Level 1 instruction TLB refill"
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},
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{
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"PublicDescription": "Level 1 data cache refill",
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"EventCode": "0x03",
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"EventName": "L1D_CACHE_REFILL",
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"BriefDescription": "Level 1 data cache refill"
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},
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{
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"PublicDescription": "Level 1 data cache access",
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"EventCode": "0x04",
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"EventName": "L1D_CACHE",
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"BriefDescription": "Level 1 data cache access"
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},
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{
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"PublicDescription": "Attributable Level 1 data TLB refill",
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"EventCode": "0x05",
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"EventName": "L1D_TLB_REFILL",
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"BriefDescription": "Attributable Level 1 data TLB refill"
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},
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{
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"PublicDescription": "Instruction architecturally executed",
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"EventCode": "0x08",
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"EventName": "INST_RETIRED",
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"BriefDescription": "Instruction architecturally executed"
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},
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{
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"PublicDescription": "Exception taken",
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"EventCode": "0x09",
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"EventName": "EXC_TAKEN",
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"BriefDescription": "Exception taken"
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},
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{
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"PublicDescription": "Instruction architecturally executed, condition check pass, exception return",
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"EventCode": "0x0a",
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"EventName": "EXC_RETURN",
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"BriefDescription": "Instruction architecturally executed, condition check pass, exception return"
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},
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{
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"PublicDescription": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR",
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"EventCode": "0x0b",
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"EventName": "CID_WRITE_RETIRED",
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"BriefDescription": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR"
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},
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{
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"PublicDescription": "Mispredicted or not predicted branch speculatively executed",
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"EventCode": "0x10",
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"EventName": "BR_MIS_PRED",
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"BriefDescription": "Mispredicted or not predicted branch speculatively executed"
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},
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{
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"PublicDescription": "Cycle",
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"EventCode": "0x11",
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"EventName": "CPU_CYCLES",
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"BriefDescription": "Cycle"
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},
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{
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"PublicDescription": "Predictable branch speculatively executed",
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"EventCode": "0x12",
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"EventName": "BR_PRED",
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"BriefDescription": "Predictable branch speculatively executed"
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},
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{
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"PublicDescription": "Data memory access",
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"EventCode": "0x13",
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"EventName": "MEM_ACCESS",
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"BriefDescription": "Data memory access"
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},
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{
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"PublicDescription": "Attributable Level 1 instruction cache access",
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"EventCode": "0x14",
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"EventName": "L1I_CACHE",
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"BriefDescription": "Attributable Level 1 instruction cache access"
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},
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{
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"PublicDescription": "Attributable Level 1 data cache write-back",
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"EventCode": "0x15",
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"EventName": "L1D_CACHE_WB",
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"BriefDescription": "Attributable Level 1 data cache write-back"
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},
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{
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"PublicDescription": "Level 2 data cache access",
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"EventCode": "0x16",
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"EventName": "L2D_CACHE",
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"BriefDescription": "Level 2 data cache access"
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},
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{
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"PublicDescription": "Level 2 data refill",
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"EventCode": "0x17",
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"EventName": "L2D_CACHE_REFILL",
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"BriefDescription": "Level 2 data refill"
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},
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{
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"PublicDescription": "Attributable Level 2 data cache write-back",
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"EventCode": "0x18",
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"EventName": "L2D_CACHE_WB",
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"BriefDescription": "Attributable Level 2 data cache write-back"
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},
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{
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"PublicDescription": "Attributable Bus access",
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"EventCode": "0x19",
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"EventName": "BUS_ACCESS",
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"BriefDescription": "Attributable Bus access"
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},
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{
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"PublicDescription": "Local memory error",
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"EventCode": "0x1a",
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"EventName": "MEMORY_ERROR",
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"BriefDescription": "Local memory error"
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},
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{
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"PublicDescription": "Operation speculatively executed",
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"EventCode": "0x1b",
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"EventName": "INST_SPEC",
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"BriefDescription": "Operation speculatively executed"
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},
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{
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"PublicDescription": "Instruction architecturally executed, Condition code check pass, write to TTBR",
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"EventCode": "0x1c",
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"EventName": "TTBR_WRITE_RETIRED",
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"BriefDescription": "Instruction architecturally executed, Condition code check pass, write to TTBR"
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},
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{
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"PublicDescription": "Bus cycle",
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"EventCode": "0x1D",
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"EventName": "BUS_CYCLES",
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"BriefDescription": "Bus cycle"
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},
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{
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"PublicDescription": "Attributable Level 2 data cache allocation without refill",
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"EventCode": "0x20",
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"EventName": "L2D_CACHE_ALLOCATE",
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"BriefDescription": "Attributable Level 2 data cache allocation without refill"
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},
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{
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"PublicDescription": "Instruction architecturally executed, branch",
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"EventCode": "0x21",
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"EventName": "BR_RETIRED",
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"BriefDescription": "Instruction architecturally executed, branch"
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},
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{
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"PublicDescription": "Instruction architecturally executed, mispredicted branch",
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"EventCode": "0x22",
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"EventName": "BR_MIS_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, mispredicted branch"
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},
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{
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"PublicDescription": "No operation issued because of the frontend",
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"EventCode": "0x23",
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"EventName": "STALL_FRONTEND",
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"BriefDescription": "No operation issued because of the frontend"
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},
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{
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"PublicDescription": "No operation issued due to the backend",
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"EventCode": "0x24",
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"EventName": "STALL_BACKEND",
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"BriefDescription": "No operation issued due to the backend"
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},
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{
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"PublicDescription": "Attributable Level 1 data or unified TLB access",
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"EventCode": "0x25",
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"EventName": "L1D_TLB",
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"BriefDescription": "Attributable Level 1 data or unified TLB access"
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},
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{
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"PublicDescription": "Attributable Level 1 instruction TLB access",
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"EventCode": "0x26",
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"EventName": "L1I_TLB",
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"BriefDescription": "Attributable Level 1 instruction TLB access"
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},
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{
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"PublicDescription": "Attributable Level 3 data cache allocation without refill",
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"EventCode": "0x29",
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"EventName": "L3D_CACHE_ALLOCATE",
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"BriefDescription": "Attributable Level 3 data cache allocation without refill"
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},
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{
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"PublicDescription": "Attributable Level 3 data cache refill",
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"EventCode": "0x2A",
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"EventName": "L3D_CACHE_REFILL",
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"BriefDescription": "Attributable Level 3 data cache refill"
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},
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{
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"PublicDescription": "Attributable Level 3 data cache access",
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"EventCode": "0x2B",
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"EventName": "L3D_CACHE",
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"BriefDescription": "Attributable Level 3 data cache access"
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},
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{
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"PublicDescription": "Attributable Level 2 data TLB refill",
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"EventCode": "0x2D",
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"EventName": "L2D_TLB_REFILL",
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"BriefDescription": "Attributable Level 2 data TLB refill"
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},
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{
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"PublicDescription": "Attributable Level 2 data or unified TLB access",
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"EventCode": "0x2F",
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"EventName": "L2D_TLB",
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"BriefDescription": "Attributable Level 2 data or unified TLB access"
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},
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{
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"PublicDescription": "Access to another socket in a multi-socket system",
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"EventCode": "0x31",
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"EventName": "REMOTE_ACCESS",
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"BriefDescription": "Access to another socket in a multi-socket system"
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},
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{
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"PublicDescription": "Access to data TLB causes a translation table walk",
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"EventCode": "0x34",
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"EventName": "DTLB_WALK",
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"BriefDescription": "Access to data TLB causes a translation table walk"
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},
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{
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"PublicDescription": "Access to instruction TLB that causes a translation table walk",
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"EventCode": "0x35",
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"EventName": "ITLB_WALK",
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"BriefDescription": "Access to instruction TLB that causes a translation table walk"
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},
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{
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"PublicDescription": "Attributable Last level cache memory read",
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"EventCode": "0x36",
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"EventName": "LL_CACHE_RD",
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"BriefDescription": "Attributable Last level cache memory read"
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},
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{
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"PublicDescription": "Last level cache miss, read",
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"EventCode": "0x37",
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"EventName": "LL_CACHE_MISS_RD",
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"BriefDescription": "Last level cache miss, read"
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}
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]
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