MIPS: OCTEON: octeon-usb: add all register offsets
Glue code uses a mix of offset and absolute address register definition. Define all of them as offsets and use them consistently. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -17,6 +17,19 @@
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#include <asm/octeon/octeon.h>
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#define USBDRD_UCTL_CTL 0x00
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#define USBDRD_UCTL_BIST_STATUS 0x08
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#define USBDRD_UCTL_SPARE0 0x10
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#define USBDRD_UCTL_INTSTAT 0x30
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#define USBDRD_UCTL_PORT_CFG_HS(port) (0x40 + (0x20 * port))
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#define USBDRD_UCTL_PORT_CFG_SS(port) (0x48 + (0x20 * port))
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#define USBDRD_UCTL_PORT_CR_DBG_CFG(port) (0x50 + (0x20 * port))
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#define USBDRD_UCTL_PORT_CR_DBG_STATUS(port) (0x58 + (0x20 * port))
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#define USBDRD_UCTL_HOST_CFG 0xe0
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#define USBDRD_UCTL_SHIM_CFG 0xe8
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#define USBDRD_UCTL_ECC 0xf0
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#define USBDRD_UCTL_SPARE1 0xf8
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/* USB Control Register */
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union cvm_usbdrd_uctl_ctl {
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uint64_t u64;
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@ -227,7 +240,6 @@ static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
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static int dwc3_octeon_config_power(struct device *dev, u64 base)
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{
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#define UCTL_HOST_CFG 0xe0
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union cvm_usbdrd_uctl_host_cfg uctl_host_cfg;
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union cvmx_gpio_bit_cfgx gpio_bit;
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uint32_t gpio_pwr[3];
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@ -268,16 +280,16 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base)
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}
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/* Enable XHCI power control and set if active high or low. */
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uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
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uctl_host_cfg.u64 = cvmx_read_csr(base + USBDRD_UCTL_HOST_CFG);
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uctl_host_cfg.s.ppc_en = 1;
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uctl_host_cfg.s.ppc_active_high_en = !power_active_low;
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cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
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cvmx_write_csr(base + USBDRD_UCTL_HOST_CFG, uctl_host_cfg.u64);
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} else {
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/* Disable XHCI power control and set if active high. */
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uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
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uctl_host_cfg.u64 = cvmx_read_csr(base + USBDRD_UCTL_HOST_CFG);
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uctl_host_cfg.s.ppc_en = 0;
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uctl_host_cfg.s.ppc_active_high_en = 0;
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cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
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cvmx_write_csr(base + USBDRD_UCTL_HOST_CFG, uctl_host_cfg.u64);
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dev_info(dev, "power control disabled\n");
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}
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return 0;
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@ -464,10 +476,9 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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static void __init dwc3_octeon_set_endian_mode(u64 base)
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{
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#define UCTL_SHIM_CFG 0xe8
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union cvm_usbdrd_uctl_shim_cfg shim_cfg;
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shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG);
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shim_cfg.u64 = cvmx_read_csr(base + USBDRD_UCTL_SHIM_CFG);
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#ifdef __BIG_ENDIAN
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shim_cfg.s.dma_endian_mode = 1;
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shim_cfg.s.csr_endian_mode = 1;
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@ -475,20 +486,16 @@ static void __init dwc3_octeon_set_endian_mode(u64 base)
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shim_cfg.s.dma_endian_mode = 0;
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shim_cfg.s.csr_endian_mode = 0;
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#endif
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cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64);
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cvmx_write_csr(base + USBDRD_UCTL_SHIM_CFG, shim_cfg.u64);
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}
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#define CVMX_USBDRDX_UCTL_CTL(index) \
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(CVMX_ADD_IO_SEG(0x0001180068000000ull) + \
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((index & 1) * 0x1000000ull))
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static void __init dwc3_octeon_phy_reset(u64 base)
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{
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union cvm_usbdrd_uctl_ctl uctl_ctl;
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int index = (base >> 24) & 1;
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uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index));
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uctl_ctl.u64 = cvmx_read_csr(base + USBDRD_UCTL_CTL);
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uctl_ctl.s.uphy_rst = 0;
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cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64);
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cvmx_write_csr(base + USBDRD_UCTL_CTL, uctl_ctl.u64);
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}
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static int __init dwc3_octeon_device_init(void)
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