drm/xe: Add Wa_14015150844 for DG2 and Xe_LPG

The workaround database tells us to set this bit, even though the bspec
indicates the bit doesn't exist on these platforms.  Since this is a
write-only register, we also can't read back its value to verify whether
it's actually working or not.  For now we'll trust that the workaround
database knows what it's talking about; if not, the hardware will just
ignore the attempt to write to a non-existent bit and it shouldn't cause
any problems.

Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://lore.kernel.org/r/20230727220920.2291913-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-07-27 15:09:21 -07:00 committed by Rodrigo Vivi
parent 17d28aa8bd
commit c7e4a611f3
2 changed files with 12 additions and 0 deletions

View File

@ -328,6 +328,7 @@
#define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3)
#define RT_CTRL XE_REG_MCR(0xe530)
#define DIS_NULL_QUERY REG_BIT(10)

View File

@ -490,6 +490,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
*/
.read_mask = 0))
},
{ XE_RTP_NAME("14015150844"),
XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
XE_RTP_NOCHECK))
},
/* PVC */
@ -517,6 +522,12 @@ static const struct xe_rtp_entry_sr engine_was[] = {
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
},
{ XE_RTP_NAME("14015150844"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
XE_RTP_NOCHECK))
},
{}
};