dt-bindings: net: ti: k3-am654-cpsw-nuss: Add J721e CPSW9G support
Update bindings for TI K3 J721e SoC which contains 9 ports (8 external ports) CPSW9G module and add compatible for it. Changes made: - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G. - Extend pattern properties for new compatible. - Change maximum number of CPSW ports to 8 for new compatible. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
parent
d75858ef10
commit
c85b53e32c
@ -57,6 +57,7 @@ properties:
|
||||
- ti,am654-cpsw-nuss
|
||||
- ti,j7200-cpswxg-nuss
|
||||
- ti,j721e-cpsw-nuss
|
||||
- ti,j721e-cpswxg-nuss
|
||||
- ti,am642-cpsw-nuss
|
||||
|
||||
reg:
|
||||
@ -111,7 +112,7 @@ properties:
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^port@[1-4]$":
|
||||
"^port@[1-8]$":
|
||||
type: object
|
||||
description: CPSWxG NUSS external ports
|
||||
|
||||
@ -121,7 +122,7 @@ properties:
|
||||
properties:
|
||||
reg:
|
||||
minimum: 1
|
||||
maximum: 4
|
||||
maximum: 8
|
||||
description: CPSW port number
|
||||
|
||||
phys:
|
||||
@ -186,12 +187,36 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,j7200-cpswxg-nuss
|
||||
const: ti,j721e-cpswxg-nuss
|
||||
then:
|
||||
properties:
|
||||
ethernet-ports:
|
||||
patternProperties:
|
||||
"^port@[3-4]$": false
|
||||
"^port@[5-8]$": false
|
||||
"^port@[1-4]$":
|
||||
properties:
|
||||
reg:
|
||||
minimum: 1
|
||||
maximum: 4
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- ti,j721e-cpswxg-nuss
|
||||
- ti,j7200-cpswxg-nuss
|
||||
then:
|
||||
properties:
|
||||
ethernet-ports:
|
||||
patternProperties:
|
||||
"^port@[3-8]$": false
|
||||
"^port@[1-2]$":
|
||||
properties:
|
||||
reg:
|
||||
minimum: 1
|
||||
maximum: 2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user