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Merge branch 'phy-warn'

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Andrew Lunn says:

====================
drivers/net/phy C=1 W=1 fixes

This fixes most of the Sparse and W=1 warnings in drivers/net/phy. The
Cavium code is still not fully clean, but it might actually be the
strange code is confusing Sparse.

v2
--
Added RB, TB, AB.
s/case/cause
Reverse Christmas tree
Module soft dependencies
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2020-07-07 12:47:11 -07:00
commit c8658e5841
14 changed files with 33 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
View File

@ -961,7 +961,7 @@ static int octeon_mgmt_init_phy(struct net_device *netdev)
PHY_INTERFACE_MODE_MII);
if (!phydev)
return -ENODEV;
return -EPROBE_DEFER;
return 0;
}
@ -1554,12 +1554,8 @@ static struct platform_driver octeon_mgmt_driver = {
.remove = octeon_mgmt_remove,
};
extern void octeon_mdiobus_force_mod_depencency(void);
static int __init octeon_mgmt_mod_init(void)
{
/* Force our mdiobus driver module to be loaded first. */
octeon_mdiobus_force_mod_depencency();
return platform_driver_register(&octeon_mgmt_driver);
}
@ -1571,6 +1567,7 @@ static void __exit octeon_mgmt_mod_exit(void)
module_init(octeon_mgmt_mod_init);
module_exit(octeon_mgmt_mod_exit);
MODULE_SOFTDEP("pre: mdio-cavium");
MODULE_DESCRIPTION(DRV_DESCRIPTION);
MODULE_AUTHOR("David Daney");
MODULE_LICENSE("GPL");

12
drivers/net/phy/adin.c
View File

@ -106,8 +106,8 @@
/**
* struct adin_cfg_reg_map - map a config value to aregister value
* @cfg value in device configuration
* @reg value in the register
* @cfg: value in device configuration
* @reg: value in the register
*/
struct adin_cfg_reg_map {
int cfg;
@ -135,9 +135,9 @@ static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = {
/**
* struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22
* @devad device address used in Clause 45 access
* @cl45_regnum register address defined by Clause 45
* @adin_regnum equivalent register address accessible via Clause 22
* @devad: device address used in Clause 45 access
* @cl45_regnum: register address defined by Clause 45
* @adin_regnum: equivalent register address accessible via Clause 22
*/
struct adin_clause45_mmd_map {
int devad;
@ -174,7 +174,7 @@ static const struct adin_hw_stat adin_hw_stats[] = {
/**
* struct adin_priv - ADIN PHY driver private data
* stats statistic counters for the PHY
* @stats: statistic counters for the PHY
*/
struct adin_priv {
u64 stats[ARRAY_SIZE(adin_hw_stats)];

7
drivers/net/phy/at803x.c
View File

@ -400,8 +400,8 @@ static int at803x_parse_dt(struct phy_device *phydev)
{
struct device_node *node = phydev->mdio.dev.of_node;
struct at803x_priv *priv = phydev->priv;
unsigned int sel, mask;
u32 freq, strength;
unsigned int sel;
int ret;
if (!IS_ENABLED(CONFIG_OF_MDIO))
@ -409,7 +409,6 @@ static int at803x_parse_dt(struct phy_device *phydev)
ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
if (!ret) {
mask = AT803X_CLK_OUT_MASK;
switch (freq) {
case 25000000:
sel = AT803X_CLK_OUT_25MHZ_XTAL;
@ -428,8 +427,8 @@ static int at803x_parse_dt(struct phy_device *phydev)
return -EINVAL;
}
priv->clk_25m_reg |= FIELD_PREP(mask, sel);
priv->clk_25m_mask |= mask;
priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
/* Fixup for the AR8030/AR8035. This chip has another mask and
* doesn't support the DSP reference. Eg. the lowest bit of the

5
drivers/net/phy/dp83640.c
View File

@ -803,9 +803,10 @@ static int decode_evnt(struct dp83640_private *dp83640,
static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
{
u16 *seqid, hash;
unsigned int offset = 0;
u8 *msgtype, *data = skb_mac_header(skb);
__be16 *seqid;
u16 hash;
/* check sequenceID, messageType, 12 bit hash of offset 20-29 */
@ -836,7 +837,7 @@ static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
if (rxts->msgtype != (*msgtype & 0xf))
return 0;
seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
seqid = (__be16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
if (rxts->seqid != ntohs(*seqid))
return 0;

3
drivers/net/phy/mdio-boardinfo.c
View File

@ -17,7 +17,8 @@ static DEFINE_MUTEX(mdio_board_lock);
/**
* mdiobus_setup_mdiodev_from_board_info - create and setup MDIO devices
* from pre-collected board specific MDIO information
* @mdiodev: MDIO device pointer
* @bus: Bus the board_info belongs to
* @cb: Callback to create device on bus
* Context: can sleep
*/
void mdiobus_setup_mdiodev_from_board_info(struct mii_bus *bus,

14
drivers/net/phy/mdio-cavium.h
View File

@ -90,7 +90,7 @@ union cvmx_smix_wr_dat {
struct cavium_mdiobus {
struct mii_bus *mii_bus;
u64 register_base;
void __iomem *register_base;
enum cavium_mdiobus_mode mode;
};
@ -98,20 +98,20 @@ struct cavium_mdiobus {
#include <asm/octeon/octeon.h>
static inline void oct_mdio_writeq(u64 val, u64 addr)
static inline void oct_mdio_writeq(u64 val, void __iomem *addr)
{
cvmx_write_csr(addr, val);
cvmx_write_csr((u64 __force)addr, val);
}
static inline u64 oct_mdio_readq(u64 addr)
static inline u64 oct_mdio_readq(void __iomem *addr)
{
return cvmx_read_csr(addr);
return cvmx_read_csr((u64 __force)addr);
}
#else
#include <linux/io-64-nonatomic-lo-hi.h>
#define oct_mdio_writeq(val, addr) writeq(val, (void *)addr)
#define oct_mdio_readq(addr) readq((void *)addr)
#define oct_mdio_writeq(val, addr) writeq(val, addr)
#define oct_mdio_readq(addr) readq(addr)
#endif
int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum);

11
drivers/net/phy/mdio-octeon.c
View File

@ -44,8 +44,7 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
return -ENXIO;
}
bus->register_base =
(u64)devm_ioremap(&pdev->dev, mdio_phys, regsize);
bus->register_base = devm_ioremap(&pdev->dev, mdio_phys, regsize);
if (!bus->register_base) {
dev_err(&pdev->dev, "dev_ioremap failed\n");
return -ENOMEM;
@ -56,7 +55,7 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
bus->mii_bus->name = KBUILD_MODNAME;
snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base);
snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%px", bus->register_base);
bus->mii_bus->parent = &pdev->dev;
bus->mii_bus->read = cavium_mdiobus_read;
@ -109,12 +108,6 @@ static struct platform_driver octeon_mdiobus_driver = {
.remove = octeon_mdiobus_remove,
};
void octeon_mdiobus_force_mod_depencency(void)
{
/* Let ethernet drivers force us to be loaded. */
}
EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);
module_platform_driver(octeon_mdiobus_driver);
MODULE_DESCRIPTION("Cavium OCTEON MDIO bus driver");

2
drivers/net/phy/mdio-thunder.c
View File

@ -84,7 +84,7 @@ static int thunder_mdiobus_pci_probe(struct pci_dev *pdev,
nexus->buses[i] = bus;
i++;
bus->register_base = (u64)nexus->bar0 +
bus->register_base = nexus->bar0 +
r.start - pci_resource_start(pdev, 0);
smi_en.u64 = 0;

2
drivers/net/phy/mdio_device.c
View File

@ -181,7 +181,7 @@ static int mdio_remove(struct device *dev)
/**
* mdio_driver_register - register an mdio_driver with the MDIO layer
* @new_driver: new mdio_driver to register
* @drv: new mdio_driver to register
*/
int mdio_driver_register(struct mdio_driver *drv)
{

4
drivers/net/phy/phy_device.c
View File

@ -106,10 +106,9 @@ const int phy_10gbit_features_array[1] = {
};
EXPORT_SYMBOL_GPL(phy_10gbit_features_array);
const int phy_10gbit_fec_features_array[1] = {
static const int phy_10gbit_fec_features_array[1] = {
ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
};
EXPORT_SYMBOL_GPL(phy_10gbit_fec_features_array);
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
EXPORT_SYMBOL_GPL(phy_10gbit_full_features);
@ -227,7 +226,6 @@ static void phy_mdio_device_remove(struct mdio_device *mdiodev)
}
static struct phy_driver genphy_driver;
extern struct phy_driver genphy_c45_driver;
static LIST_HEAD(phy_fixup_list);
static DEFINE_MUTEX(phy_fixup_lock);

2
drivers/staging/octeon/ethernet-mdio.c
View File

@ -163,7 +163,7 @@ int cvm_oct_phy_setup_device(struct net_device *dev)
of_node_put(phy_node);
if (!phydev)
return -ENODEV;
return -EPROBE_DEFER;
priv->last_link = 0;
phy_start(phydev);

2
drivers/staging/octeon/ethernet-mdio.h
View File

@ -22,7 +22,5 @@
extern const struct ethtool_ops cvm_oct_ethtool_ops;
void octeon_mdiobus_force_mod_depencency(void);
int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
int cvm_oct_phy_setup_device(struct net_device *dev);

3
drivers/staging/octeon/ethernet.c
View File

@ -689,8 +689,6 @@ static int cvm_oct_probe(struct platform_device *pdev)
mtu_overhead += VLAN_HLEN;
#endif
octeon_mdiobus_force_mod_depencency();
pip = pdev->dev.of_node;
if (!pip) {
pr_err("Error: No 'pip' in /aliases\n");
@ -987,6 +985,7 @@ static struct platform_driver cvm_oct_driver = {
module_platform_driver(cvm_oct_driver);
MODULE_SOFTDEP("pre: mdio-cavium");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
MODULE_DESCRIPTION("Cavium Networks Octeon ethernet driver.");

3
include/linux/phy.h
View File

@ -1385,6 +1385,9 @@ int genphy_c45_pma_read_abilities(struct phy_device *phydev);
int genphy_c45_read_status(struct phy_device *phydev);
int genphy_c45_config_aneg(struct phy_device *phydev);
/* Generic C45 PHY driver */
extern struct phy_driver genphy_c45_driver;
/* The gen10g_* functions are the old Clause 45 stub */
int gen10g_config_aneg(struct phy_device *phydev);