drm/i915/hwmon: Expose card reactive critical power
Expose the card reactive critical (I1) power. I1 is exposed as power1_crit in microwatts (typically for client products) or as curr1_crit in milliamperes (typically for server). v2: Add curr1_crit functionality (Ashutosh) v3: Use HWMON_CHANNEL_INFO to define power1_crit, curr1_crit (Badal) v4: Use hwm_ prefix for static functions (Ashutosh) v5: KernelVersion: 6.2, Date: February 2023 in doc (Tvrtko) v6: Change contact to intel-gfx (Rodrigo) Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221013154526.2105579-6-ashutosh.dixit@intel.com
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@ -26,6 +26,32 @@ Description: RO. Card default power limit (default TDP setting).
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Only supported for particular Intel i915 graphics platforms.
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What: /sys/devices/.../hwmon/hwmon<i>/power1_crit
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Date: February 2023
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KernelVersion: 6.2
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Contact: intel-gfx@lists.freedesktop.org
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Description: RW. Card reactive critical (I1) power limit in microwatts.
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Card reactive critical (I1) power limit in microwatts is exposed
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for client products. The power controller will throttle the
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operating frequency if the power averaged over a window exceeds
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this limit.
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Only supported for particular Intel i915 graphics platforms.
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What: /sys/devices/.../hwmon/hwmon<i>/curr1_crit
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Date: February 2023
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KernelVersion: 6.2
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Contact: intel-gfx@lists.freedesktop.org
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Description: RW. Card reactive critical (I1) power limit in milliamperes.
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Card reactive critical (I1) power limit in milliamperes is
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exposed for server products. The power controller will throttle
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the operating frequency if the power averaged over a window
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exceeds this limit.
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Only supported for particular Intel i915 graphics platforms.
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What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
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Date: February 2023
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KernelVersion: 6.2
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@ -11,16 +11,19 @@
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#include "i915_hwmon.h"
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#include "i915_reg.h"
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#include "intel_mchbar_regs.h"
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#include "intel_pcode.h"
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#include "gt/intel_gt_regs.h"
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/*
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* SF_* - scale factors for particular quantities according to hwmon spec.
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* - voltage - millivolts
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* - power - microwatts
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* - curr - milliamperes
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* - energy - microjoules
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*/
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#define SF_VOLTAGE 1000
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#define SF_POWER 1000000
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#define SF_CURR 1000
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#define SF_ENERGY 1000000
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struct hwm_reg {
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@ -158,11 +161,25 @@ hwm_energy(struct hwm_drvdata *ddat, long *energy)
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static const struct hwmon_channel_info *hwm_info[] = {
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HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
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HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
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HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
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HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
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HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
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NULL
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};
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/* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
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static int hwm_pcode_read_i1(struct drm_i915_private *i915, u32 *uval)
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{
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return snb_pcode_read_p(&i915->uncore, PCODE_POWER_SETUP,
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POWER_SETUP_SUBCOMMAND_READ_I1, 0, uval);
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}
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static int hwm_pcode_write_i1(struct drm_i915_private *i915, u32 uval)
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{
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return snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP,
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POWER_SETUP_SUBCOMMAND_WRITE_I1, 0, uval);
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}
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static umode_t
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hwm_in_is_visible(const struct hwm_drvdata *ddat, u32 attr)
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{
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@ -198,13 +215,18 @@ hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val)
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static umode_t
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hwm_power_is_visible(const struct hwm_drvdata *ddat, u32 attr, int chan)
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{
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struct drm_i915_private *i915 = ddat->uncore->i915;
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struct i915_hwmon *hwmon = ddat->hwmon;
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u32 uval;
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switch (attr) {
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case hwmon_power_max:
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return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? 0664 : 0;
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case hwmon_power_rated_max:
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return i915_mmio_reg_valid(hwmon->rg.pkg_power_sku) ? 0444 : 0;
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case hwmon_power_crit:
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return (hwm_pcode_read_i1(i915, &uval) ||
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!(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
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default:
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return 0;
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}
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@ -214,6 +236,8 @@ static int
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hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)
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{
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struct i915_hwmon *hwmon = ddat->hwmon;
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int ret;
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u32 uval;
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switch (attr) {
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case hwmon_power_max:
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@ -230,6 +254,15 @@ hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)
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hwmon->scl_shift_power,
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SF_POWER);
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return 0;
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case hwmon_power_crit:
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ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval);
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if (ret)
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return ret;
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if (!(uval & POWER_SETUP_I1_WATTS))
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return -ENODEV;
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*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
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SF_POWER, POWER_SETUP_I1_SHIFT);
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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@ -239,6 +272,7 @@ static int
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hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
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{
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struct i915_hwmon *hwmon = ddat->hwmon;
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u32 uval;
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switch (attr) {
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case hwmon_power_max:
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@ -248,6 +282,9 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
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hwmon->scl_shift_power,
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SF_POWER, val);
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return 0;
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case hwmon_power_crit:
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uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_POWER);
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return hwm_pcode_write_i1(ddat->uncore->i915, uval);
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default:
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return -EOPNOTSUPP;
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}
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@ -280,6 +317,56 @@ hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long *val)
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}
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}
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static umode_t
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hwm_curr_is_visible(const struct hwm_drvdata *ddat, u32 attr)
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{
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struct drm_i915_private *i915 = ddat->uncore->i915;
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u32 uval;
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switch (attr) {
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case hwmon_curr_crit:
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return (hwm_pcode_read_i1(i915, &uval) ||
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(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
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default:
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return 0;
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}
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}
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static int
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hwm_curr_read(struct hwm_drvdata *ddat, u32 attr, long *val)
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{
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int ret;
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u32 uval;
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switch (attr) {
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case hwmon_curr_crit:
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ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval);
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if (ret)
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return ret;
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if (uval & POWER_SETUP_I1_WATTS)
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return -ENODEV;
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*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
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SF_CURR, POWER_SETUP_I1_SHIFT);
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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}
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static int
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hwm_curr_write(struct hwm_drvdata *ddat, u32 attr, long val)
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{
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u32 uval;
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switch (attr) {
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case hwmon_curr_crit:
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uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_CURR);
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return hwm_pcode_write_i1(ddat->uncore->i915, uval);
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default:
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return -EOPNOTSUPP;
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}
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}
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static umode_t
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hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
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u32 attr, int channel)
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@ -293,6 +380,8 @@ hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
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return hwm_power_is_visible(ddat, attr, channel);
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case hwmon_energy:
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return hwm_energy_is_visible(ddat, attr);
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case hwmon_curr:
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return hwm_curr_is_visible(ddat, attr);
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default:
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return 0;
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}
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@ -311,6 +400,8 @@ hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
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return hwm_power_read(ddat, attr, channel, val);
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case hwmon_energy:
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return hwm_energy_read(ddat, attr, val);
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case hwmon_curr:
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return hwm_curr_read(ddat, attr, val);
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default:
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return -EOPNOTSUPP;
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}
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@ -325,6 +416,8 @@ hwm_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
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switch (type) {
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case hwmon_power:
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return hwm_power_write(ddat, attr, channel, val);
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case hwmon_curr:
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return hwm_curr_write(ddat, attr, val);
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default:
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return -EOPNOTSUPP;
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}
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@ -6650,6 +6650,12 @@
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#define DG1_PCODE_STATUS 0x7E
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#define DG1_UNCORE_GET_INIT_STATUS 0x0
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#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
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#define PCODE_POWER_SETUP 0x7C
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#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
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#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
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#define POWER_SETUP_I1_WATTS REG_BIT(31)
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#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
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#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
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#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
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#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
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/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
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