net: hns3: refactor dev capability and dev spec of debugfs
Currently, the debugfs command for dev capability and dev spec are implemented by "echo xxxx > cmd", and record the information in dmesg. It's unnecessary and heavy. To improve it, create a single file "dev_info" for them, and query them by command "cat dev_info", return the result to userspace, rather than record in dmesg. The display style is below: $cat dev_info dev capability: support FD: yes support GRO: yes support FEC: yes support UDP GSO: no support PTP: no support INT QL: no support HW TX csum: no support UDP tunnel csum: no support TX push: no support imp-controlled PHY: no support rxd advanced layout: no dev spec: MAC entry num: 0 MNG entry num: 0 MAX non tso bd num: 8 RSS ind tbl size: 512 RSS key size: 40 RSS size: 1 Allocated RSS size: 0 Task queue pairs numbers: 1 RX buffer length: 2048 Desc num per TX queue: 1024 Desc num per RX queue: 1024 Total number of enabled TCs: 1 MAX INT QL: 0 MAX INT GL: 8160 MAX TM RATE: 100000 MAX QSET number: 1024 Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jiaran Zhang
David S. Miller
parent
5e69ea7ee2
commit
c929bc2ac3
@ -254,6 +254,7 @@ enum hnae3_dbg_cmd {
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HNAE3_DBG_CMD_TM_NODES,
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HNAE3_DBG_CMD_TM_PRI,
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HNAE3_DBG_CMD_TM_QSET,
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HNAE3_DBG_CMD_DEV_INFO,
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HNAE3_DBG_CMD_UNKNOWN,
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};
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@ -45,6 +45,50 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
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.buf_len = HNS3_DBG_READ_LEN,
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.init = hns3_dbg_common_file_init,
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},
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{
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.name = "dev_info",
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.cmd = HNAE3_DBG_CMD_DEV_INFO,
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.dentry = HNS3_DBG_DENTRY_COMMON,
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.buf_len = HNS3_DBG_READ_LEN,
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.init = hns3_dbg_common_file_init,
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},
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};
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static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
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{
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.name = "support FD",
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.cap_bit = HNAE3_DEV_SUPPORT_FD_B,
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}, {
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.name = "support GRO",
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.cap_bit = HNAE3_DEV_SUPPORT_GRO_B,
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}, {
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.name = "support FEC",
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.cap_bit = HNAE3_DEV_SUPPORT_FEC_B,
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}, {
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.name = "support UDP GSO",
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.cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B,
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}, {
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.name = "support PTP",
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.cap_bit = HNAE3_DEV_SUPPORT_PTP_B,
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}, {
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.name = "support INT QL",
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.cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B,
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}, {
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.name = "support HW TX csum",
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.cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
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}, {
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.name = "support UDP tunnel csum",
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.cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
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}, {
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.name = "support TX push",
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.cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B,
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}, {
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.name = "support imp-controlled PHY",
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.cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B,
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}, {
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.name = "support rxd advanced layout",
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.cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
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},
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};
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static int hns3_dbg_queue_info(struct hnae3_handle *h,
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@ -320,8 +364,6 @@ static void hns3_dbg_help(struct hnae3_handle *h)
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dev_info(&h->pdev->dev, "queue info <number>\n");
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dev_info(&h->pdev->dev, "queue map\n");
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dev_info(&h->pdev->dev, "bd info <q_num> <bd index>\n");
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dev_info(&h->pdev->dev, "dev capability\n");
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dev_info(&h->pdev->dev, "dev spec\n");
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if (!hns3_is_phys_func(h->pdev))
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return;
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@ -363,68 +405,78 @@ static void hns3_dbg_help(struct hnae3_handle *h)
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dev_info(&h->pdev->dev, "%s", printf_buf);
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}
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static void hns3_dbg_dev_caps(struct hnae3_handle *h)
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static void
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hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos)
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{
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struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
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unsigned long *caps;
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static const char * const str[] = {"no", "yes"};
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unsigned long *caps = ae_dev->caps;
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u32 i, state;
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caps = ae_dev->caps;
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*pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n");
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dev_info(&h->pdev->dev, "support FD: %s\n",
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test_bit(HNAE3_DEV_SUPPORT_FD_B, caps) ? "yes" : "no");
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dev_info(&h->pdev->dev, "support GRO: %s\n",
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test_bit(HNAE3_DEV_SUPPORT_GRO_B, caps) ? "yes" : "no");
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dev_info(&h->pdev->dev, "support FEC: %s\n",
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test_bit(HNAE3_DEV_SUPPORT_FEC_B, caps) ? "yes" : "no");
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dev_info(&h->pdev->dev, "support UDP GSO: %s\n",
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test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, caps) ? "yes" : "no");
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dev_info(&h->pdev->dev, "support PTP: %s\n",
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test_bit(HNAE3_DEV_SUPPORT_PTP_B, caps) ? "yes" : "no");
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dev_info(&h->pdev->dev, "support INT QL: %s\n",
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test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, caps) ? "yes" : "no");
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dev_info(&h->pdev->dev, "support HW TX csum: %s\n",
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test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, caps) ? "yes" : "no");
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dev_info(&h->pdev->dev, "support UDP tunnel csum: %s\n",
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test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, caps) ?
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"yes" : "no");
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dev_info(&h->pdev->dev, "support PAUSE: %s\n",
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test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps) ?
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"yes" : "no");
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dev_info(&h->pdev->dev, "support imp-controlled PHY: %s\n",
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test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, caps) ? "yes" : "no");
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dev_info(&h->pdev->dev, "support rxd advanced layout: %s\n",
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test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, caps) ?
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"yes" : "no");
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for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) {
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state = test_bit(hns3_dbg_cap[i].cap_bit, caps);
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*pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n",
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hns3_dbg_cap[i].name, str[state]);
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}
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*pos += scnprintf(buf + *pos, len - *pos, "\n");
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}
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static void hns3_dbg_dev_specs(struct hnae3_handle *h)
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static void
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hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos)
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{
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struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
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struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs;
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struct hnae3_knic_private_info *kinfo = &h->kinfo;
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struct hns3_nic_priv *priv = h->priv;
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dev_info(priv->dev, "MAC entry num: %u\n", dev_specs->mac_entry_num);
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dev_info(priv->dev, "MNG entry num: %u\n", dev_specs->mng_entry_num);
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dev_info(priv->dev, "MAX non tso bd num: %u\n",
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dev_specs->max_non_tso_bd_num);
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dev_info(priv->dev, "RSS ind tbl size: %u\n",
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dev_specs->rss_ind_tbl_size);
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dev_info(priv->dev, "RSS key size: %u\n", dev_specs->rss_key_size);
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dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
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dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
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dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
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*pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n");
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*pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n",
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dev_specs->mac_entry_num);
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*pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n",
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dev_specs->mng_entry_num);
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*pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n",
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dev_specs->max_non_tso_bd_num);
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*pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n",
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dev_specs->rss_ind_tbl_size);
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*pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n",
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dev_specs->rss_key_size);
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*pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n",
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kinfo->rss_size);
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*pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n",
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kinfo->req_rss_size);
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*pos += scnprintf(buf + *pos, len - *pos,
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"Task queue pairs numbers: %u\n",
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kinfo->num_tqps);
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*pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n",
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kinfo->rx_buf_len);
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*pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n",
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kinfo->num_tx_desc);
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*pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n",
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kinfo->num_rx_desc);
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*pos += scnprintf(buf + *pos, len - *pos,
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"Total number of enabled TCs: %u\n",
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kinfo->tc_info.num_tc);
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*pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n",
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dev_specs->int_ql_max);
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*pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n",
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dev_specs->max_int_gl);
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*pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n",
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dev_specs->max_tm_rate);
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*pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n",
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dev_specs->max_qset_num);
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}
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dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
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dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
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dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
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dev_info(priv->dev, "Total number of enabled TCs: %u\n",
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kinfo->tc_info.num_tc);
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dev_info(priv->dev, "MAX INT QL: %u\n", dev_specs->int_ql_max);
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dev_info(priv->dev, "MAX INT GL: %u\n", dev_specs->max_int_gl);
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dev_info(priv->dev, "MAX frame size: %u\n", dev_specs->max_frm_size);
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dev_info(priv->dev, "MAX TM RATE: %uMbps\n", dev_specs->max_tm_rate);
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dev_info(priv->dev, "MAX QSET number: %u\n", dev_specs->max_qset_num);
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static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len)
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{
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int pos = 0;
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hns3_dbg_dev_caps(h, buf, len, &pos);
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hns3_dbg_dev_specs(h, buf, len, &pos);
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return 0;
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}
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static ssize_t hns3_dbg_cmd_read(struct file *filp, char __user *buffer,
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@ -468,10 +520,6 @@ static int hns3_dbg_check_cmd(struct hnae3_handle *handle, char *cmd_buf)
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ret = hns3_dbg_queue_map(handle);
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else if (strncmp(cmd_buf, "bd info", 7) == 0)
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ret = hns3_dbg_bd_info(handle, cmd_buf);
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else if (strncmp(cmd_buf, "dev capability", 14) == 0)
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hns3_dbg_dev_caps(handle);
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else if (strncmp(cmd_buf, "dev spec", 8) == 0)
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hns3_dbg_dev_specs(handle);
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else if (handle->ae_algo->ops->dbg_run_cmd)
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ret = handle->ae_algo->ops->dbg_run_cmd(handle, cmd_buf);
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else
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@ -545,10 +593,23 @@ static int hns3_dbg_get_cmd_index(struct hnae3_handle *handle,
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return -EINVAL;
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}
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static const struct hns3_dbg_func hns3_dbg_cmd_func[] = {
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{
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.cmd = HNAE3_DBG_CMD_DEV_INFO,
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.dbg_dump = hns3_dbg_dev_info,
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},
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};
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static int hns3_dbg_read_cmd(struct hnae3_handle *handle,
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enum hnae3_dbg_cmd cmd, char *buf, int len)
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{
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const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
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u32 i;
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for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) {
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if (cmd == hns3_dbg_cmd_func[i].cmd)
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return hns3_dbg_cmd_func[i].dbg_dump(handle, buf, len);
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}
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if (!ops->dbg_read_cmd)
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return -EOPNOTSUPP;
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@ -26,4 +26,14 @@ struct hns3_dbg_cmd_info {
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int (*init)(struct hnae3_handle *handle, unsigned int cmd);
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};
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struct hns3_dbg_func {
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enum hnae3_dbg_cmd cmd;
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int (*dbg_dump)(struct hnae3_handle *handle, char *buf, int len);
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};
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struct hns3_dbg_cap_info {
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const char *name;
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enum HNAE3_DEV_CAP_BITS cap_bit;
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};
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#endif
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