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RISC-V Devicetrees for v6.5

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StarFive:
 Watchdog nodes for both the JH7110 & its forerunner, the JH7100. PMU, P
 being power, support for the JH7110. PMIC and frequency scaling support
 for the JH7110 equipped VisionFive 2.
 Most of the DT bits for the JH7110, and the SBCs using it, are pending
 support for one of the clock controllers, so it's a smaller set of
 changes than I would have hoped for.
 
 Misc:
 Pick up some dt-binding cleanup that Palmer assigned to me & had no
 uptake from the respective maintainers. My powers of estimation failed
 me again, with part of my motivation for picking them up being the
 addition of new platforms that ended up not making it. Hopefully next
 window for those, as they were relatively close.
 Exclude the Allwinner and Renesas subdirectories from the Misc.
 MAINTAINERS entry, since I do not take care of those.
 
 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Merge tag 'riscv-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

RISC-V Devicetrees for v6.5

StarFive:
Watchdog nodes for both the JH7110 & its forerunner, the JH7100. PMU, P
being power, support for the JH7110. PMIC and frequency scaling support
for the JH7110 equipped VisionFive 2.
Most of the DT bits for the JH7110, and the SBCs using it, are pending
support for one of the clock controllers, so it's a smaller set of
changes than I would have hoped for.

Misc:
Pick up some dt-binding cleanup that Palmer assigned to me & had no
uptake from the respective maintainers. My powers of estimation failed
me again, with part of my motivation for picking them up being the
addition of new platforms that ended up not making it. Hopefully next
window for those, as they were relatively close.
Exclude the Allwinner and Renesas subdirectories from the Misc.
MAINTAINERS entry, since I do not take care of those.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: Add cpu scaling for JH7110 SoC
  riscv: dts: starfive: Enable axp15060 pmic for cpufreq
  dt-bindings: interrupt-controller: sifive,plic: Sort compatible values
  dt-bindings: timer: sifive,clint: Clean up compatible value section
  riscv: dts: starfive: jh7110: Add watchdog node
  riscv: dts: starfive: jh7100: Add watchdog node
  riscv: dts: starfive: Add PMU controller node
  MAINTAINERS: exclude maintained subdirs in RISC-V misc DT entry

Link: https://lore.kernel.org/r/20230612-fasting-floss-0bc05a08bc7a@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-06-20 22:49:35 +02:00
commit c9a5aa0e53
6 changed files with 104 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View File

@ -57,10 +57,10 @@ properties:
- const: andestech,nceplic100
- items:
- enum:
- canaan,k210-plic
- sifive,fu540-c000-plic
- starfive,jh7100-plic
- starfive,jh7110-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
- items:
- enum:

21
Documentation/devicetree/bindings/timer/sifive,clint.yaml
View File

@ -29,11 +29,11 @@ properties:
oneOf:
- items:
- enum:
- sifive,fu540-c000-clint
- starfive,jh7100-clint
- starfive,jh7110-clint
- canaan,k210-clint
- const: sifive,clint0
- canaan,k210-clint # Canaan Kendryte K210
- sifive,fu540-c000-clint # SiFive FU540
- starfive,jh7100-clint # StarFive JH7100
- starfive,jh7110-clint # StarFive JH7110
- const: sifive,clint0 # SiFive CLINT v0 IP block
- items:
- enum:
- allwinner,sun20i-d1-clint
@ -45,14 +45,9 @@ properties:
description: For the QEMU virt machine only
description:
Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
Supported compatible strings are -
"sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and
"sifive,clint0" for the SiFive CLINT v0 IP block with no chip
integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details
Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
when compatible with a SiFive CLINT. Please refer to
sifive-blocks-ip-versioning.txt for details regarding the latter.
reg:
maxItems: 1

2
MAINTAINERS
View File

@ -18150,6 +18150,8 @@ Q: https://patchwork.kernel.org/project/linux-riscv/list/
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F: Documentation/devicetree/bindings/riscv/
F: arch/riscv/boot/dts/
X: arch/riscv/boot/dts/allwinner/
X: arch/riscv/boot/dts/renesas/
RISC-V PMU DRIVERS
M: Atish Patra <atishp@atishpatra.org>

10
arch/riscv/boot/dts/starfive/jh7100.dtsi
View File

@ -238,5 +238,15 @@
#size-cells = <0>;
status = "disabled";
};
watchdog@12480000 {
compatible = "starfive,jh7100-wdt";
reg = <0x0 0x12480000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
<&clkgen JH7100_CLK_WDT_CORE>;
clock-names = "apb", "core";
resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
<&rstgen JH7100_RSTN_WDT>;
};
};
};

33
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
View File

@ -114,6 +114,23 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
status = "okay";
axp15060: pmic@36 {
compatible = "x-powers,axp15060";
reg = <0x36>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
regulators {
vdd_cpu: dcdc2 {
regulator-always-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1540000>;
regulator-name = "vdd-cpu";
};
};
};
};
&i2c6 {
@ -213,3 +230,19 @@
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&U74_1 {
cpu-supply = <&vdd_cpu>;
};
&U74_2 {
cpu-supply = <&vdd_cpu>;
};
&U74_3 {
cpu-supply = <&vdd_cpu>;
};
&U74_4 {
cpu-supply = <&vdd_cpu>;
};

50
arch/riscv/boot/dts/starfive/jh7110.dtsi
View File

@ -53,6 +53,9 @@
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@ -79,6 +82,9 @@
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@ -105,6 +111,9 @@
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@ -131,6 +140,9 @@
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@ -164,6 +176,27 @@
};
};
cpu_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-375000000 {
opp-hz = /bits/ 64 <375000000>;
opp-microvolt = <800000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <800000>;
};
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
opp-microvolt = <800000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1040000>;
};
};
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac0_rgmii_rxin";
@ -469,6 +502,16 @@
#gpio-cells = <2>;
};
watchdog@13070000 {
compatible = "starfive,jh7110-wdt";
reg = <0x0 0x13070000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
<&syscrg JH7110_SYSCLK_WDT_CORE>;
clock-names = "apb", "core";
resets = <&syscrg JH7110_SYSRST_WDT_APB>,
<&syscrg JH7110_SYSRST_WDT_CORE>;
};
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
@ -496,5 +539,12 @@
gpio-controller;
#gpio-cells = <2>;
};
pwrc: power-controller@17030000 {
compatible = "starfive,jh7110-pmu";
reg = <0x0 0x17030000 0x0 0x10000>;
interrupts = <111>;
#power-domain-cells = <1>;
};
};
};