x86: unify tss_struct
Although slighly different, the tss_struct is very similar in x86_64 and i386. The really different part, which matchs the hardware vision of it, is now called x86_hw_tss, and each of the architectures provides yours. It's then used as a field in the outter tss_struct. Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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0ccb8acc51
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@ -110,7 +110,7 @@ int main(void)
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ENTRY(cr8);
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BLANK();
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#undef ENTRY
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DEFINE(TSS_ist, offsetof(struct tss_struct, ist));
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DEFINE(TSS_ist, offsetof(struct tss_struct, x86_tss.ist));
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BLANK();
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DEFINE(crypto_tfm_ctx_offset, offsetof(struct crypto_tfm, __crt_ctx));
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BLANK();
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@ -33,7 +33,7 @@ static void doublefault_fn(void)
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printk(KERN_EMERG "double fault, tss at %08lx\n", tss);
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if (ptr_ok(tss)) {
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struct i386_hw_tss *t = (struct i386_hw_tss *)tss;
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struct x86_hw_tss *t = (struct x86_hw_tss *)tss;
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printk(KERN_EMERG "eip = %08lx, esp = %08lx\n",
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t->ip, t->sp);
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@ -639,7 +639,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
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/*
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* Reload esp0, LDT and the page table pointer:
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*/
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tss->sp0 = next->sp0;
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tss->x86_tss.sp0 = next->sp0;
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/*
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* Switch DS and ES.
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@ -258,10 +258,10 @@ void __cpuinit cpu_init (void)
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v, cpu);
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}
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estacks += PAGE_SIZE << order[v];
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orig_ist->ist[v] = t->ist[v] = (unsigned long)estacks;
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orig_ist->ist[v] = t->x86_tss.ist[v] = (unsigned long)estacks;
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}
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t->io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
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t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
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/*
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* <= is required because the CPU will access up to
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* 8 bits beyond the end of the IO permission bitmap.
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@ -614,7 +614,7 @@ do_rest:
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start_rip = setup_trampoline();
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init_rsp = c_idle.idle->thread.sp;
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per_cpu(init_tss,cpu).sp0 = init_rsp;
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per_cpu(init_tss, cpu).x86_tss.sp0 = init_rsp;
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initial_code = start_secondary;
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clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
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@ -51,7 +51,7 @@ struct lguest_ro_state
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/* Fields which are used when guest is running. */
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struct desc_ptr guest_idt_desc;
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struct desc_ptr guest_gdt_desc;
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struct i386_hw_tss guest_tss;
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struct x86_hw_tss guest_tss;
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struct desc_struct guest_idt[IDT_ENTRIES];
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struct desc_struct guest_gdt[GDT_ENTRIES];
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};
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@ -8,6 +8,7 @@ struct task_struct;
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struct mm_struct;
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#include <asm/page.h>
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#include <asm/percpu.h>
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#include <asm/system.h>
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/*
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@ -38,6 +39,82 @@ static inline void load_cr3(pgd_t *pgdir)
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write_cr3(__pa(pgdir));
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}
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#ifdef CONFIG_X86_32
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/* This is the TSS defined by the hardware. */
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struct x86_hw_tss {
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unsigned short back_link, __blh;
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unsigned long sp0;
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unsigned short ss0, __ss0h;
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unsigned long sp1;
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unsigned short ss1, __ss1h; /* ss1 caches MSR_IA32_SYSENTER_CS */
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unsigned long sp2;
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unsigned short ss2, __ss2h;
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unsigned long __cr3;
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unsigned long ip;
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unsigned long flags;
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unsigned long ax, cx, dx, bx;
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unsigned long sp, bp, si, di;
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unsigned short es, __esh;
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unsigned short cs, __csh;
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unsigned short ss, __ssh;
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unsigned short ds, __dsh;
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unsigned short fs, __fsh;
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unsigned short gs, __gsh;
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unsigned short ldt, __ldth;
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unsigned short trace, io_bitmap_base;
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} __attribute__((packed));
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#else
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struct x86_hw_tss {
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u32 reserved1;
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u64 sp0;
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u64 sp1;
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u64 sp2;
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u64 reserved2;
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u64 ist[7];
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u32 reserved3;
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u32 reserved4;
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u16 reserved5;
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u16 io_bitmap_base;
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} __attribute__((packed)) ____cacheline_aligned;
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#endif
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/*
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* Size of io_bitmap.
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*/
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#define IO_BITMAP_BITS 65536
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#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
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#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
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#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
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#define INVALID_IO_BITMAP_OFFSET 0x8000
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#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
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struct tss_struct {
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struct x86_hw_tss x86_tss;
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/*
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* The extra 1 is there because the CPU will access an
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* additional byte beyond the end of the IO permission
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* bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
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/*
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* Cache the current maximum and the last task that used the bitmap:
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*/
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unsigned long io_bitmap_max;
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struct thread_struct *io_bitmap_owner;
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/*
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* pads the TSS to be cacheline-aligned (size is 0x100)
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*/
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unsigned long __cacheline_filler[35];
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/*
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* .. and then another 0x100 bytes for emergency kernel stack
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*/
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unsigned long stack[64];
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} __attribute__((packed));
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DECLARE_PER_CPU(struct tss_struct, init_tss);
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#ifdef CONFIG_X86_32
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# include "processor_32.h"
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#else
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@ -81,7 +81,6 @@ struct cpuinfo_x86 {
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extern struct cpuinfo_x86 boot_cpu_data;
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extern struct cpuinfo_x86 new_cpu_data;
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extern struct tss_struct doublefault_tss;
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DECLARE_PER_CPU(struct tss_struct, init_tss);
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#ifdef CONFIG_SMP
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DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
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@ -123,16 +122,6 @@ extern unsigned int mca_pentium_flag;
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#define TASK_SIZE (PAGE_OFFSET)
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/*
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* Size of io_bitmap.
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*/
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#define IO_BITMAP_BITS 65536
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#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
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#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
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#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
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#define INVALID_IO_BITMAP_OFFSET 0x8000
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#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
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struct i387_fsave_struct {
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long cwd;
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long swd;
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@ -185,57 +174,6 @@ typedef struct {
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unsigned long seg;
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} mm_segment_t;
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struct thread_struct;
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/* This is the TSS defined by the hardware. */
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struct i386_hw_tss {
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unsigned short back_link,__blh;
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unsigned long sp0;
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unsigned short ss0,__ss0h;
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unsigned long sp1;
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unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
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unsigned long sp2;
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unsigned short ss2,__ss2h;
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unsigned long __cr3;
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unsigned long ip;
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unsigned long flags;
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unsigned long ax, cx, dx, bx;
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unsigned long sp, bp, si, di;
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unsigned short es, __esh;
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unsigned short cs, __csh;
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unsigned short ss, __ssh;
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unsigned short ds, __dsh;
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unsigned short fs, __fsh;
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unsigned short gs, __gsh;
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unsigned short ldt, __ldth;
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unsigned short trace, io_bitmap_base;
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} __attribute__((packed));
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struct tss_struct {
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struct i386_hw_tss x86_tss;
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/*
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* The extra 1 is there because the CPU will access an
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* additional byte beyond the end of the IO permission
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* bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
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/*
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* Cache the current maximum and the last task that used the bitmap:
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*/
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unsigned long io_bitmap_max;
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struct thread_struct *io_bitmap_owner;
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/*
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* pads the TSS to be cacheline-aligned (size is 0x100)
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*/
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unsigned long __cacheline_filler[35];
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/*
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* .. and then another 0x100 bytes for emergency kernel stack
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*/
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unsigned long stack[64];
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} __attribute__((packed));
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#define ARCH_MIN_TASKALIGN 16
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struct thread_struct {
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@ -91,14 +91,6 @@ extern void identify_cpu(struct cpuinfo_x86 *);
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#define TASK_SIZE (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
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#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
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/*
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* Size of io_bitmap.
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*/
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#define IO_BITMAP_BITS 65536
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#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
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#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
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#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
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#define INVALID_IO_BITMAP_OFFSET 0x8000
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struct i387_fxsave_struct {
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u16 cwd;
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@ -118,32 +110,7 @@ union i387_union {
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struct i387_fxsave_struct fxsave;
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};
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struct tss_struct {
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u32 reserved1;
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u64 sp0;
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u64 sp1;
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u64 sp2;
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u64 reserved2;
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u64 ist[7];
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u32 reserved3;
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u32 reserved4;
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u16 reserved5;
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u16 io_bitmap_base;
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/*
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* The extra 1 is there because the CPU will access an
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* additional byte beyond the end of the IO permission
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* bitmap. The extra byte must be all 1 bits, and must
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* be within the limit. Thus we have:
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*
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* 128 bytes, the bitmap itself, for ports 0..0x3ff
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* 8 bytes, for an extra "long" of ~0UL
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*/
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unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
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} __attribute__((packed)) ____cacheline_aligned;
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extern struct cpuinfo_x86 boot_cpu_data;
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DECLARE_PER_CPU(struct tss_struct,init_tss);
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/* Save the original ist values for checking stack pointers during debugging */
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struct orig_ist {
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unsigned long ist[7];
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@ -195,7 +162,7 @@ struct thread_struct {
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}
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#define INIT_TSS { \
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.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
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.x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
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}
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#define INIT_MMAP \
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