drm/radeon/r600_cs: Fix possible int overflows in r600_cs_check_reg()
[ Upstream commit 39c960bbf9d9ea862398759e75736cfb68c3446f ] While improbable, there may be a chance of hitting integer overflow when the result of radeon_get_ib_value() gets shifted left. Avoid it by casting one of the operands to larger data type (u64). Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 1729dd33d20b ("drm/radeon/kms: r600 CS parser fixes") Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -1276,7 +1276,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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return -EINVAL;
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}
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tmp = (reg - CB_COLOR0_BASE) / 4;
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track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
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track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
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ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
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track->cb_color_base_last[tmp] = ib[idx];
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track->cb_color_bo[tmp] = reloc->robj;
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@ -1303,7 +1303,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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"0x%04X\n", reg);
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return -EINVAL;
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}
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track->htile_offset = radeon_get_ib_value(p, idx) << 8;
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track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;
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ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
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track->htile_bo = reloc->robj;
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track->db_dirty = true;
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