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- fix GC7000 TX clock gating

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- revert NPU UAPI changes
 -----BEGIN PGP SIGNATURE-----
 
 iQFLBAABCAA1FiEEz9DmVLy+XdLQMNIiz8wpfG0KEgsFAmYqgnwXHGwuc3RhY2hA
 cGVuZ3V0cm9uaXguZGUACgkQz8wpfG0KEgt63gf+O+d7WAM6XovVkGdWF07HJ+o3
 3pN+axXtRORo3cMzfGOQuqbk34cNaY5U+O1qoh8sfcHx+79yx+A2PpE3dCGdWLZi
 dWkQ+0miYFFh/sSkfTIiMVlFN1LdDKcatNFBoZJX7QYGoUd1CxVktdyttR8o1+I7
 khT41VmR4owFTgjmy/ypOJdWFX2jLUS3T8vdxAI1DW8ActVTpODJxxFjH6MUnhej
 3N9aY3Lh55Z4RY6pBrUSwguzrt+VXdUOBzZ5zGVk2wwE1h1TToglQznFEgNo1zJp
 FoUd1YMqBIfvtyysm/KY8d9udIpjW0wknSnEpREs7hqdo4y9i9klgNRUrRgmaw==
 =t59K
 -----END PGP SIGNATURE-----

Merge tag 'drm-etnaviv-fixes-2024-04-25' of https://git.pengutronix.de/git/lst/linux into drm-fixes

- fix GC7000 TX clock gating
- revert NPU UAPI changes

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Lucas Stach <l.stach@pengutronix.de>
Link: https://patchwork.freedesktop.org/patch/msgid/c24457dc18ba9eab3ff919b398a25b1af9f1124e.camel@pengutronix.de
This commit is contained in:
Dave Airlie 2024-04-26 12:50:23 +10:00
commit ca382d6aa5
4 changed files with 2 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/gpu/drm/etnaviv/etnaviv_gpu.c
View File

@ -164,26 +164,6 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
*value = gpu->identity.eco_id;
break;
case ETNAVIV_PARAM_GPU_NN_CORE_COUNT:
*value = gpu->identity.nn_core_count;
break;
case ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE:
*value = gpu->identity.nn_mad_per_core;
break;
case ETNAVIV_PARAM_GPU_TP_CORE_COUNT:
*value = gpu->identity.tp_core_count;
break;
case ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE:
*value = gpu->identity.on_chip_sram_size;
break;
case ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE:
*value = gpu->identity.axi_sram_size;
break;
default:
DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
return -EINVAL;
@ -663,8 +643,8 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
/* Disable TX clock gating on affected core revisions. */
if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
etnaviv_is_model_rev(gpu, GC2000, 0x6202) ||
etnaviv_is_model_rev(gpu, GC2000, 0x6203))
etnaviv_is_model_rev(gpu, GC7000, 0x6202) ||
etnaviv_is_model_rev(gpu, GC7000, 0x6203))
pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
/* Disable SE and RA clock gating on affected core revisions. */

12
drivers/gpu/drm/etnaviv/etnaviv_gpu.h
View File

@ -54,18 +54,6 @@ struct etnaviv_chip_identity {
/* Number of Neural Network cores. */
u32 nn_core_count;
/* Number of MAD units per Neural Network core. */
u32 nn_mad_per_core;
/* Number of Tensor Processing cores. */
u32 tp_core_count;
/* Size in bytes of the SRAM inside the NPU. */
u32 on_chip_sram_size;
/* Size in bytes of the SRAM across the AXI bus. */
u32 axi_sram_size;
/* Size of the vertex cache. */
u32 vertex_cache_size;

34
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
View File

@ -17,10 +17,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 128,
.shader_core_count = 1,
.nn_core_count = 0,
.nn_mad_per_core = 0,
.tp_core_count = 0,
.on_chip_sram_size = 0,
.axi_sram_size = 0,
.vertex_cache_size = 8,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@ -52,11 +48,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.register_max = 64,
.thread_count = 256,
.shader_core_count = 1,
.nn_core_count = 0,
.nn_mad_per_core = 0,
.tp_core_count = 0,
.on_chip_sram_size = 0,
.axi_sram_size = 0,
.vertex_cache_size = 8,
.vertex_output_buffer_size = 512,
.pixel_pipes = 1,
@ -89,10 +80,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 512,
.shader_core_count = 2,
.nn_core_count = 0,
.nn_mad_per_core = 0,
.tp_core_count = 0,
.on_chip_sram_size = 0,
.axi_sram_size = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@ -125,10 +112,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 512,
.shader_core_count = 2,
.nn_core_count = 0,
.nn_mad_per_core = 0,
.tp_core_count = 0,
.on_chip_sram_size = 0,
.axi_sram_size = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@ -160,11 +143,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.register_max = 64,
.thread_count = 512,
.shader_core_count = 2,
.nn_core_count = 0,
.nn_mad_per_core = 0,
.tp_core_count = 0,
.on_chip_sram_size = 0,
.axi_sram_size = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@ -197,10 +175,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 1024,
.shader_core_count = 4,
.nn_core_count = 0,
.nn_mad_per_core = 0,
.tp_core_count = 0,
.on_chip_sram_size = 0,
.axi_sram_size = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 2,
@ -233,10 +207,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 256,
.shader_core_count = 1,
.nn_core_count = 8,
.nn_mad_per_core = 64,
.tp_core_count = 4,
.on_chip_sram_size = 524288,
.axi_sram_size = 1048576,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@ -269,10 +239,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 256,
.shader_core_count = 1,
.nn_core_count = 6,
.nn_mad_per_core = 64,
.tp_core_count = 3,
.on_chip_sram_size = 262144,
.axi_sram_size = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,

5
include/uapi/drm/etnaviv_drm.h
View File

@ -77,11 +77,6 @@ struct drm_etnaviv_timespec {
#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
#define ETNAVIV_PARAM_GPU_NN_CORE_COUNT 0x1f
#define ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE 0x20
#define ETNAVIV_PARAM_GPU_TP_CORE_COUNT 0x21
#define ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE 0x22
#define ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE 0x23
#define ETNA_MAX_PIPES 4