From ca87a3bf731d1b252f2e0a1be135846d02d0e6fc Mon Sep 17 00:00:00 2001
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Date: Fri, 15 Feb 2019 07:18:37 +0100
Subject: [PATCH] staging: mt7621-dts: fix pci phy register addresses
Both pci-phy0 and pci-phy1 are using bad addresses to search
for its registers. Use proper register values.
Fixes: 06184ba5a33a: staging: mt7621-dts: add pci-phy related bindings to board's device tree
Reported-by: NeilBrown <neil@brown.name>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/staging/mt7621-dts/mt7621.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index f0c51622eca1..851b035b906a 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -452,9 +452,9 @@
};
};
- pcie0_phy: pcie-phy@1a149000 {
+ pcie0_phy: pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
- reg = <0x1a149000 0x0700>;
+ reg = <0x1e149000 0x0700>;
#address-cells = <1>;
#size-cells = <0>;
@@ -469,9 +469,9 @@
};
};
- pcie1_phy: pcie-phy@1a14a000 {
+ pcie1_phy: pcie-phy@1e14a000 {
compatible = "mediatek,mt7621-pci-phy";
- reg = <0x1a14a000 0x0700>;
+ reg = <0x1e14a000 0x0700>;
#address-cells = <1>;
#size-cells = <0>;