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Allwinner arm64 DT changes for 4.17

Browse Source 
We've had for this release a pretty good progress on the arm64 front as
 well:
   - The A64 now has SPDIF support
   - The H6 is now supported (even though at an early stage)
   - The TERES-I laptop from Olimex has seen some early support as well
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Merge tag 'sunxi-dt64-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Pull "Allwinner arm64 DT changes for 4.17" from Maxime Ripard:

We've had for this release a pretty good progress on the arm64 front as
well:
  - The A64 now has SPDIF support
  - The H6 is now supported (even though at an early stage)
  - The TERES-I laptop from Olimex has seen some early support as well

* tag 'sunxi-dt64-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: a64: Add support for TERES-I laptop
  arm64: dts: allwinner: a64: add simplefb for A64 SoC
  arm64: dts: allwinner: a64: Add watchdog
  arm64: dts: allwinner: a64: Add i2c0 pins
  arm64: allwinner: h6: add support for Pine H64 board
  arm64: allwinner: h6: add the basical Allwinner H6 DTSI file
  arm64: dts: sunxi: Switch MMC nodes away from cd-inverted property
  arm64: dts: allwinner: a64: Add DAI nodes
  arm64: dts: allwinner: a64: Add SPDIF to the Pine64
  arm64: dts: allwinner: a64: Add SPDIF to the A64
  arm64: dts: allwinner: a64: Add the SPDIF block and pin
This commit is contained in:
Arnd Bergmann 2018-03-27 14:55:26 +02:00
commit cafc87023b
11 changed files with 584 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
View File

@ -2,8 +2,10 @@ Allwinner SoCs Watchdog timer
Required properties:
- compatible : should be either "allwinner,sun4i-a10-wdt" or
"allwinner,sun6i-a31-wdt"
- compatible : should be one of
"allwinner,sun4i-a10-wdt"
"allwinner,sun6i-a31-wdt"
"allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt"
- reg : Specifies base physical address and size of the registers.
Example:

2
arch/arm64/boot/dts/allwinner/Makefile
View File

@ -5,8 +5,10 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb

3
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
View File

@ -120,8 +120,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";

3
arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
View File

@ -82,8 +82,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";

3
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
View File

@ -68,8 +68,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";

3
arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
View File

@ -67,8 +67,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
status = "okay";
};

8
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
View File

@ -103,8 +103,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";
@ -230,6 +229,11 @@
regulator-name = "vcc-rtc";
};
/* On Euler connector */
&spdif {
status = "disabled";
};
/* On Exp and Euler connectors */
&uart0 {
pinctrl-names = "default";

265
arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts Normal file
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@ -0,0 +1,265 @@
/*
* Copyright (C) Harald Geyer <harald@ccbib.org>
* based on sun50i-a64-olinuxino.dts by Jagan Teki <jteki@openedev.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
/dts-v1/;
#include "sun50i-a64.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Olimex A64 Teres-I";
compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
framebuffer-lcd {
eDP25-supply = <&reg_dldo2>;
eDP12-supply = <&reg_dldo3>;
};
};
gpio-keys {
compatible = "gpio-keys";
lid-switch {
label = "Lid Switch";
gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
};
};
leds {
compatible = "gpio-leds";
capslock {
label = "teres-i:green:capslock";
gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
};
numlock {
label = "teres-i:green:numlock";
gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
};
};
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
status = "okay";
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};
};
&ehci1 {
status = "okay";
};
/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline)
* driver for this chip at the moment, the bootloader initializes it.
* However it can be accessed with the i2c-dev driver from user space.
*/
&i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_aldo2>;
vqmmc-supply = <&reg_dldo4>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
rtl8723bs: wifi@1 {
reg = <1>;
interrupt-parent = <&r_pio>;
interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
interrupt-names = "host-wake";
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&ohci1 {
status = "okay";
};
&r_rsb {
status = "okay";
axp803: pmic@3a3 {
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
#include "axp803.dtsi"
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc-pe";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-pl";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pll-avcc";
};
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1040000>;
regulator-max-microvolt = <1300000>;
regulator-name = "vdd-cpux";
};
/* DCDC3 is polyphased with DCDC2 */
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc-ddr3";
};
&reg_dcdc6 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-sys";
};
&reg_dldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-hdmi";
};
&reg_dldo2 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc-pd";
};
&reg_dldo3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "eDP12";
};
&reg_dldo4 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-io";
};
&reg_eldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "cpvdd";
};
&reg_eldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-dvdd-csi";
};
&reg_fldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-1v2-hsic";
};
/*
* The A64 chip cannot work without this regulator off, although
* it seems to be only driving the AR100 core.
* Maybe we don't still know well about CPUs domain.
*/
&reg_fldo2 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpus";
};
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

99
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -52,6 +52,26 @@
#address-cells = <1>;
#size-cells = <1>;
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
* However there is no support for this clock on A64 yet, so we depend
* on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
*/
simplefb_lcd: framebuffer-lcd {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "mixer0-lcd0";
clocks = <&ccu CLK_TCON0>,
<&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
status = "disabled";
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -112,6 +132,24 @@
method = "smc";
};
sound_spdif {
compatible = "simple-audio-card";
simple-audio-card,name = "On-board SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
spdif_out: spdif-out {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
@ -291,6 +329,11 @@
interrupt-controller;
#interrupt-cells = <3>;
i2c0_pins: i2c0_pins {
pins = "PH0", "PH1";
function = "i2c0";
};
i2c1_pins: i2c1_pins {
pins = "PH2", "PH3";
function = "i2c1";
@ -336,6 +379,11 @@
drive-strength = <40>;
};
spdif_tx_pin: spdif {
pins = "PH8";
function = "spdif";
};
spi0_pins: spi0 {
pins = "PC0", "PC1", "PC2", "PC3";
function = "spi0";
@ -382,6 +430,50 @@
};
};
spdif: spdif@1c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-spdif",
"allwinner,sun8i-h3-spdif";
reg = <0x01c21000 0x400>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
resets = <&ccu RST_BUS_SPDIF>;
clock-names = "apb", "spdif";
dmas = <&dma 2>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx_pin>;
status = "disabled";
};
i2s0: i2s@1c22000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-i2s",
"allwinner,sun8i-h3-i2s";
reg = <0x01c22000 0x400>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
clock-names = "apb", "mod";
resets = <&ccu RST_BUS_I2S0>;
dma-names = "rx", "tx";
dmas = <&dma 3>, <&dma 3>;
status = "disabled";
};
i2s1: i2s@1c22400 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-i2s",
"allwinner,sun8i-h3-i2s";
reg = <0x01c22400 0x400>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
clock-names = "apb", "mod";
resets = <&ccu RST_BUS_I2S1>;
dma-names = "rx", "tx";
dmas = <&dma 4>, <&dma 4>;
status = "disabled";
};
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
@ -593,5 +685,12 @@
#address-cells = <1>;
#size-cells = <0>;
};
wdt0: watchdog@1c20ca0 {
compatible = "allwinner,sun50i-a64-wdt",
"allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
};
};
};

29
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts Normal file
View File

@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
/dts-v1/;
#include "sun50i-h6.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Pine H64";
compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

175
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi Normal file
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@ -0,0 +1,175 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
};
};
iosc: internal-osc-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16000000>;
clock-accuracy = <300000000>;
clock-output-names = "iosc";
};
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ccu: clock@3001000 {
compatible = "allwinner,sun50i-h6-ccu";
reg = <0x03001000 0x1000>;
clocks = <&osc24M>, <&osc32k>, <&iosc>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
gic: interrupt-controller@3021000 {
compatible = "arm,gic-400";
reg = <0x03021000 0x1000>,
<0x03022000 0x2000>,
<0x03024000 0x2000>,
<0x03026000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-controller;
#interrupt-cells = <3>;
};
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-h6-pinctrl";
reg = <0x0300b000 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 26>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
uart0_ph_pins: uart0-ph {
pins = "PH0", "PH1";
function = "uart0";
};
};
uart0: serial@5000000 {
compatible = "snps,dw-apb-uart";
reg = <0x05000000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 70>;
resets = <&ccu 21>;
status = "disabled";
};
uart1: serial@5000400 {
compatible = "snps,dw-apb-uart";
reg = <0x05000400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 71>;
resets = <&ccu 22>;
status = "disabled";
};
uart2: serial@5000800 {
compatible = "snps,dw-apb-uart";
reg = <0x05000800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 72>;
resets = <&ccu 23>;
status = "disabled";
};
uart3: serial@5000c00 {
compatible = "snps,dw-apb-uart";
reg = <0x05000c00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 73>;
resets = <&ccu 24>;
status = "disabled";
};
};
};