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drm/amd/display: Rework power sequence and resource allocation logic

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Rework part of the modifications made to the power sequence and resource
allocation logic.

Reviewed-by: Xi (Alex) Liu <xi.liu@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sung Joon Kim 2024-04-04 13:00:02 -04:00 committed by Alex Deucher
parent e9e4b3a05b
commit cb5b29178e
3 changed files with 5 additions and 45 deletions
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8
drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
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@ -116,10 +116,10 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
.update_visual_confirm_color = dcn10_update_visual_confirm_color,
.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,
.update_dsc_pg = dcn32_update_dsc_pg,
.calc_blocks_to_gate = dcn351_calc_blocks_to_gate,
.calc_blocks_to_ungate = dcn351_calc_blocks_to_ungate,
.hw_block_power_up = dcn351_hw_block_power_up,
.hw_block_power_down = dcn351_hw_block_power_down,
.calc_blocks_to_gate = dcn35_calc_blocks_to_gate,
.calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,
.hw_block_power_up = dcn35_hw_block_power_up,
.hw_block_power_down = dcn35_hw_block_power_down,
.root_clock_control = dcn35_root_clock_control,
};

36
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
View File

@ -1728,38 +1728,6 @@ static bool dcn351_validate_bandwidth(struct dc *dc,
return out;
}
struct pipe_ctx *dcn351_acquire_free_pipe_as_secondary_dpp_pipe(
const struct dc_state *cur_ctx,
struct dc_state *new_ctx,
const struct resource_pool *pool,
const struct pipe_ctx *opp_head_pipe)
{
int free_pipe_idx;
struct pipe_ctx *free_pipe;
free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
&cur_ctx->res_ctx, &new_ctx->res_ctx,
pool, opp_head_pipe);
if (free_pipe_idx >= 0) {
free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
free_pipe->pipe_idx = free_pipe_idx;
free_pipe->stream = opp_head_pipe->stream;
free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];
free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
free_pipe->plane_res.mpcc_inst =
pool->dpps[free_pipe->pipe_idx]->inst;
} else {
ASSERT(opp_head_pipe);
free_pipe = NULL;
}
return free_pipe;
}
static struct resource_funcs dcn351_res_pool_funcs = {
.destroy = dcn351_destroy_resource_pool,
.link_enc_create = dcn35_link_encoder_create,
@ -1771,8 +1739,7 @@ static struct resource_funcs dcn351_res_pool_funcs = {
.calculate_wm_and_dlg = NULL,
.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
.populate_dml_pipes = dcn351_populate_dml_pipes_from_context_fpu,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn351_acquire_free_pipe_as_secondary_dpp_pipe,
.acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
.release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
@ -2162,7 +2129,6 @@ static bool dcn351_resource_construct(
dc->dml2_options.max_segments_per_hubp = 24;
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
dc->dml2_options.map_dc_pipes_with_callbacks = true;
if (dc->config.sdpif_request_limit_words_per_umc == 0)
dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/

6
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h
View File

@ -20,10 +20,4 @@ struct resource_pool *dcn351_create_resource_pool(
const struct dc_init_data *init_data,
struct dc *dc);
struct pipe_ctx *dcn351_acquire_free_pipe_as_secondary_dpp_pipe(
const struct dc_state *cur_ctx,
struct dc_state *new_ctx,
const struct resource_pool *pool,
const struct pipe_ctx *opp_head_pipe);
#endif /* _DCN351_RESOURCE_H_ */