arm64: dts: marvell: Add support for AP807/AP807-quad
Describe AP807 and AP807-quad support. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Gregory CLEMENT
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51
arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
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51
arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Marvell Armada AP807 Quad
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*
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* Copyright (C) 2019 Marvell Technology Group Ltd.
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*/
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#include "armada-ap807.dtsi"
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/ {
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model = "Marvell Armada AP807 Quad";
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compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0x000>;
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0x001>;
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 0>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0x100>;
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 1>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0x101>;
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 1>;
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};
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};
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};
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arch/arm64/boot/dts/marvell/armada-ap807.dtsi
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arch/arm64/boot/dts/marvell/armada-ap807.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Marvell Armada AP807
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*
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* Copyright (C) 2019 Marvell Technology Group Ltd.
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*/
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#define AP_NAME ap807
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#include "armada-ap80x.dtsi"
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/ {
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model = "Marvell Armada AP807";
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compatible = "marvell,armada-ap807";
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};
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&ap_syscon0 {
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ap_clk: clock {
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compatible = "marvell,ap807-clock";
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#clock-cells = <1>;
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};
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};
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&ap_syscon1 {
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cpu_clk: clock-cpu {
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compatible = "marvell,ap807-cpu-clock";
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clocks = <&ap_clk 0>, <&ap_clk 1>;
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#clock-cells = <1>;
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};
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};
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