[media] marvell-cam: Working s/g DMA
The core Marvell camera driver can now do scatter/gather DMA on controllers which support that functionality. Signed-off-by: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Jonathan Corbet
Mauro Carvalho Chehab
parent
60c0732244
commit
cbc4f3a277
@ -3,6 +3,8 @@ config VIDEO_CAFE_CCIC
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depends on PCI && I2C && VIDEO_V4L2
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select VIDEO_OV7670
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select VIDEOBUF2_VMALLOC
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select VIDEOBUF2_DMA_CONTIG
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select VIDEOBUF2_DMA_SG
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---help---
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This is a video4linux2 driver for the Marvell 88ALP01 integrated
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CMOS camera controller. This is the controller found on first-
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@ -15,6 +17,7 @@ config VIDEO_MMP_CAMERA
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select I2C_GPIO
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select VIDEOBUF2_VMALLOC
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select VIDEOBUF2_DMA_CONTIG
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select VIDEOBUF2_DMA_SG
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---help---
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This is a Video4Linux2 driver for the integrated camera
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controller found on Marvell Armada 610 application
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@ -26,6 +26,7 @@
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#include <media/ov7670.h>
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#include <media/videobuf2-vmalloc.h>
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#include <media/videobuf2-dma-contig.h>
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#include <media/videobuf2-dma-sg.h>
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#include "mcam-core.h"
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@ -106,6 +107,7 @@ MODULE_PARM_DESC(buffer_mode,
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#define CF_DMA_ACTIVE 3 /* A frame is incoming */
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#define CF_CONFIG_NEEDED 4 /* Must configure hardware */
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#define CF_SINGLE_BUFFER 5 /* Running with a single buffer */
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#define CF_SG_RESTART 6 /* SG restart needed */
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#define sensor_call(cam, o, f, args...) \
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v4l2_subdev_call(cam->sensor, o, f, ##args)
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@ -179,6 +181,17 @@ static void mcam_set_config_needed(struct mcam_camera *cam, int needed)
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clear_bit(CF_CONFIG_NEEDED, &cam->flags);
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}
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/*
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* The two-word DMA descriptor format used by the Armada 610 and like. There
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* Is a three-word format as well (set C1_DESC_3WORD) where the third
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* word is a pointer to the next descriptor, but we don't use it. Two-word
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* descriptors have to be contiguous in memory.
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*/
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struct mcam_dma_desc {
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u32 dma_addr;
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u32 segment_len;
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};
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/*
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* Our buffer type for working with videobuf2. Note that the vb2
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* developers have decreed that struct vb2_buffer must be at the
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@ -187,6 +200,9 @@ static void mcam_set_config_needed(struct mcam_camera *cam, int needed)
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struct mcam_vb_buffer {
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struct vb2_buffer vb_buf;
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struct list_head queue;
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struct mcam_dma_desc *dma_desc; /* Descriptor virtual address */
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dma_addr_t dma_desc_pa; /* Descriptor physical address */
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int dma_desc_nent; /* Number of mapped descriptors */
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};
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static inline struct mcam_vb_buffer *vb_to_mvb(struct vb2_buffer *vb)
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@ -268,6 +284,9 @@ static void mcam_set_contig_buffer(struct mcam_camera *cam, int frame)
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clear_bit(CF_SINGLE_BUFFER, &cam->flags);
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}
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/*
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* Initial B_DMA_contig setup.
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*/
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static void mcam_ctlr_dma_contig(struct mcam_camera *cam)
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{
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mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
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@ -277,14 +296,38 @@ static void mcam_ctlr_dma_contig(struct mcam_camera *cam)
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}
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static void mcam_ctlr_dma(struct mcam_camera *cam)
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/*
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* Set up the next buffer for S/G I/O; caller should be sure that
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* the controller is stopped and a buffer is available.
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*/
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static void mcam_sg_next_buffer(struct mcam_camera *cam)
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{
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if (cam->buffer_mode == B_DMA_contig)
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mcam_ctlr_dma_contig(cam);
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else
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mcam_ctlr_dma_vmalloc(cam);
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struct mcam_vb_buffer *buf;
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buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
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list_del_init(&buf->queue);
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mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa);
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mcam_reg_write(cam, REG_DESC_LEN_Y,
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buf->dma_desc_nent*sizeof(struct mcam_dma_desc));
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mcam_reg_write(cam, REG_DESC_LEN_U, 0);
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mcam_reg_write(cam, REG_DESC_LEN_V, 0);
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cam->vb_bufs[0] = buf;
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}
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/*
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* Initial B_DMA_sg setup
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*/
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static void mcam_ctlr_dma_sg(struct mcam_camera *cam)
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{
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mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_3WORD);
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mcam_sg_next_buffer(cam);
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mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA);
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cam->nbufs = 3;
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}
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/*
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* Image format setup, independent of DMA scheme.
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*/
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static void mcam_ctlr_image(struct mcam_camera *cam)
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{
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int imgsz;
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@ -341,9 +384,20 @@ static int mcam_ctlr_configure(struct mcam_camera *cam)
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unsigned long flags;
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spin_lock_irqsave(&cam->dev_lock, flags);
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mcam_ctlr_dma(cam);
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switch (cam->buffer_mode) {
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case B_vmalloc:
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mcam_ctlr_dma_vmalloc(cam);
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break;
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case B_DMA_contig:
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mcam_ctlr_dma_contig(cam);
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break;
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case B_DMA_sg:
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mcam_ctlr_dma_sg(cam);
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break;
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}
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mcam_ctlr_image(cam);
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mcam_set_config_needed(cam, 0);
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clear_bit(CF_SG_RESTART, &cam->flags);
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spin_unlock_irqrestore(&cam->dev_lock, flags);
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return 0;
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}
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@ -379,6 +433,19 @@ static void mcam_ctlr_stop(struct mcam_camera *cam)
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mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
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}
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/*
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* Scatter/gather mode requires stopping the controller between
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* frames so we can put in a new DMA descriptor array. If no new
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* buffer exists at frame completion, the controller is left stopped;
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* this function is charged with gettig things going again.
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*/
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static void mcam_sg_restart(struct mcam_camera *cam)
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{
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mcam_ctlr_dma_sg(cam);
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mcam_ctlr_start(cam);
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clear_bit(CF_SG_RESTART, &cam->flags);
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}
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static void mcam_ctlr_init(struct mcam_camera *cam)
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{
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unsigned long flags;
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@ -416,14 +483,15 @@ static void mcam_ctlr_stop_dma(struct mcam_camera *cam)
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* interrupt, then wait until no DMA is active.
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*/
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spin_lock_irqsave(&cam->dev_lock, flags);
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clear_bit(CF_SG_RESTART, &cam->flags);
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mcam_ctlr_stop(cam);
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cam->state = S_IDLE;
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spin_unlock_irqrestore(&cam->dev_lock, flags);
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msleep(10);
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msleep(40);
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if (test_bit(CF_DMA_ACTIVE, &cam->flags))
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cam_err(cam, "Timeout waiting for DMA to end\n");
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/* This would be bad news - what now? */
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spin_lock_irqsave(&cam->dev_lock, flags);
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cam->state = S_IDLE;
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mcam_ctlr_irq_disable(cam);
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spin_unlock_irqrestore(&cam->dev_lock, flags);
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}
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@ -540,9 +608,8 @@ static int mcam_cam_configure(struct mcam_camera *cam)
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* DMA buffer management. These functions need s_mutex held.
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*/
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/* FIXME: this is inefficient as hell, since dma_alloc_coherent just
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* does a get_free_pages() call, and we waste a good chunk of an orderN
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* allocation. Should try to allocate the whole set in one chunk.
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/*
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* Allocate in-kernel DMA buffers for vmalloc mode.
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*/
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static int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
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{
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@ -650,24 +717,56 @@ static int mcam_vb_queue_setup(struct vb2_queue *vq, unsigned int *nbufs,
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void *alloc_ctxs[])
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{
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struct mcam_camera *cam = vb2_get_drv_priv(vq);
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int minbufs = (cam->buffer_mode == B_DMA_contig) ? 3 : 2;
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sizes[0] = cam->pix_format.sizeimage;
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*num_planes = 1; /* Someday we have to support planar formats... */
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if (*nbufs < 3 || *nbufs > 32)
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*nbufs = 3; /* semi-arbitrary numbers */
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if (*nbufs < minbufs)
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*nbufs = minbufs;
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if (cam->buffer_mode == B_DMA_contig)
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alloc_ctxs[0] = cam->vb_alloc_ctx;
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return 0;
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}
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static int mcam_vb_buf_init(struct vb2_buffer *vb)
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/* DMA_sg only */
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static int mcam_vb_sg_buf_init(struct vb2_buffer *vb)
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{
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struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
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struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
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int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
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INIT_LIST_HEAD(&mvb->queue);
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mvb->dma_desc = dma_alloc_coherent(cam->dev,
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ndesc * sizeof(struct mcam_dma_desc),
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&mvb->dma_desc_pa, GFP_KERNEL);
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if (mvb->dma_desc == NULL) {
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cam_err(cam, "Unable to get DMA descriptor array\n");
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return -ENOMEM;
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}
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return 0;
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}
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static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb)
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{
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struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
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struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
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struct vb2_dma_sg_desc *sgd = vb2_dma_sg_plane_desc(vb, 0);
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struct mcam_dma_desc *desc = mvb->dma_desc;
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struct scatterlist *sg;
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int i;
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mvb->dma_desc_nent = dma_map_sg(cam->dev, sgd->sglist, sgd->num_pages,
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DMA_FROM_DEVICE);
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if (mvb->dma_desc_nent <= 0)
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return -EIO; /* Not sure what's right here */
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for_each_sg(sgd->sglist, sg, mvb->dma_desc_nent, i) {
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desc->dma_addr = sg_dma_address(sg);
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desc->segment_len = sg_dma_len(sg);
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desc++;
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}
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return 0;
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}
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static void mcam_vb_buf_queue(struct vb2_buffer *vb)
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{
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struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
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@ -678,11 +777,34 @@ static void mcam_vb_buf_queue(struct vb2_buffer *vb)
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spin_lock_irqsave(&cam->dev_lock, flags);
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start = (cam->state == S_BUFWAIT) && !list_empty(&cam->buffers);
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list_add(&mvb->queue, &cam->buffers);
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if (test_bit(CF_SG_RESTART, &cam->flags))
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mcam_sg_restart(cam);
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spin_unlock_irqrestore(&cam->dev_lock, flags);
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if (start)
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mcam_read_setup(cam);
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}
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static int mcam_vb_sg_buf_finish(struct vb2_buffer *vb)
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{
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struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
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struct vb2_dma_sg_desc *sgd = vb2_dma_sg_plane_desc(vb, 0);
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dma_unmap_sg(cam->dev, sgd->sglist, sgd->num_pages, DMA_FROM_DEVICE);
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return 0;
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}
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static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb)
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{
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struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
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struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
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int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
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dma_free_coherent(cam->dev, ndesc * sizeof(struct mcam_dma_desc),
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mvb->dma_desc, mvb->dma_desc_pa);
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}
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/*
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* vb2 uses these to release the mutex when waiting in dqbuf. I'm
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* not actually sure we need to do this (I'm not sure that vb2_dqbuf() needs
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@ -752,7 +874,6 @@ static int mcam_vb_stop_streaming(struct vb2_queue *vq)
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static const struct vb2_ops mcam_vb2_ops = {
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.queue_setup = mcam_vb_queue_setup,
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.buf_init = mcam_vb_buf_init,
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.buf_queue = mcam_vb_buf_queue,
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.start_streaming = mcam_vb_start_streaming,
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.stop_streaming = mcam_vb_stop_streaming,
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@ -760,22 +881,49 @@ static const struct vb2_ops mcam_vb2_ops = {
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.wait_finish = mcam_vb_wait_finish,
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};
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/*
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* Scatter/gather mode complicates things somewhat.
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*/
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static const struct vb2_ops mcam_vb2_sg_ops = {
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.queue_setup = mcam_vb_queue_setup,
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.buf_init = mcam_vb_sg_buf_init,
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.buf_prepare = mcam_vb_sg_buf_prepare,
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.buf_queue = mcam_vb_buf_queue,
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.buf_finish = mcam_vb_sg_buf_finish,
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.buf_cleanup = mcam_vb_sg_buf_cleanup,
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.start_streaming = mcam_vb_start_streaming,
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.stop_streaming = mcam_vb_stop_streaming,
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.wait_prepare = mcam_vb_wait_prepare,
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.wait_finish = mcam_vb_wait_finish,
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};
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static int mcam_setup_vb2(struct mcam_camera *cam)
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{
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struct vb2_queue *vq = &cam->vb_queue;
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memset(vq, 0, sizeof(*vq));
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vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
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vq->io_modes = VB2_MMAP; /* Add userptr */
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vq->drv_priv = cam;
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INIT_LIST_HEAD(&cam->buffers);
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switch (cam->buffer_mode) {
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case B_DMA_contig:
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vq->ops = &mcam_vb2_ops;
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if (cam->buffer_mode == B_DMA_contig) {
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vq->mem_ops = &vb2_dma_contig_memops;
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cam->vb_alloc_ctx = vb2_dma_contig_init_ctx(cam->dev);
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} else
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vq->io_modes = VB2_MMAP | VB2_USERPTR;
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break;
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case B_DMA_sg:
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vq->ops = &mcam_vb2_sg_ops;
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vq->mem_ops = &vb2_dma_sg_memops;
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vq->io_modes = VB2_MMAP | VB2_USERPTR;
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break;
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case B_vmalloc:
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vq->ops = &mcam_vb2_ops;
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vq->mem_ops = &vb2_vmalloc_memops;
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vq->buf_struct_size = sizeof(struct mcam_vb_buffer);
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vq->io_modes = VB2_MMAP;
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break;
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}
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return vb2_queue_init(vq);
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}
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@ -1313,8 +1461,6 @@ static void mcam_buffer_done(struct mcam_camera *cam, int frame,
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{
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vbuf->v4l2_buf.bytesused = cam->pix_format.sizeimage;
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vbuf->v4l2_buf.sequence = cam->buf_seq[frame];
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vbuf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_QUEUED;
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vbuf->v4l2_buf.flags |= V4L2_BUF_FLAG_DONE;
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vb2_set_plane_payload(vbuf, 0, cam->pix_format.sizeimage);
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vb2_buffer_done(vbuf, VB2_BUF_STATE_DONE);
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}
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@ -1363,7 +1509,7 @@ static void mcam_frame_tasklet(unsigned long data)
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/*
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* For direct DMA, mark the buffer ready and set up another one.
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*/
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static void mcam_dma_complete(struct mcam_camera *cam, int frame)
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static void mcam_dma_contig_done(struct mcam_camera *cam, int frame)
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{
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struct mcam_vb_buffer *buf = cam->vb_bufs[frame];
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@ -1374,6 +1520,52 @@ static void mcam_dma_complete(struct mcam_camera *cam, int frame)
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mcam_set_contig_buffer(cam, frame);
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}
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/*
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* Frame completion with S/G is trickier. We can't muck with
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* a descriptor chain on the fly, since the controller buffers it
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* internally. So we have to actually stop and restart; Marvell
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* says this is the way to do it.
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*
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* Of course, stopping is easier said than done; experience shows
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* that the controller can start a frame *after* C0_ENABLE has been
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* cleared. So when running in S/G mode, the controller is "stopped"
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* on receipt of the start-of-frame interrupt. That means we can
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* safely change the DMA descriptor array here and restart things
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* (assuming there's another buffer waiting to go).
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*/
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static void mcam_dma_sg_done(struct mcam_camera *cam, int frame)
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{
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struct mcam_vb_buffer *buf = cam->vb_bufs[0];
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/*
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* Very Bad Not Good Things happen if you don't clear
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* C1_DESC_ENA before making any descriptor changes.
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*/
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mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_ENA);
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/*
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* If we have another buffer available, put it in and
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* restart the engine.
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*/
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if (!list_empty(&cam->buffers)) {
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mcam_sg_next_buffer(cam);
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mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA);
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mcam_ctlr_start(cam);
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/*
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* Otherwise set CF_SG_RESTART and the controller will
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* be restarted once another buffer shows up.
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*/
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} else {
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set_bit(CF_SG_RESTART, &cam->flags);
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singles++;
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||||
}
|
||||
/*
|
||||
* Now we can give the completed frame back to user space.
|
||||
*/
|
||||
delivered++;
|
||||
mcam_buffer_done(cam, frame, &buf->vb_buf);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void mcam_frame_complete(struct mcam_camera *cam, int frame)
|
||||
{
|
||||
@ -1385,21 +1577,24 @@ static void mcam_frame_complete(struct mcam_camera *cam, int frame)
|
||||
cam->next_buf = frame;
|
||||
cam->buf_seq[frame] = ++(cam->sequence);
|
||||
cam->last_delivered = frame;
|
||||
|
||||
frames++;
|
||||
switch (cam->state) {
|
||||
/*
|
||||
* We're streaming and have a ready frame, hand it back
|
||||
* "This should never happen"
|
||||
*/
|
||||
case S_STREAMING:
|
||||
if (cam->buffer_mode == B_vmalloc)
|
||||
if (cam->state != S_STREAMING)
|
||||
return;
|
||||
/*
|
||||
* Process the frame and set up the next one.
|
||||
*/
|
||||
switch (cam->buffer_mode) {
|
||||
case B_vmalloc:
|
||||
tasklet_schedule(&cam->s_tasklet);
|
||||
else
|
||||
mcam_dma_complete(cam, frame);
|
||||
break;
|
||||
|
||||
default:
|
||||
cam_err(cam, "Frame interrupt in non-operational state\n");
|
||||
case B_DMA_contig:
|
||||
mcam_dma_contig_done(cam, frame);
|
||||
break;
|
||||
case B_DMA_sg:
|
||||
mcam_dma_sg_done(cam, frame);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -1416,6 +1611,11 @@ int mccic_irq(struct mcam_camera *cam, unsigned int irqs)
|
||||
* Handle any frame completions. There really should
|
||||
* not be more than one of these, or we have fallen
|
||||
* far behind.
|
||||
*
|
||||
* When running in S/G mode, the frame number lacks any
|
||||
* real meaning - there's only one descriptor array - but
|
||||
* the controller still picks a different one to signal
|
||||
* each time.
|
||||
*/
|
||||
for (frame = 0; frame < cam->nbufs; frame++)
|
||||
if (irqs & (IRQ_EOF0 << frame)) {
|
||||
@ -1430,6 +1630,8 @@ int mccic_irq(struct mcam_camera *cam, unsigned int irqs)
|
||||
if (irqs & (IRQ_SOF0 | IRQ_SOF1 | IRQ_SOF2)) {
|
||||
set_bit(CF_DMA_ACTIVE, &cam->flags);
|
||||
handled = 1;
|
||||
if (cam->buffer_mode == B_DMA_sg)
|
||||
mcam_ctlr_stop(cam);
|
||||
}
|
||||
return handled;
|
||||
}
|
||||
@ -1480,8 +1682,15 @@ int mccic_register(struct mcam_camera *cam)
|
||||
cam->buffer_mode = B_vmalloc;
|
||||
else if (buffer_mode == 1)
|
||||
cam->buffer_mode = B_DMA_contig;
|
||||
else if (buffer_mode != -1)
|
||||
printk(KERN_ERR "marvel-cam: "
|
||||
else if (buffer_mode == 2) {
|
||||
if (cam->chip_id == V4L2_IDENT_ARMADA610)
|
||||
cam->buffer_mode = B_DMA_sg;
|
||||
else {
|
||||
printk(KERN_ERR "marvell-cam: Cafe can't do S/G I/O\n");
|
||||
cam->buffer_mode = B_vmalloc;
|
||||
}
|
||||
} else if (buffer_mode != -1)
|
||||
printk(KERN_ERR "marvell-cam: "
|
||||
"Strange module buffer mode %d - ignoring\n",
|
||||
buffer_mode);
|
||||
mcam_ctlr_init(cam);
|
||||
|
||||
@ -38,7 +38,8 @@ enum mcam_state {
|
||||
*/
|
||||
enum mcam_buffer_mode {
|
||||
B_vmalloc = 0,
|
||||
B_DMA_contig
|
||||
B_DMA_contig,
|
||||
B_DMA_sg
|
||||
};
|
||||
|
||||
/*
|
||||
@ -250,8 +251,11 @@ int mccic_resume(struct mcam_camera *cam);
|
||||
#define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */
|
||||
#define CO_SOF_NOSYNC 0x40000000 /* Use inband active signaling */
|
||||
|
||||
|
||||
/* Bits below C1_444ALPHA are not present in Cafe */
|
||||
#define REG_CTRL1 0x40 /* Control 1 */
|
||||
#define C1_CLKGATE 0x00000001 /* Sensor clock gate */
|
||||
#define C1_DESC_ENA 0x00000100 /* DMA descriptor enable */
|
||||
#define C1_DESC_3WORD 0x00000200 /* Three-word descriptors used */
|
||||
#define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */
|
||||
#define C1_ALPHA_SHFT 20
|
||||
#define C1_DMAB32 0x00000000 /* 32-byte DMA burst */
|
||||
@ -267,6 +271,14 @@ int mccic_resume(struct mcam_camera *cam);
|
||||
/* This appears to be a Cafe-only register */
|
||||
#define REG_UBAR 0xc4 /* Upper base address register */
|
||||
|
||||
/* Armada 610 DMA descriptor registers */
|
||||
#define REG_DMA_DESC_Y 0x200
|
||||
#define REG_DMA_DESC_U 0x204
|
||||
#define REG_DMA_DESC_V 0x208
|
||||
#define REG_DESC_LEN_Y 0x20c /* Lengths are in bytes */
|
||||
#define REG_DESC_LEN_U 0x210
|
||||
#define REG_DESC_LEN_V 0x214
|
||||
|
||||
/*
|
||||
* Useful stuff that probably belongs somewhere global.
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user