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[ARM] pxa: make additional DCSR bits valid for PXA3xx

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Signed-off-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Eric Miao 2008-09-08 15:17:47 +08:00 committed by Russell King
parent 283afa0661
commit cbd18f8e3d
1 changed files with 7 additions and 6 deletions
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13
arch/arm/mach-pxa/include/mach/pxa-regs.h
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@ -92,7 +92,13 @@
#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
#ifdef CONFIG_PXA27x #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
@ -101,11 +107,6 @@
#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
#define DCSR_EORINTR (1 << 9) /* The end of Receive */ #define DCSR_EORINTR (1 << 9) /* The end of Receive */
#endif #endif
#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
#define DALGN __REG(0x400000a0) /* DMA Alignment Register */ #define DALGN __REG(0x400000a0) /* DMA Alignment Register */
#define DINT __REG(0x400000f0) /* DMA Interrupt Register */ #define DINT __REG(0x400000f0) /* DMA Interrupt Register */