x86/mce: Get rid of machine_check_vector
Get rid of the indirect function pointer and use flags settings instead to steer execution. Now that it is not an indirect call any longer, drop the instrumentation annotation for objtool too. No functional changes. Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lkml.kernel.org/r/20210922165101.18951-3-bp@alien8.de
This commit is contained in:
Borislav Petkov
parent
631adc7b0b
commit
cbe1de162d
@ -215,16 +215,6 @@ static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
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u64 lapic_id) { return -EINVAL; }
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#endif
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#ifdef CONFIG_X86_ANCIENT_MCE
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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void winchip_mcheck_init(struct cpuinfo_x86 *c);
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static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
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#else
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static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void enable_p5_mce(void) {}
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#endif
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void mce_setup(struct mce *m);
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void mce_log(struct mce *m);
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DECLARE_PER_CPU(struct device *, mce_device);
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@ -1328,6 +1328,15 @@ static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callba
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task_work_add(current, ¤t->mce_kill_me, TWA_RESUME);
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}
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/* Handle unconfigured int18 (should never happen) */
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static noinstr void unexpected_machine_check(struct pt_regs *regs)
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{
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instrumentation_begin();
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pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
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smp_processor_id());
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instrumentation_end();
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}
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/*
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* The actual machine check handler. This only handles real
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* exceptions when something got corrupted coming in through int 18.
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@ -1348,36 +1357,43 @@ static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callba
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*/
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noinstr void do_machine_check(struct pt_regs *regs)
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{
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int worst = 0, order, no_way_out, kill_current_task, lmce;
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DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
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DECLARE_BITMAP(toclear, MAX_NR_BANKS);
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struct mca_config *cfg = &mca_cfg;
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struct mce m, *final;
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char *msg = NULL;
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int worst = 0;
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if (unlikely(mce_flags.p5))
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return pentium_machine_check(regs);
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else if (unlikely(mce_flags.winchip))
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return winchip_machine_check(regs);
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else if (unlikely(!mca_cfg.initialized))
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return unexpected_machine_check(regs);
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/*
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* Establish sequential order between the CPUs entering the machine
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* check handler.
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*/
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int order = -1;
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order = -1;
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/*
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* If no_way_out gets set, there is no safe way to recover from this
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* MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
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*/
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int no_way_out = 0;
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no_way_out = 0;
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/*
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* If kill_current_task is not set, there might be a way to recover from this
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* error.
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*/
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int kill_current_task = 0;
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kill_current_task = 0;
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/*
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* MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
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* on Intel.
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*/
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int lmce = 1;
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lmce = 1;
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this_cpu_inc(mce_exception_count);
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@ -1855,9 +1871,11 @@ static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
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switch (c->x86_vendor) {
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case X86_VENDOR_INTEL:
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intel_p5_mcheck_init(c);
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mce_flags.p5 = 1;
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return 1;
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case X86_VENDOR_CENTAUR:
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winchip_mcheck_init(c);
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mce_flags.winchip = 1;
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return 1;
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default:
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return 0;
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@ -2012,18 +2030,6 @@ bool filter_mce(struct mce *m)
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return false;
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}
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/* Handle unconfigured int18 (should never happen) */
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static noinstr void unexpected_machine_check(struct pt_regs *regs)
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{
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instrumentation_begin();
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pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
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smp_processor_id());
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instrumentation_end();
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}
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/* Call the installed machine check handler for this CPU setup. */
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void (*machine_check_vector)(struct pt_regs *) = unexpected_machine_check;
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static __always_inline void exc_machine_check_kernel(struct pt_regs *regs)
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{
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irqentry_state_t irq_state;
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@ -2034,31 +2040,22 @@ static __always_inline void exc_machine_check_kernel(struct pt_regs *regs)
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* Only required when from kernel mode. See
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* mce_check_crashing_cpu() for details.
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*/
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if (machine_check_vector == do_machine_check &&
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mce_check_crashing_cpu())
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if (mca_cfg.initialized && mce_check_crashing_cpu())
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return;
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irq_state = irqentry_nmi_enter(regs);
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/*
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* The call targets are marked noinstr, but objtool can't figure
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* that out because it's an indirect call. Annotate it.
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*/
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instrumentation_begin();
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machine_check_vector(regs);
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do_machine_check(regs);
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instrumentation_end();
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irqentry_nmi_exit(regs, irq_state);
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}
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static __always_inline void exc_machine_check_user(struct pt_regs *regs)
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{
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irqentry_enter_from_user_mode(regs);
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instrumentation_begin();
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machine_check_vector(regs);
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do_machine_check(regs);
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instrumentation_end();
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irqentry_exit_to_user_mode(regs);
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}
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@ -2125,7 +2122,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
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return;
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}
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machine_check_vector = do_machine_check;
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mca_cfg.initialized = 1;
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__mcheck_cpu_init_early(c);
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__mcheck_cpu_init_generic();
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@ -8,9 +8,6 @@
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#include <linux/device.h>
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#include <asm/mce.h>
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/* Pointer to the installed machine check handler for this CPU setup. */
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extern void (*machine_check_vector)(struct pt_regs *);
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enum severity_level {
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MCE_NO_SEVERITY,
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MCE_DEFERRED_SEVERITY,
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@ -126,7 +123,9 @@ struct mca_config {
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ser : 1,
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recovery : 1,
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bios_cmci_threshold : 1,
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__reserved : 59;
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/* Proper #MC exception handler is set */
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initialized : 1,
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__reserved : 58;
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s8 bootlog;
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int tolerant;
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@ -162,7 +161,13 @@ struct mce_vendor_flags {
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/* AMD-style error thresholding banks present. */
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amd_threshold : 1,
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__reserved_0 : 60;
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/* Pentium, family 5-style MCA */
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p5 : 1,
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/* Centaur Winchip C6-style MCA */
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winchip : 1,
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__reserved_0 : 58;
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};
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extern struct mce_vendor_flags mce_flags;
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@ -195,4 +200,18 @@ __visible bool ex_handler_wrmsr_fault(const struct exception_table_entry *fixup,
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unsigned long error_code,
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unsigned long fault_addr);
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#ifdef CONFIG_X86_ANCIENT_MCE
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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void winchip_mcheck_init(struct cpuinfo_x86 *c);
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noinstr void pentium_machine_check(struct pt_regs *regs);
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noinstr void winchip_machine_check(struct pt_regs *regs);
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static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
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#else
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static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void enable_p5_mce(void) {}
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static inline void pentium_machine_check(struct pt_regs *regs) {}
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static inline void winchip_machine_check(struct pt_regs *regs) {}
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#endif
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#endif /* __X86_MCE_INTERNAL_H__ */
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@ -21,7 +21,7 @@
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int mce_p5_enabled __read_mostly;
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/* Machine check handler for Pentium class Intel CPUs: */
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static noinstr void pentium_machine_check(struct pt_regs *regs)
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noinstr void pentium_machine_check(struct pt_regs *regs)
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{
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u32 loaddr, hi, lotype;
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@ -54,10 +54,6 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
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if (!cpu_has(c, X86_FEATURE_MCE))
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return;
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machine_check_vector = pentium_machine_check;
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/* Make sure the vector pointer is visible before we enable MCEs: */
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wmb();
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/* Read registers before enabling: */
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rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
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rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
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@ -17,7 +17,7 @@
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#include "internal.h"
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/* Machine check handler for WinChip C6: */
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static noinstr void winchip_machine_check(struct pt_regs *regs)
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noinstr void winchip_machine_check(struct pt_regs *regs)
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{
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instrumentation_begin();
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pr_emerg("CPU0: Machine Check Exception.\n");
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@ -30,10 +30,6 @@ void winchip_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 lo, hi;
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machine_check_vector = winchip_machine_check;
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/* Make sure the vector pointer is visible before we enable MCEs: */
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wmb();
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rdmsr(MSR_IDT_FCR1, lo, hi);
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lo |= (1<<2); /* Enable EIERRINT (int 18 MCE) */
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lo &= ~(1<<4); /* Enable MCE */
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