[ARM] versatile: remove IRQ mask definitions
These definitions are unused and serve no purpose with genirq. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King
Russell King
parent
7ef4de17cc
commit
ccaec3ec78
@ -60,39 +60,6 @@
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#define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31)
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#define IRQ_VIC_END (IRQ_VIC_START + 31)
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#define IRQMASK_WDOGINT INTMASK_WDOGINT
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#define IRQMASK_SOFTINT INTMASK_SOFTINT
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#define IRQMASK_COMMRx INTMASK_COMMRx
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#define IRQMASK_COMMTx INTMASK_COMMTx
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#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
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#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
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#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
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#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
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#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
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#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
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#define IRQMASK_RTCINT INTMASK_RTCINT
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#define IRQMASK_SSPINT INTMASK_SSPINT
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#define IRQMASK_UARTINT0 INTMASK_UARTINT0
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#define IRQMASK_UARTINT1 INTMASK_UARTINT1
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#define IRQMASK_UARTINT2 INTMASK_UARTINT2
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#define IRQMASK_SCIINT INTMASK_SCIINT
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#define IRQMASK_CLCDINT INTMASK_CLCDINT
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#define IRQMASK_DMAINT INTMASK_DMAINT
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#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
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#define IRQMASK_MBXINT INTMASK_MBXINT
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#define IRQMASK_GNDINT INTMASK_GNDINT
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#define IRQMASK_VICSOURCE21 INTMASK_VICSOURCE21
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#define IRQMASK_VICSOURCE22 INTMASK_VICSOURCE22
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#define IRQMASK_VICSOURCE23 INTMASK_VICSOURCE23
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#define IRQMASK_VICSOURCE24 INTMASK_VICSOURCE24
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#define IRQMASK_VICSOURCE25 INTMASK_VICSOURCE25
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#define IRQMASK_VICSOURCE26 INTMASK_VICSOURCE26
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#define IRQMASK_VICSOURCE27 INTMASK_VICSOURCE27
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#define IRQMASK_VICSOURCE28 INTMASK_VICSOURCE28
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#define IRQMASK_VICSOURCE29 INTMASK_VICSOURCE29
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#define IRQMASK_VICSOURCE30 INTMASK_VICSOURCE30
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#define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31
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/*
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* FIQ interrupts definitions are the same as the INT definitions.
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*/
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@ -130,39 +97,6 @@
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#define FIQ_VICSOURCE31 INT_VICSOURCE31
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#define FIQMASK_WDOGINT INTMASK_WDOGINT
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#define FIQMASK_SOFTINT INTMASK_SOFTINT
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#define FIQMASK_COMMRx INTMASK_COMMRx
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#define FIQMASK_COMMTx INTMASK_COMMTx
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#define FIQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
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#define FIQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
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#define FIQMASK_GPIOINT0 INTMASK_GPIOINT0
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#define FIQMASK_GPIOINT1 INTMASK_GPIOINT1
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#define FIQMASK_GPIOINT2 INTMASK_GPIOINT2
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#define FIQMASK_GPIOINT3 INTMASK_GPIOINT3
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#define FIQMASK_RTCINT INTMASK_RTCINT
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#define FIQMASK_SSPINT INTMASK_SSPINT
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#define FIQMASK_UARTINT0 INTMASK_UARTINT0
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#define FIQMASK_UARTINT1 INTMASK_UARTINT1
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#define FIQMASK_UARTINT2 INTMASK_UARTINT2
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#define FIQMASK_SCIINT INTMASK_SCIINT
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#define FIQMASK_CLCDINT INTMASK_CLCDINT
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#define FIQMASK_DMAINT INTMASK_DMAINT
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#define FIQMASK_PWRFAILINT INTMASK_PWRFAILINT
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#define FIQMASK_MBXINT INTMASK_MBXINT
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#define FIQMASK_GNDINT INTMASK_GNDINT
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#define FIQMASK_VICSOURCE21 INTMASK_VICSOURCE21
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#define FIQMASK_VICSOURCE22 INTMASK_VICSOURCE22
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#define FIQMASK_VICSOURCE23 INTMASK_VICSOURCE23
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#define FIQMASK_VICSOURCE24 INTMASK_VICSOURCE24
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#define FIQMASK_VICSOURCE25 INTMASK_VICSOURCE25
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#define FIQMASK_VICSOURCE26 INTMASK_VICSOURCE26
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#define FIQMASK_VICSOURCE27 INTMASK_VICSOURCE27
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#define FIQMASK_VICSOURCE28 INTMASK_VICSOURCE28
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#define FIQMASK_VICSOURCE29 INTMASK_VICSOURCE29
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#define FIQMASK_VICSOURCE30 INTMASK_VICSOURCE30
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#define FIQMASK_VICSOURCE31 INTMASK_VICSOURCE31
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/*
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* Secondary interrupt controller
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*/
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@ -188,24 +122,4 @@
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#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3)
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#define IRQ_SIC_END 63
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#define SIC_IRQMASK_MMCI0B SIC_INTMASK_MMCI0B
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#define SIC_IRQMASK_MMCI1B SIC_INTMASK_MMCI1B
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#define SIC_IRQMASK_KMI0 SIC_INTMASK_KMI0
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#define SIC_IRQMASK_KMI1 SIC_INTMASK_KMI1
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#define SIC_IRQMASK_SCI3 SIC_INTMASK_SCI3
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#define SIC_IRQMASK_UART3 SIC_INTMASK_UART3
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#define SIC_IRQMASK_CLCD SIC_INTMASK_CLCD
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#define SIC_IRQMASK_TOUCH SIC_INTMASK_TOUCH
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#define SIC_IRQMASK_KEYPAD SIC_INTMASK_KEYPAD
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#define SIC_IRQMASK_DoC SIC_INTMASK_DoC
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#define SIC_IRQMASK_MMCI0A SIC_INTMASK_MMCI0A
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#define SIC_IRQMASK_MMCI1A SIC_INTMASK_MMCI1A
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#define SIC_IRQMASK_AACI SIC_INTMASK_AACI
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#define SIC_IRQMASK_ETH SIC_INTMASK_ETH
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#define SIC_IRQMASK_USB SIC_INTMASK_USB
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#define SIC_IRQMASK_PCI0 SIC_INTMASK_PCI0
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#define SIC_IRQMASK_PCI1 SIC_INTMASK_PCI1
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#define SIC_IRQMASK_PCI2 SIC_INTMASK_PCI2
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#define SIC_IRQMASK_PCI3 SIC_INTMASK_PCI3
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#define NR_IRQS 64
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@ -347,44 +347,6 @@
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#define INT_VICSOURCE30 30 /* PCI 3 */
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#define INT_VICSOURCE31 31 /* SIC source */
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/*
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* Interrupt bit positions
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*
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*/
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#define INTMASK_WDOGINT (1 << INT_WDOGINT)
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#define INTMASK_SOFTINT (1 << INT_SOFTINT)
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#define INTMASK_COMMRx (1 << INT_COMMRx)
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#define INTMASK_COMMTx (1 << INT_COMMTx)
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#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
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#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
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#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
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#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
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#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
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#define INTMASK_GPIOINT3 (1 << INT_GPIOINT3)
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#define INTMASK_RTCINT (1 << INT_RTCINT)
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#define INTMASK_SSPINT (1 << INT_SSPINT)
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#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
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#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
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#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
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#define INTMASK_SCIINT (1 << INT_SCIINT)
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#define INTMASK_CLCDINT (1 << INT_CLCDINT)
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#define INTMASK_DMAINT (1 << INT_DMAINT)
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#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
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#define INTMASK_MBXINT (1 << INT_MBXINT)
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#define INTMASK_GNDINT (1 << INT_GNDINT)
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#define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21)
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#define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22)
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#define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23)
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#define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24)
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#define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25)
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#define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26)
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#define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27)
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#define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28)
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#define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29)
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#define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30)
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#define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31)
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#define VERSATILE_SC_VALID_INT 0x003FFFFF
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#define MAXIRQNUM 31
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@ -417,26 +379,6 @@
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#define SIC_INT_PCI3 30
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#define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B)
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#define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B)
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#define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0)
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#define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1)
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#define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3)
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#define SIC_INTMASK_UART3 (1 << SIC_INT_UART3)
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#define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD)
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#define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH)
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#define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD)
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#define SIC_INTMASK_DoC (1 << SIC_INT_DoC)
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#define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A)
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#define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A)
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#define SIC_INTMASK_AACI (1 << SIC_INT_AACI)
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#define SIC_INTMASK_ETH (1 << SIC_INT_ETH)
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#define SIC_INTMASK_USB (1 << SIC_INT_USB)
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#define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0)
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#define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1)
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#define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2)
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#define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3)
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/*
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* Clean base - dummy
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*
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