drm/bridge: anx7625: add HDCP support
This patch provides HDCP setting interface for userspace to dynamic enable/disable HDCP function. Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Robert Foss <robert.foss@linaro.org> Signed-off-by: Xin Ji <xji@analogixsemi.com> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220106100127.1862702-2-xji@analogixsemi.com
This commit is contained in:
Xin Ji
Robert Foss
parent
191be00229
commit
cd1637c7e4
@ -26,6 +26,7 @@
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_hdcp.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_of.h>
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#include <drm/drm_panel.h>
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@ -213,6 +214,65 @@ static int wait_aux_op_finish(struct anx7625_data *ctx)
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return 0;
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}
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static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
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u32 address, u8 len, u8 *buf)
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{
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struct device *dev = &ctx->client->dev;
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int ret;
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u8 addrh, addrm, addrl;
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u8 cmd;
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if (len > MAX_DPCD_BUFFER_SIZE) {
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dev_err(dev, "exceed aux buffer len.\n");
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return -EINVAL;
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}
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addrl = address & 0xFF;
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addrm = (address >> 8) & 0xFF;
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addrh = (address >> 16) & 0xFF;
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cmd = DPCD_CMD(len, DPCD_READ);
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cmd = ((len - 1) << 4) | 0x09;
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/* Set command and length */
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ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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AP_AUX_COMMAND, cmd);
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/* Set aux access address */
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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AP_AUX_ADDR_7_0, addrl);
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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AP_AUX_ADDR_15_8, addrm);
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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AP_AUX_ADDR_19_16, addrh);
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/* Enable aux access */
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ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
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AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
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if (ret < 0) {
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dev_err(dev, "cannot access aux related register.\n");
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return -EIO;
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}
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usleep_range(2000, 2100);
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ret = wait_aux_op_finish(ctx);
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if (ret) {
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dev_err(dev, "aux IO error: wait aux op finish.\n");
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return ret;
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}
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ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
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AP_AUX_BUFF_START, len, buf);
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if (ret < 0) {
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dev_err(dev, "read dpcd register failed\n");
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return -EIO;
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}
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return 0;
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}
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static int anx7625_video_mute_control(struct anx7625_data *ctx,
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u8 status)
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{
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@ -669,6 +729,165 @@ static int anx7625_dpi_config(struct anx7625_data *ctx)
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return ret;
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}
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static int anx7625_read_flash_status(struct anx7625_data *ctx)
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{
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return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL);
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}
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static int anx7625_hdcp_key_probe(struct anx7625_data *ctx)
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{
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int ret, val;
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struct device *dev = &ctx->client->dev;
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u8 ident[FLASH_BUF_LEN];
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ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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FLASH_ADDR_HIGH, 0x91);
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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FLASH_ADDR_LOW, 0xA0);
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if (ret < 0) {
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dev_err(dev, "IO error : set key flash address.\n");
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return ret;
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}
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ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8);
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF);
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if (ret < 0) {
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dev_err(dev, "IO error : set key flash len.\n");
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return ret;
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}
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ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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R_FLASH_RW_CTRL, FLASH_READ);
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ret |= readx_poll_timeout(anx7625_read_flash_status,
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ctx, val,
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((val & FLASH_DONE) || (val < 0)),
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2000,
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2000 * 150);
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if (ret) {
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dev_err(dev, "flash read access fail!\n");
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return -EIO;
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}
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ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
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FLASH_BUF_BASE_ADDR,
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FLASH_BUF_LEN, ident);
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if (ret < 0) {
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dev_err(dev, "read flash data fail!\n");
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return -EIO;
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}
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if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF)
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return -EINVAL;
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return 0;
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}
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static int anx7625_hdcp_key_load(struct anx7625_data *ctx)
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{
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int ret;
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struct device *dev = &ctx->client->dev;
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/* Select HDCP 1.4 KEY */
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ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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R_BOOT_RETRY, 0x12);
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8);
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF);
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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R_RAM_LEN_H, HDCP14KEY_SIZE >> 12);
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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R_RAM_LEN_L, HDCP14KEY_SIZE >> 4);
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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R_RAM_ADDR_H, 0);
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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R_RAM_ADDR_L, 0);
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/* Enable HDCP 1.4 KEY load */
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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R_RAM_CTRL, DECRYPT_EN | LOAD_START);
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dev_dbg(dev, "load HDCP 1.4 key done\n");
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return ret;
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}
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static int anx7625_hdcp_disable(struct anx7625_data *ctx)
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{
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int ret;
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struct device *dev = &ctx->client->dev;
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dev_dbg(dev, "disable HDCP 1.4\n");
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/* Disable HDCP */
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ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
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/* Try auth flag */
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ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
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/* Interrupt for DRM */
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ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
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if (ret < 0)
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dev_err(dev, "fail to disable HDCP\n");
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return anx7625_write_and(ctx, ctx->i2c.tx_p0_client,
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TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF);
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}
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static int anx7625_hdcp_enable(struct anx7625_data *ctx)
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{
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u8 bcap;
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int ret;
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struct device *dev = &ctx->client->dev;
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ret = anx7625_hdcp_key_probe(ctx);
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if (ret) {
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dev_dbg(dev, "no key found, not to do hdcp\n");
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return ret;
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}
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/* Read downstream capability */
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anx7625_aux_dpcd_read(ctx, 0x68028, 1, &bcap);
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if (!(bcap & 0x01)) {
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pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap);
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return 0;
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}
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dev_dbg(dev, "enable HDCP 1.4\n");
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/* First clear HDCP state */
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ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
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TX_HDCP_CTRL0,
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KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
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usleep_range(1000, 1100);
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/* Second clear HDCP state */
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ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
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TX_HDCP_CTRL0,
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KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
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/* Set time for waiting KSVR */
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ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
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SP_TX_WAIT_KSVR_TIME, 0xc8);
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/* Set time for waiting R0 */
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ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
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SP_TX_WAIT_R0_TIME, 0xb0);
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ret |= anx7625_hdcp_key_load(ctx);
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if (ret) {
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pr_warn("prepare HDCP key failed.\n");
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return ret;
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}
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ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20);
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/* Try auth flag */
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ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
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/* Interrupt for DRM */
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ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
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if (ret < 0)
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dev_err(dev, "fail to enable HDCP\n");
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return anx7625_write_or(ctx, ctx->i2c.tx_p0_client,
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TX_HDCP_CTRL0, HARD_AUTH_EN);
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}
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static void anx7625_dp_start(struct anx7625_data *ctx)
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{
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int ret;
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@ -679,6 +898,9 @@ static void anx7625_dp_start(struct anx7625_data *ctx)
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return;
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}
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/* Disable HDCP */
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anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
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if (ctx->pdata.is_dpi)
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ret = anx7625_dpi_config(ctx);
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else
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@ -686,6 +908,10 @@ static void anx7625_dp_start(struct anx7625_data *ctx)
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if (ret < 0)
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DRM_DEV_ERROR(dev, "MIPI phy setup error.\n");
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ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
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ctx->dp_en = 1;
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}
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static void anx7625_dp_stop(struct anx7625_data *ctx)
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@ -705,6 +931,10 @@ static void anx7625_dp_stop(struct anx7625_data *ctx)
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ret |= anx7625_video_mute_control(ctx, 1);
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if (ret < 0)
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DRM_DEV_ERROR(dev, "IO error : mute video fail\n");
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ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
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ctx->dp_en = 0;
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}
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static int sp_tx_rst_aux(struct anx7625_data *ctx)
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@ -1697,6 +1927,83 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
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return 0;
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}
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static void hdcp_check_work_func(struct work_struct *work)
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{
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u8 status;
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struct delayed_work *dwork;
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struct anx7625_data *ctx;
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struct device *dev;
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struct drm_device *drm_dev;
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dwork = to_delayed_work(work);
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ctx = container_of(dwork, struct anx7625_data, hdcp_work);
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dev = &ctx->client->dev;
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if (!ctx->connector) {
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dev_err(dev, "HDCP connector is null!");
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return;
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}
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drm_dev = ctx->connector->dev;
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drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
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mutex_lock(&ctx->hdcp_wq_lock);
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status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0);
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dev_dbg(dev, "sink HDCP status check: %.02x\n", status);
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if (status & BIT(1)) {
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ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED;
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drm_hdcp_update_content_protection(ctx->connector,
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ctx->hdcp_cp);
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dev_dbg(dev, "update CP to ENABLE\n");
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}
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mutex_unlock(&ctx->hdcp_wq_lock);
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drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
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}
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static int anx7625_connector_atomic_check(struct anx7625_data *ctx,
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struct drm_connector_state *state)
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{
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struct device *dev = &ctx->client->dev;
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int cp;
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dev_dbg(dev, "hdcp state check\n");
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cp = state->content_protection;
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if (cp == ctx->hdcp_cp)
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return 0;
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if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
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if (ctx->dp_en) {
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dev_dbg(dev, "enable HDCP\n");
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anx7625_hdcp_enable(ctx);
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queue_delayed_work(ctx->hdcp_workqueue,
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&ctx->hdcp_work,
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msecs_to_jiffies(2000));
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}
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}
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if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
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if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
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dev_err(dev, "current CP is not ENABLED\n");
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return -EINVAL;
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}
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anx7625_hdcp_disable(ctx);
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ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
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drm_hdcp_update_content_protection(ctx->connector,
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ctx->hdcp_cp);
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dev_dbg(dev, "update CP to UNDESIRE\n");
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}
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if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
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dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n");
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return -EINVAL;
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}
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return 0;
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}
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static int anx7625_bridge_attach(struct drm_bridge *bridge,
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enum drm_bridge_attach_flags flags)
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{
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@ -1920,8 +2227,11 @@ static int anx7625_bridge_atomic_check(struct drm_bridge *bridge,
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struct device *dev = &ctx->client->dev;
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dev_dbg(dev, "drm bridge atomic check\n");
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return anx7625_bridge_mode_fixup(bridge, &crtc_state->mode,
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&crtc_state->adjusted_mode);
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anx7625_bridge_mode_fixup(bridge, &crtc_state->mode,
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&crtc_state->adjusted_mode);
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return anx7625_connector_atomic_check(ctx, conn_state);
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}
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static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge,
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@ -2189,6 +2499,15 @@ static int anx7625_i2c_probe(struct i2c_client *client,
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anx7625_init_gpio(platform);
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mutex_init(&platform->lock);
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mutex_init(&platform->hdcp_wq_lock);
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INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func);
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platform->hdcp_workqueue = create_workqueue("hdcp workqueue");
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if (!platform->hdcp_workqueue) {
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dev_err(dev, "fail to create work queue\n");
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ret = -ENOMEM;
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goto free_platform;
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}
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platform->pdata.intp_irq = client->irq;
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if (platform->pdata.intp_irq) {
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@ -2198,7 +2517,7 @@ static int anx7625_i2c_probe(struct i2c_client *client,
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if (!platform->workqueue) {
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DRM_DEV_ERROR(dev, "fail to create work queue\n");
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ret = -ENOMEM;
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goto free_platform;
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goto free_hdcp_wq;
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}
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ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq,
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@ -2268,6 +2587,10 @@ free_wq:
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if (platform->workqueue)
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destroy_workqueue(platform->workqueue);
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free_hdcp_wq:
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if (platform->hdcp_workqueue)
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destroy_workqueue(platform->hdcp_workqueue);
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free_platform:
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kfree(platform);
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@ -2283,6 +2606,12 @@ static int anx7625_i2c_remove(struct i2c_client *client)
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if (platform->pdata.intp_irq)
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destroy_workqueue(platform->workqueue);
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if (platform->hdcp_workqueue) {
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cancel_delayed_work(&platform->hdcp_work);
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flush_workqueue(platform->workqueue);
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destroy_workqueue(platform->workqueue);
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}
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if (!platform->pdata.low_power_mode)
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pm_runtime_put_sync_suspend(&client->dev);
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@ -59,10 +59,23 @@
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/***************************************************************/
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/* Register definition of device address 0x70 */
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#define I2C_ADDR_70_DPTX 0x70
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#define TX_HDCP_CTRL0 0x01
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#define STORE_AN BIT(7)
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#define RX_REPEATER BIT(6)
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||||
#define RE_AUTHEN BIT(5)
|
||||
#define SW_AUTH_OK BIT(4)
|
||||
#define HARD_AUTH_EN BIT(3)
|
||||
#define ENC_EN BIT(2)
|
||||
#define BKSV_SRM_PASS BIT(1)
|
||||
#define KSVLIST_VLD BIT(0)
|
||||
|
||||
#define SP_TX_LINK_BW_SET_REG 0xA0
|
||||
#define SP_TX_LANE_COUNT_SET_REG 0xA1
|
||||
#define SP_TX_WAIT_R0_TIME 0x40
|
||||
#define SP_TX_WAIT_KSVR_TIME 0x42
|
||||
#define SP_TX_SYS_CTRL1_REG 0x80
|
||||
#define HDCP2TX_FW_EN BIT(4)
|
||||
|
||||
#define SP_TX_LINK_BW_SET_REG 0xA0
|
||||
#define SP_TX_LANE_COUNT_SET_REG 0xA1
|
||||
|
||||
#define M_VID_0 0xC0
|
||||
#define M_VID_1 0xC1
|
||||
@ -71,6 +84,12 @@
|
||||
#define N_VID_1 0xC4
|
||||
#define N_VID_2 0xC5
|
||||
|
||||
#define KEY_START_ADDR 0x9000
|
||||
#define KEY_RESERVED 416
|
||||
|
||||
#define HDCP14KEY_START_ADDR (KEY_START_ADDR + KEY_RESERVED)
|
||||
#define HDCP14KEY_SIZE 624
|
||||
|
||||
/***************************************************************/
|
||||
/* Register definition of device address 0x72 */
|
||||
#define AUX_RST 0x04
|
||||
@ -155,9 +174,43 @@
|
||||
|
||||
#define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E
|
||||
|
||||
#define R_BOOT_RETRY 0x00
|
||||
#define R_RAM_ADDR_H 0x01
|
||||
#define R_RAM_ADDR_L 0x02
|
||||
#define R_RAM_LEN_H 0x03
|
||||
#define R_RAM_LEN_L 0x04
|
||||
#define FLASH_LOAD_STA 0x05
|
||||
#define FLASH_LOAD_STA_CHK BIT(7)
|
||||
|
||||
#define R_RAM_CTRL 0x05
|
||||
/* bit positions */
|
||||
#define FLASH_DONE BIT(7)
|
||||
#define BOOT_LOAD_DONE BIT(6)
|
||||
#define CRC_OK BIT(5)
|
||||
#define LOAD_DONE BIT(4)
|
||||
#define O_RW_DONE BIT(3)
|
||||
#define FUSE_BUSY BIT(2)
|
||||
#define DECRYPT_EN BIT(1)
|
||||
#define LOAD_START BIT(0)
|
||||
|
||||
#define FLASH_ADDR_HIGH 0x0F
|
||||
#define FLASH_ADDR_LOW 0x10
|
||||
#define FLASH_LEN_HIGH 0x31
|
||||
#define FLASH_LEN_LOW 0x32
|
||||
#define R_FLASH_RW_CTRL 0x33
|
||||
/* bit positions */
|
||||
#define READ_DELAY_SELECT BIT(7)
|
||||
#define GENERAL_INSTRUCTION_EN BIT(6)
|
||||
#define FLASH_ERASE_EN BIT(5)
|
||||
#define RDID_READ_EN BIT(4)
|
||||
#define REMS_READ_EN BIT(3)
|
||||
#define WRITE_STATUS_EN BIT(2)
|
||||
#define FLASH_READ BIT(1)
|
||||
#define FLASH_WRITE BIT(0)
|
||||
|
||||
#define FLASH_BUF_BASE_ADDR 0x60
|
||||
#define FLASH_BUF_LEN 0x20
|
||||
|
||||
#define XTAL_FRQ_SEL 0x3F
|
||||
/* bit field positions */
|
||||
#define XTAL_FRQ_SEL_POS 5
|
||||
@ -184,10 +237,15 @@
|
||||
#define AP_AUX_CTRL_ADDRONLY 0x20
|
||||
|
||||
#define AP_AUX_BUFF_START 0x15
|
||||
#define PIXEL_CLOCK_L 0x25
|
||||
#define PIXEL_CLOCK_H 0x26
|
||||
#define PIXEL_CLOCK_L 0x25
|
||||
#define PIXEL_CLOCK_H 0x26
|
||||
|
||||
#define AP_AUX_COMMAND 0x27 /* com+len */
|
||||
#define LENGTH_SHIFT 4
|
||||
#define DPCD_READ 0x09
|
||||
#define DPCD_WRITE 0x08
|
||||
#define DPCD_CMD(len, cmd) ((((len) - 1) << LENGTH_SHIFT) | (cmd))
|
||||
|
||||
#define AP_AUX_COMMAND 0x27 /* com+len */
|
||||
/* Bit 0&1: 3D video structure */
|
||||
/* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */
|
||||
#define AP_AV_STATUS 0x28
|
||||
@ -392,16 +450,23 @@ struct anx7625_data {
|
||||
struct platform_device *audio_pdev;
|
||||
int hpd_status;
|
||||
int hpd_high_cnt;
|
||||
int dp_en;
|
||||
int hdcp_cp;
|
||||
/* Lock for work queue */
|
||||
struct mutex lock;
|
||||
struct i2c_client *client;
|
||||
struct anx7625_i2c_client i2c;
|
||||
struct i2c_client *last_client;
|
||||
struct timer_list hdcp_timer;
|
||||
struct s_edid_data slimport_edid_p;
|
||||
struct device *codec_dev;
|
||||
hdmi_codec_plugged_cb plugged_cb;
|
||||
struct work_struct work;
|
||||
struct workqueue_struct *workqueue;
|
||||
struct delayed_work hdcp_work;
|
||||
struct workqueue_struct *hdcp_workqueue;
|
||||
/* Lock for hdcp work queue */
|
||||
struct mutex hdcp_wq_lock;
|
||||
char edid_block;
|
||||
struct display_timing dt;
|
||||
u8 display_timing_valid;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user