net: phy: dp83tg720: wake up PHYs in managed mode
In case this PHY is bootstrapped for managed mode, we need to manually
wake it. Otherwise no link will be detected.
Cc: stable@vger.kernel.org
Fixes: cb80ee2f9b
("net: phy: Add support for the DP83TG720S Ethernet PHY")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Link: https://lore.kernel.org/r/20240614094516.1481231-1-o.rempel@pengutronix.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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@ -17,6 +17,11 @@
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#define DP83TG720S_PHY_RESET 0x1f
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#define DP83TG720S_HW_RESET BIT(15)
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#define DP83TG720S_LPS_CFG3 0x18c
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/* Power modes are documented as bit fields but used as values */
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/* Power Mode 0 is Normal mode */
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#define DP83TG720S_LPS_CFG3_PWR_MODE_0 BIT(0)
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#define DP83TG720S_RGMII_DELAY_CTRL 0x602
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/* In RGMII mode, Enable or disable the internal delay for RXD */
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#define DP83TG720S_RGMII_RX_CLK_SEL BIT(1)
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@ -154,10 +159,17 @@ static int dp83tg720_config_init(struct phy_device *phydev)
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*/
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usleep_range(1000, 2000);
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if (phy_interface_is_rgmii(phydev))
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return dp83tg720_config_rgmii_delay(phydev);
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if (phy_interface_is_rgmii(phydev)) {
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ret = dp83tg720_config_rgmii_delay(phydev);
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if (ret)
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return ret;
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}
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return 0;
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/* In case the PHY is bootstrapped in managed mode, we need to
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* wake it.
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*/
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return phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LPS_CFG3,
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DP83TG720S_LPS_CFG3_PWR_MODE_0);
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}
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static struct phy_driver dp83tg720_driver[] = {
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