phy: qcom: qmp-pcie: restore compatibility with existing DTs
[ Upstream commit 912cee11c14376a6f707d72fcaf343a40bff48e8 ] Existing device trees specify only a single clock-output-name for the PCIe PHYs. The function phy_aux_clk_register() expects a second entry in that property. When it doesn't find it, it returns an error, thus failing the probe of the PHY and thus breaking support for the corresponding PCIe host. Follow the approach of the combo USB+DT PHY and generate the name for the AUX clocks instead of requiring it in DT. Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-1-730d1811acf4@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -3730,14 +3730,11 @@ static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np)
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{
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struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed;
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struct clk_init_data init = { };
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int ret;
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char name[64];
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ret = of_property_read_string_index(np, "clock-output-names", 1, &init.name);
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if (ret) {
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dev_err(qmp->dev, "%pOFn: No clock-output-names index 1\n", np);
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return ret;
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}
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snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev));
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init.name = name;
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init.ops = &clk_fixed_rate_ops;
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fixed->fixed_rate = qmp->cfg->aux_clock_rate;
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