From e9cd3444e8e0b4800257797eb9aaa298d761bfce Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 23 Nov 2017 15:34:31 +0100 Subject: [PATCH 1/9] arm64: dts: exynos: Add CPU performance counters to Exynos5433 boards Enable support for ARM Performance Monitoring Units available in Cortex-A53 and Cortex-A57 CPU cores for Exynos5433 SoCs. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 7fe994b750da..9484d2f867dc 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -247,6 +247,24 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x18000000>; + arm_a53_pmu { + compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + arm_a57_pmu { + compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + chipid@10000000 { compatible = "samsung,exynos4210-chipid"; reg = <0x10000000 0x100>; From bb7b2c6594856577452758599c8433df1ff32cc3 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 29 Nov 2017 12:13:20 +0100 Subject: [PATCH 2/9] arm64: dts: exynos: Add support for S3FWRN5 NFC chip to TM2(e) boards Add device tree node with S3FWRN5 NFC chip to TM2(e) boards. The chip is connected through HS-I2C bus #4. Signed-off-by: Robert Baldyga [mszyprow: rebased onto v4.15-rc1, moved node to exynos5433-tm2-common.dtsi, rephrased commit message] Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi Tested-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 297597442c44..5028d7352856 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -741,6 +741,19 @@ }; }; +&hsi2c_4 { + status = "okay"; + + s3fwrn5: nfc@27 { + compatible = "samsung,s3fwrn5-i2c"; + reg = <0x27>; + interrupt-parent = <&gpa1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + s3fwrn5,en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>; + s3fwrn5,fw-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>; + }; +}; + &hsi2c_5 { status = "okay"; From c2607220720879cebcb971fcb0b1827a6e0129e2 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 29 Nov 2017 12:26:33 +0100 Subject: [PATCH 3/9] arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC This patch adds support for GSCL power domain to Exynos 5433 SoCs, which contains following devices: a clock controller, three GSCL video scalers and their SYSMMUs. Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 9484d2f867dc..2a03be0c9ae7 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -443,6 +443,7 @@ clocks = <&xxti>, <&cmu_top CLK_ACLK_GSCL_111>, <&cmu_top CLK_ACLK_GSCL_333>; + power-domains = <&pd_gscl>; }; cmu_apollo: clock-controller@11900000 { @@ -543,6 +544,13 @@ <&cmu_top CLK_ACLK_CAM1_552>; }; + pd_gscl: power-domain@105c4000 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c4000 0x20>; + #power-domain-cells = <0>; + label = "GSCL"; + }; + tmu_atlas0: tmu@10060000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10060000 0x200>; @@ -910,6 +918,7 @@ <&cmu_gscl CLK_ACLK_XIU_GSCLX>, <&cmu_gscl CLK_ACLK_GSCLBEND_333>; iommus = <&sysmmu_gscl0>; + power-domains = <&pd_gscl>; }; gsc_1: video-scaler@13C10000 { @@ -923,6 +932,7 @@ <&cmu_gscl CLK_ACLK_XIU_GSCLX>, <&cmu_gscl CLK_ACLK_GSCLBEND_333>; iommus = <&sysmmu_gscl1>; + power-domains = <&pd_gscl>; }; gsc_2: video-scaler@13C20000 { @@ -936,6 +946,7 @@ <&cmu_gscl CLK_ACLK_XIU_GSCLX>, <&cmu_gscl CLK_ACLK_GSCLBEND_333>; iommus = <&sysmmu_gscl2>; + power-domains = <&pd_gscl>; }; jpeg: codec@15020000 { @@ -1010,6 +1021,7 @@ clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>, <&cmu_gscl CLK_PCLK_SMMU_GSCL0>; #iommu-cells = <0>; + power-domains = <&pd_gscl>; }; sysmmu_gscl1: sysmmu@13c90000 { @@ -1020,6 +1032,7 @@ clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>, <&cmu_gscl CLK_PCLK_SMMU_GSCL1>; #iommu-cells = <0>; + power-domains = <&pd_gscl>; }; sysmmu_gscl2: sysmmu@13ca0000 { @@ -1030,6 +1043,7 @@ clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>, <&cmu_gscl CLK_PCLK_SMMU_GSCL2>; #iommu-cells = <0>; + power-domains = <&pd_gscl>; }; sysmmu_jpeg: sysmmu@15060000 { From 9715ed87c94e8839e7e7d32e038aa21dc81785d4 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 29 Nov 2017 12:26:34 +0100 Subject: [PATCH 4/9] arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC This patch adds support for DISP power domain to Exynos 5433 SoCs, which contains following devices: a clock controller, two display controllers (DECON and DECON TV), their SYSMMUs, MIC, DSI and HDMI video devices. Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 2a03be0c9ae7..95f30ccc00a3 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -386,6 +386,7 @@ <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, <&cmu_mif CLK_ACLK_DISP_333>; + power-domains = <&pd_disp>; }; cmu_aud: clock-controller@114c0000 { @@ -551,6 +552,13 @@ label = "GSCL"; }; + pd_disp: power-domain@105c4080 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c4080 0x20>; + #power-domain-cells = <0>; + label = "DISP"; + }; + tmu_atlas0: tmu@10060000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10060000 0x200>; @@ -754,6 +762,7 @@ clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", "pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk"; + power-domains = <&pd_disp>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = , , @@ -791,6 +800,7 @@ "aclk_xiu_decon0x", "pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk"; samsung,disp-sysreg = <&syscon_disp>; + power-domains = <&pd_disp>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = , , @@ -816,6 +826,7 @@ "phyclk_mipidphy0_rxclkesc0", "sclk_rgb_vclk_to_dsim0", "sclk_mipi"; + power-domains = <&pd_disp>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -839,6 +850,7 @@ clocks = <&cmu_disp CLK_PCLK_MIC0>, <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; + power-domains = <&pd_disp>; samsung,disp-syscon = <&syscon_disp>; status = "disabled"; @@ -980,6 +992,7 @@ clock-names = "pclk", "aclk"; clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>; + power-domains = <&pd_disp>; #iommu-cells = <0>; }; @@ -991,6 +1004,7 @@ clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>, <&cmu_disp CLK_ACLK_SMMU_DECON1X>; #iommu-cells = <0>; + power-domains = <&pd_disp>; }; sysmmu_tv0x: sysmmu@13a20000 { @@ -1001,6 +1015,7 @@ clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>, <&cmu_disp CLK_ACLK_SMMU_TV0X>; #iommu-cells = <0>; + power-domains = <&pd_disp>; }; sysmmu_tv1x: sysmmu@13a30000 { @@ -1011,6 +1026,7 @@ clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>, <&cmu_disp CLK_ACLK_SMMU_TV1X>; #iommu-cells = <0>; + power-domains = <&pd_disp>; }; sysmmu_gscl0: sysmmu@13c80000 { From e45dda53d38b8e0956be6b8db239611514c7d8dc Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 29 Nov 2017 12:26:35 +0100 Subject: [PATCH 5/9] arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC This patch adds support for MSCL power domain to Exynos 5433 SoCs, which contains following devices: a clock controller, JPEG codec device and its SYSMMU. Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 95f30ccc00a3..0a06be283a31 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -476,6 +476,7 @@ clocks = <&xxti>, <&cmu_top CLK_SCLK_JPEG_MSCL>, <&cmu_top CLK_ACLK_MSCL_400>; + power-domains = <&pd_mscl>; }; cmu_mfc: clock-controller@15280000 { @@ -552,6 +553,13 @@ label = "GSCL"; }; + pd_mscl: power-domain@105c4040 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c4040 0x20>; + #power-domain-cells = <0>; + label = "MSCL"; + }; + pd_disp: power-domain@105c4080 { compatible = "samsung,exynos5433-pd"; reg = <0x105c4080 0x20>; @@ -971,6 +979,7 @@ <&cmu_mscl CLK_ACLK_XIU_MSCLX>, <&cmu_mscl CLK_SCLK_JPEG>; iommus = <&sysmmu_jpeg>; + power-domains = <&pd_mscl>; }; mfc: codec@152E0000 { @@ -1070,6 +1079,7 @@ clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>, <&cmu_mscl CLK_ACLK_SMMU_JPEG>; #iommu-cells = <0>; + power-domains = <&pd_mscl>; }; sysmmu_mfc_0: sysmmu@15200000 { From c4e7aba66bf08ed6af292f9d2e54a2806a015349 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 29 Nov 2017 12:26:36 +0100 Subject: [PATCH 6/9] arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC This patch adds support for MFC power domain to Exynos 5433 SoCs, which contains following devices: a clock controller, MFC codec device and its SYSMMUs. Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0a06be283a31..cfa2a0d4dc2f 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -486,6 +486,7 @@ clock-names = "oscclk", "aclk_mfc_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; + power-domains = <&pd_mfc>; }; cmu_hevc: clock-controller@14f80000 { @@ -567,6 +568,13 @@ label = "DISP"; }; + pd_mfc: power-domain@105c4180 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c4180 0x20>; + #power-domain-cells = <0>; + label = "MFC"; + }; + tmu_atlas0: tmu@10060000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10060000 0x200>; @@ -992,6 +1000,7 @@ <&cmu_mfc CLK_ACLK_XIU_MFCX>; iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; iommu-names = "left", "right"; + power-domains = <&pd_mfc>; }; sysmmu_decon0x: sysmmu@13a00000 { @@ -1090,6 +1099,7 @@ clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>, <&cmu_mfc CLK_ACLK_SMMU_MFC_0>; #iommu-cells = <0>; + power-domains = <&pd_mfc>; }; sysmmu_mfc_1: sysmmu@15210000 { @@ -1100,6 +1110,7 @@ clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>, <&cmu_mfc CLK_ACLK_SMMU_MFC_1>; #iommu-cells = <0>; + power-domains = <&pd_mfc>; }; serial_0: serial@14c10000 { From 217d3f4f9ad5b4e51d8038560ce8906d19d1abe3 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 29 Nov 2017 12:26:37 +0100 Subject: [PATCH 7/9] arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC This patch adds support for AUD power domain to Exynos5433 SoCs, which contains following devices: a clock controller, a pin controller, LPASS module, I2S controller, ADMA PL330 engine and UART #3 device. Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index cfa2a0d4dc2f..2c019a0fd8e3 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -395,6 +395,7 @@ #clock-cells = <1>; clock-names = "oscclk", "fout_aud_pll"; clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; + power-domains = <&pd_aud>; }; cmu_bus0: clock-controller@13600000 { @@ -568,6 +569,13 @@ label = "DISP"; }; + pd_aud: power-domain@105c40c0 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c40c0 0x20>; + #power-domain-cells = <0>; + label = "AUD"; + }; + pd_mfc: power-domain@105c4180 { compatible = "samsung,exynos5433-pd"; reg = <0x105c4180 0x20>; @@ -687,6 +695,7 @@ compatible = "samsung,exynos5433-pinctrl"; reg = <0x114b0000 0x1000>; interrupts = ; + power-domains = <&pd_aud>; }; pinctrl_cpif: pinctrl@10fe0000 { @@ -1566,6 +1575,7 @@ clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; clock-names = "sfr0_ctrl"; samsung,pmu-syscon = <&pmu_system_controller>; + power-domains = <&pd_aud>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -1579,6 +1589,7 @@ #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; + power-domains = <&pd_aud>; }; i2s0: i2s0@11440000 { @@ -1595,6 +1606,7 @@ clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + power-domains = <&pd_aud>; status = "disabled"; }; @@ -1607,6 +1619,7 @@ clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; pinctrl-0 = <&uart_aud_bus>; + power-domains = <&pd_aud>; status = "disabled"; }; }; From 3b94d24dea6c1253a3bcec390401ddbf568125cd Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 29 Nov 2017 12:26:38 +0100 Subject: [PATCH 8/9] arm64: dts: exynos: Add remaining power domains to Exynos5433 SoC This patch adds support for G2D, G3D, CAM0, CAM1, ISP, HVEC power domains to Exynos5433 SoCs. Currently only clock controllers for those domains are defined. CAM1 is a parent of CAM0 power domain and CAM0 is a parent of ISP power domain. Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 2c019a0fd8e3..1962b8074349 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -361,6 +361,7 @@ clocks = <&xxti>, <&cmu_top CLK_ACLK_G2D_266>, <&cmu_top CLK_ACLK_G2D_400>; + power-domains = <&pd_g2d>; }; cmu_disp: clock-controller@13b90000 { @@ -432,6 +433,7 @@ clock-names = "oscclk", "aclk_g3d_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; + power-domains = <&pd_g3d>; }; cmu_gscl: clock-controller@13cf0000 { @@ -497,6 +499,7 @@ clock-names = "oscclk", "aclk_hevc_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; + power-domains = <&pd_hevc>; }; cmu_isp: clock-controller@146d0000 { @@ -510,6 +513,7 @@ clocks = <&xxti>, <&cmu_top CLK_ACLK_ISP_DIS_400>, <&cmu_top CLK_ACLK_ISP_400>; + power-domains = <&pd_isp>; }; cmu_cam0: clock-controller@120d0000 { @@ -525,6 +529,7 @@ <&cmu_top CLK_ACLK_CAM0_333>, <&cmu_top CLK_ACLK_CAM0_400>, <&cmu_top CLK_ACLK_CAM0_552>; + power-domains = <&pd_cam0>; }; cmu_cam1: clock-controller@145d0000 { @@ -546,6 +551,7 @@ <&cmu_top CLK_ACLK_CAM1_333>, <&cmu_top CLK_ACLK_CAM1_400>, <&cmu_top CLK_ACLK_CAM1_552>; + power-domains = <&pd_cam1>; }; pd_gscl: power-domain@105c4000 { @@ -555,6 +561,14 @@ label = "GSCL"; }; + pd_cam0: power-domain@105c4020 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c4020 0x20>; + #power-domain-cells = <0>; + power-domains = <&pd_cam1>; + label = "CAM0"; + }; + pd_mscl: power-domain@105c4040 { compatible = "samsung,exynos5433-pd"; reg = <0x105c4040 0x20>; @@ -562,6 +576,13 @@ label = "MSCL"; }; + pd_g3d: power-domain@105c4060 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c4060 0x20>; + #power-domain-cells = <0>; + label = "G3D"; + }; + pd_disp: power-domain@105c4080 { compatible = "samsung,exynos5433-pd"; reg = <0x105c4080 0x20>; @@ -569,6 +590,13 @@ label = "DISP"; }; + pd_cam1: power-domain@105c40a0 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c40a0 0x20>; + #power-domain-cells = <0>; + label = "CAM1"; + }; + pd_aud: power-domain@105c40c0 { compatible = "samsung,exynos5433-pd"; reg = <0x105c40c0 0x20>; @@ -576,6 +604,21 @@ label = "AUD"; }; + pd_g2d: power-domain@105c4120 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c4120 0x20>; + #power-domain-cells = <0>; + label = "G2D"; + }; + + pd_isp: power-domain@105c4140 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c4140 0x20>; + #power-domain-cells = <0>; + power-domains = <&pd_cam0>; + label = "ISP"; + }; + pd_mfc: power-domain@105c4180 { compatible = "samsung,exynos5433-pd"; reg = <0x105c4180 0x20>; @@ -583,6 +626,13 @@ label = "MFC"; }; + pd_hevc: power-domain@105c41c0 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c41c0 0x20>; + #power-domain-cells = <0>; + label = "HEVC"; + }; + tmu_atlas0: tmu@10060000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10060000 0x200>; From 3808354701090723b53c73afaccfcafdeb8a5bfe Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Fri, 1 Dec 2017 12:33:51 +0100 Subject: [PATCH 9/9] arm64: dts: exynos: Increase bus frequency for MHL chip sii8620 supports 1 MHz clock, it allows faster transmissions and according to extensive tests allows to mitigate some obscure bugs in I2C client logic of the chip. Signed-off-by: Andrzej Hajda Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 5028d7352856..2e4bc94e9b8b 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -769,6 +769,7 @@ &hsi2c_7 { status = "okay"; + clock-frequency = <1000000>; sii8620@39 { reg = <0x39>;