ARM: EXYNOS: replace clock.c for other new EXYNOS SoCs
This patch changes the name of clock.c to clock-exynos4.c for other EXYNOS series such as EXYNOS5. And since the header file of clock is used only in arch/arm/mach-exynos, moves it in the local directory. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Kukjin Kim
parent
c15a04338b
commit
ce9c00eea1
@ -12,7 +12,8 @@ obj- :=
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# Core
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obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o
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obj-$(CONFIG_ARCH_EXYNOS) += common.o
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obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
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obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
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obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
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@ -1,5 +1,4 @@
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/* linux/arch/arm/mach-exynos4/clock.c
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*
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/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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@ -26,9 +25,9 @@
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/sysmmu.h>
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#include <mach/exynos4-clock.h>
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#include "common.h"
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#include "clock-exynos4.h"
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#ifdef CONFIG_PM_SLEEP
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static struct sleep_save exynos4_clock_save[] = {
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@ -215,8 +214,8 @@ static struct clksrc_clk clk_mout_apll = {
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.clk = {
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.name = "mout_apll",
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},
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.sources = &clk_src_apll,
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.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
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.sources = &clk_src_apll,
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.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
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};
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struct clksrc_clk clk_sclk_apll = {
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@ -224,22 +223,22 @@ struct clksrc_clk clk_sclk_apll = {
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.name = "sclk_apll",
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.parent = &clk_mout_apll.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
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};
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struct clksrc_clk clk_mout_epll = {
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.clk = {
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.name = "mout_epll",
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},
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.sources = &clk_src_epll,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
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.sources = &clk_src_epll,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
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};
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struct clksrc_clk clk_mout_mpll = {
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.clk = {
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.clk = {
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.name = "mout_mpll",
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},
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.sources = &clk_src_mpll,
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.sources = &clk_src_mpll,
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/* reg_src will be added in each SoCs' clock */
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};
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@ -258,8 +257,8 @@ static struct clksrc_clk clk_moutcore = {
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.clk = {
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.name = "moutcore",
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},
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.sources = &clkset_moutcore,
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.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
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.sources = &clkset_moutcore,
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.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
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};
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static struct clksrc_clk clk_coreclk = {
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@ -267,7 +266,7 @@ static struct clksrc_clk clk_coreclk = {
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.name = "core_clk",
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.parent = &clk_moutcore.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
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};
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static struct clksrc_clk clk_armclk = {
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@ -282,7 +281,7 @@ static struct clksrc_clk clk_aclk_corem0 = {
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.name = "aclk_corem0",
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_cores = {
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@ -290,7 +289,7 @@ static struct clksrc_clk clk_aclk_cores = {
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.name = "aclk_cores",
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_corem1 = {
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@ -298,7 +297,7 @@ static struct clksrc_clk clk_aclk_corem1 = {
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.name = "aclk_corem1",
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
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};
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static struct clksrc_clk clk_periphclk = {
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@ -306,7 +305,7 @@ static struct clksrc_clk clk_periphclk = {
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.name = "periphclk",
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
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};
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/* Core list of CMU_CORE side */
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@ -325,8 +324,8 @@ static struct clksrc_clk clk_mout_corebus = {
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.clk = {
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.name = "mout_corebus",
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},
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.sources = &clkset_mout_corebus,
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.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
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.sources = &clkset_mout_corebus,
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.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
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};
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static struct clksrc_clk clk_sclk_dmc = {
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@ -334,7 +333,7 @@ static struct clksrc_clk clk_sclk_dmc = {
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.name = "sclk_dmc",
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.parent = &clk_mout_corebus.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_cored = {
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@ -342,7 +341,7 @@ static struct clksrc_clk clk_aclk_cored = {
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.name = "aclk_cored",
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.parent = &clk_sclk_dmc.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_corep = {
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@ -350,7 +349,7 @@ static struct clksrc_clk clk_aclk_corep = {
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.name = "aclk_corep",
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.parent = &clk_aclk_cored.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_acp = {
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@ -358,7 +357,7 @@ static struct clksrc_clk clk_aclk_acp = {
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.name = "aclk_acp",
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.parent = &clk_mout_corebus.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
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};
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static struct clksrc_clk clk_pclk_acp = {
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@ -366,7 +365,7 @@ static struct clksrc_clk clk_pclk_acp = {
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.name = "pclk_acp",
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.parent = &clk_aclk_acp.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
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};
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/* Core list of CMU_TOP side */
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@ -385,36 +384,36 @@ static struct clksrc_clk clk_aclk_200 = {
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.clk = {
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.name = "aclk_200",
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},
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_100 = {
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.clk = {
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.name = "aclk_100",
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},
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
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};
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static struct clksrc_clk clk_aclk_160 = {
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.clk = {
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.name = "aclk_160",
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},
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
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};
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struct clksrc_clk clk_aclk_133 = {
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.clk = {
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.name = "aclk_133",
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},
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
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};
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static struct clk *clkset_vpllsrc_list[] = {
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@ -433,8 +432,8 @@ static struct clksrc_clk clk_vpllsrc = {
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.enable = exynos4_clksrc_mask_top_ctrl,
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.ctrlbit = (1 << 0),
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},
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.sources = &clkset_vpllsrc,
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.reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
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.sources = &clkset_vpllsrc,
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.reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
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};
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static struct clk *clkset_sclk_vpll_list[] = {
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@ -451,8 +450,8 @@ struct clksrc_clk clk_sclk_vpll = {
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.clk = {
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.name = "sclk_vpll",
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},
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.sources = &clkset_sclk_vpll,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
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.sources = &clkset_sclk_vpll,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
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};
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static struct clk init_clocks_off[] = {
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@ -816,8 +815,8 @@ static struct clksrc_clk clk_mout_g2d0 = {
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.clk = {
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.name = "mout_g2d0",
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},
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.sources = &clkset_mout_g2d0,
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.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
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.sources = &clkset_mout_g2d0,
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.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
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};
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static struct clk *clkset_mout_g2d1_list[] = {
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@ -834,8 +833,8 @@ static struct clksrc_clk clk_mout_g2d1 = {
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.clk = {
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.name = "mout_g2d1",
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},
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.sources = &clkset_mout_g2d1,
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.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
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.sources = &clkset_mout_g2d1,
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.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
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};
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static struct clk *clkset_mout_g2d_list[] = {
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@ -862,8 +861,8 @@ static struct clksrc_clk clk_mout_mfc0 = {
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.clk = {
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.name = "mout_mfc0",
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},
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.sources = &clkset_mout_mfc0,
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.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
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.sources = &clkset_mout_mfc0,
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.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
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};
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static struct clk *clkset_mout_mfc1_list[] = {
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@ -880,8 +879,8 @@ static struct clksrc_clk clk_mout_mfc1 = {
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.clk = {
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.name = "mout_mfc1",
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},
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.sources = &clkset_mout_mfc1,
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.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
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.sources = &clkset_mout_mfc1,
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.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
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};
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static struct clk *clkset_mout_mfc_list[] = {
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@ -917,7 +916,7 @@ static struct clksrc_clk clk_sclk_dac = {
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static struct clksrc_clk clk_sclk_pixel = {
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.clk = {
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.name = "sclk_pixel",
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.parent = &clk_sclk_vpll.clk,
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.parent = &clk_sclk_vpll.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
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};
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@ -953,7 +952,7 @@ static struct clksrc_sources clkset_sclk_mixer = {
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};
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static struct clksrc_clk clk_sclk_mixer = {
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.clk = {
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.clk = {
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.name = "sclk_mixer",
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.enable = exynos4_clksrc_mask_tv_ctrl,
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.ctrlbit = (1 << 4),
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@ -970,7 +969,7 @@ static struct clksrc_clk *sclk_tv[] = {
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};
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static struct clksrc_clk clk_dout_mmc0 = {
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.clk = {
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.clk = {
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.name = "dout_mmc0",
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},
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.sources = &clkset_group,
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@ -979,7 +978,7 @@ static struct clksrc_clk clk_dout_mmc0 = {
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};
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static struct clksrc_clk clk_dout_mmc1 = {
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.clk = {
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.clk = {
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.name = "dout_mmc1",
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},
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.sources = &clkset_group,
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@ -988,7 +987,7 @@ static struct clksrc_clk clk_dout_mmc1 = {
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};
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static struct clksrc_clk clk_dout_mmc2 = {
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.clk = {
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.clk = {
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.name = "dout_mmc2",
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},
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.sources = &clkset_group,
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@ -997,7 +996,7 @@ static struct clksrc_clk clk_dout_mmc2 = {
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};
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static struct clksrc_clk clk_dout_mmc3 = {
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.clk = {
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.clk = {
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.name = "dout_mmc3",
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},
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.sources = &clkset_group,
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@ -1016,7 +1015,7 @@ static struct clksrc_clk clk_dout_mmc4 = {
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.clk = {
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.name = "sclk_pwm",
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.enable = exynos4_clksrc_mask_peril0_ctrl,
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.ctrlbit = (1 << 24),
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@ -1025,7 +1024,7 @@ static struct clksrc_clk clksrcs[] = {
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.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.clk = {
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.name = "sclk_csis",
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.devname = "s5p-mipi-csis.0",
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.enable = exynos4_clksrc_mask_cam_ctrl,
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@ -1035,7 +1034,7 @@ static struct clksrc_clk clksrcs[] = {
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.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
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}, {
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.clk = {
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.clk = {
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.name = "sclk_csis",
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.devname = "s5p-mipi-csis.1",
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.enable = exynos4_clksrc_mask_cam_ctrl,
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@ -1045,7 +1044,7 @@ static struct clksrc_clk clksrcs[] = {
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.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
|
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.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_cam0",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
@ -1054,7 +1053,7 @@ static struct clksrc_clk clksrcs[] = {
|
||||
.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_cam1",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 20),
|
||||
@ -1063,7 +1062,7 @@ static struct clksrc_clk clksrcs[] = {
|
||||
.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.devname = "exynos4-fimc.0",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
@ -1073,7 +1072,7 @@ static struct clksrc_clk clksrcs[] = {
|
||||
.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.devname = "exynos4-fimc.1",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
@ -1083,7 +1082,7 @@ static struct clksrc_clk clksrcs[] = {
|
||||
.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.devname = "exynos4-fimc.2",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
@ -1093,7 +1092,7 @@ static struct clksrc_clk clksrcs[] = {
|
||||
.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.devname = "exynos4-fimc.3",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
@ -1103,7 +1102,7 @@ static struct clksrc_clk clksrcs[] = {
|
||||
.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
.devname = "exynos4-fb.0",
|
||||
.enable = exynos4_clksrc_mask_lcd0_ctrl,
|
||||
@ -1113,14 +1112,14 @@ static struct clksrc_clk clksrcs[] = {
|
||||
.reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_fimg2d",
|
||||
},
|
||||
.sources = &clkset_mout_g2d,
|
||||
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_mfc",
|
||||
.devname = "s5p-mfc",
|
||||
},
|
||||
@ -1128,9 +1127,9 @@ static struct clksrc_clk clksrcs[] = {
|
||||
.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_dwmmc",
|
||||
.parent = &clk_dout_mmc4.clk,
|
||||
.parent = &clk_dout_mmc4.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
},
|
||||
@ -1151,7 +1150,7 @@ static struct clksrc_clk clk_sclk_uart0 = {
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_uart1 = {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "uclk1",
|
||||
.devname = "exynos4210-uart.1",
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
@ -1163,7 +1162,7 @@ static struct clksrc_clk clk_sclk_uart1 = {
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_uart2 = {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "uclk1",
|
||||
.devname = "exynos4210-uart.2",
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
@ -1175,7 +1174,7 @@ static struct clksrc_clk clk_sclk_uart2 = {
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_uart3 = {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "uclk1",
|
||||
.devname = "exynos4210-uart.3",
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
@ -1187,7 +1186,7 @@ static struct clksrc_clk clk_sclk_uart3 = {
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_mmc0 = {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.parent = &clk_dout_mmc0.clk,
|
||||
@ -1198,10 +1197,10 @@ static struct clksrc_clk clk_sclk_mmc0 = {
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_mmc1 = {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.parent = &clk_dout_mmc1.clk,
|
||||
.parent = &clk_dout_mmc1.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
},
|
||||
@ -1209,10 +1208,10 @@ static struct clksrc_clk clk_sclk_mmc1 = {
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_mmc2 = {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.parent = &clk_dout_mmc2.clk,
|
||||
.parent = &clk_dout_mmc2.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
},
|
||||
@ -1220,10 +1219,10 @@ static struct clksrc_clk clk_sclk_mmc2 = {
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_mmc3 = {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.parent = &clk_dout_mmc3.clk,
|
||||
.parent = &clk_dout_mmc3.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
},
|
||||
@ -1231,11 +1230,11 @@ static struct clksrc_clk clk_sclk_mmc3 = {
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_spi0 = {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_spi",
|
||||
.devname = "s3c64xx-spi.0",
|
||||
.devname = "s3c64xx-spi.0",
|
||||
.enable = exynos4_clksrc_mask_peril1_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
.ctrlbit = (1 << 16),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
|
||||
@ -1243,11 +1242,11 @@ static struct clksrc_clk clk_sclk_spi0 = {
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_spi1 = {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_spi",
|
||||
.devname = "s3c64xx-spi.1",
|
||||
.devname = "s3c64xx-spi.1",
|
||||
.enable = exynos4_clksrc_mask_peril1_ctrl,
|
||||
.ctrlbit = (1 << 20),
|
||||
.ctrlbit = (1 << 20),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
|
||||
@ -1255,11 +1254,11 @@ static struct clksrc_clk clk_sclk_spi1 = {
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_spi2 = {
|
||||
.clk = {
|
||||
.clk = {
|
||||
.name = "sclk_spi",
|
||||
.devname = "s3c64xx-spi.2",
|
||||
.devname = "s3c64xx-spi.2",
|
||||
.enable = exynos4_clksrc_mask_peril1_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
|
||||
@ -1,5 +1,4 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
@ -28,9 +28,9 @@
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/exynos4-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4210_clock_save[] = {
|
||||
|
||||
@ -28,9 +28,9 @@
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/exynos4-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4212_clock_save[] = {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user