pinctrl: samsung: Fix NULL pointer exception on external interrupts on S3C24xx
After commit8b1bd11c1f("pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank"), the S3C24xx (and probably S3C64xx as well) fails: Unable to handle kernel NULL pointer dereference at virtual address 000000a8 ... (s3c24xx_demux_eint4_7) from [<c004469c>] (__handle_domain_irq+0x6c/0xcc) (__handle_domain_irq) from [<c0009444>] (s3c24xx_handle_irq+0x6c/0x12c) (s3c24xx_handle_irq) from [<c000e5fc>] (__irq_svc+0x5c/0x78) Mentioned commit moved the pointer to controller's base IO memory address from each controller's driver data (samsung_pinctrl_drv_data) to per-bank structure (samsung_pin_bank). The external interrupt demux handlers (s3c24xx_demux_eint()) tried to get this base address from opaque pointer stored under irq_chip data: struct irq_data *irqd = irq_desc_get_irq_data(desc); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); ... pend = readl(bank->eint_base + EINTPEND_REG); which is wrong because this is hardware irq and it bank was never set for this irq_chip. For S3C24xx and S3C64xx, this partially reverts mentioned commit by bringing back the virt_base stored under each controller's driver data (samsung_pinctrl_drv_data). This virt_base address will be now duplicated: - samsung_pinctrl_drv_data->virt_base: used on S3C24xx and S3C64xx, - samsung_pin_bank->pctl_base: used on Exynos. Fixes:8b1bd11c1f("pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank") Cc: <stable@vger.kernel.org> Cc: Sergio Prado <sergio.prado@e-labworks.com> Reported-by: Sergio Prado <sergio.prado@e-labworks.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Lihua Yao <ylhuajnu@163.com>
This commit is contained in:
Krzysztof Kozlowski
parent
5771a8c088
commit
cee7413d84
@ -151,7 +151,7 @@ static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
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u32 val;
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/* Make sure that pin is configured as interrupt */
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reg = bank->pctl_base + bank->pctl_offset;
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reg = d->virt_base + bank->pctl_offset;
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shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
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mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
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@ -184,7 +184,7 @@ static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
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s3c24xx_eint_set_handler(data, type);
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/* Set up interrupt trigger */
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reg = bank->eint_base + EINT_REG(index);
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reg = d->virt_base + EINT_REG(index);
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shift = EINT_OFFS(index);
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val = readl(reg);
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@ -259,29 +259,32 @@ static void s3c2410_demux_eint0_3(struct irq_desc *desc)
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static void s3c2412_eint0_3_ack(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long bitval = 1UL << data->hwirq;
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writel(bitval, bank->eint_base + EINTPEND_REG);
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writel(bitval, d->virt_base + EINTPEND_REG);
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}
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static void s3c2412_eint0_3_mask(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long mask;
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mask = readl(bank->eint_base + EINTMASK_REG);
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mask = readl(d->virt_base + EINTMASK_REG);
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mask |= (1UL << data->hwirq);
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writel(mask, bank->eint_base + EINTMASK_REG);
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writel(mask, d->virt_base + EINTMASK_REG);
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}
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static void s3c2412_eint0_3_unmask(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long mask;
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mask = readl(bank->eint_base + EINTMASK_REG);
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mask = readl(d->virt_base + EINTMASK_REG);
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mask &= ~(1UL << data->hwirq);
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writel(mask, bank->eint_base + EINTMASK_REG);
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writel(mask, d->virt_base + EINTMASK_REG);
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}
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static struct irq_chip s3c2412_eint0_3_chip = {
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@ -316,31 +319,34 @@ static void s3c2412_demux_eint0_3(struct irq_desc *desc)
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static void s3c24xx_eint_ack(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned char index = bank->eint_offset + data->hwirq;
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writel(1UL << index, bank->eint_base + EINTPEND_REG);
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writel(1UL << index, d->virt_base + EINTPEND_REG);
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}
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static void s3c24xx_eint_mask(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned char index = bank->eint_offset + data->hwirq;
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unsigned long mask;
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mask = readl(bank->eint_base + EINTMASK_REG);
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mask = readl(d->virt_base + EINTMASK_REG);
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mask |= (1UL << index);
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writel(mask, bank->eint_base + EINTMASK_REG);
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writel(mask, d->virt_base + EINTMASK_REG);
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}
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static void s3c24xx_eint_unmask(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned char index = bank->eint_offset + data->hwirq;
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unsigned long mask;
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mask = readl(bank->eint_base + EINTMASK_REG);
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mask = readl(d->virt_base + EINTMASK_REG);
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mask &= ~(1UL << index);
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writel(mask, bank->eint_base + EINTMASK_REG);
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writel(mask, d->virt_base + EINTMASK_REG);
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}
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static struct irq_chip s3c24xx_eint_chip = {
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@ -356,14 +362,13 @@ static inline void s3c24xx_demux_eint(struct irq_desc *desc,
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{
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struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_data *irqd = irq_desc_get_irq_data(desc);
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = data->drvdata;
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unsigned int pend, mask;
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chained_irq_enter(chip, desc);
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pend = readl(bank->eint_base + EINTPEND_REG);
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mask = readl(bank->eint_base + EINTMASK_REG);
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pend = readl(d->virt_base + EINTPEND_REG);
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mask = readl(d->virt_base + EINTMASK_REG);
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pend &= ~mask;
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pend &= range;
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@ -280,7 +280,7 @@ static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
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u32 val;
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/* Make sure that pin is configured as interrupt */
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reg = bank->pctl_base + bank->pctl_offset;
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reg = d->virt_base + bank->pctl_offset;
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shift = pin;
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if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) {
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/* 4-bit bank type with 2 con regs */
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@ -308,8 +308,9 @@ static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
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static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
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void __iomem *reg = bank->eint_base + EINTMASK_REG(bank->eint_offset);
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void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset);
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u32 val;
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val = readl(reg);
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@ -333,8 +334,9 @@ static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)
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static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
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void __iomem *reg = bank->eint_base + EINTPEND_REG(bank->eint_offset);
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void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset);
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writel(1 << index, reg);
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}
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@ -357,7 +359,7 @@ static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
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s3c64xx_irq_set_handler(irqd, type);
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/* Set up interrupt trigger */
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reg = bank->eint_base + EINTCON_REG(bank->eint_offset);
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reg = d->virt_base + EINTCON_REG(bank->eint_offset);
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shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
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shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */
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@ -409,8 +411,7 @@ static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc);
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struct irq_data *irqd = irq_desc_get_irq_data(desc);
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
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chained_irq_enter(chip, desc);
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@ -420,7 +421,7 @@ static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
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unsigned int pin;
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unsigned int virq;
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svc = readl(bank->eint_base + SERVICE_REG);
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svc = readl(drvdata->virt_base + SERVICE_REG);
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group = SVC_GROUP(svc);
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pin = svc & SVC_NUM_MASK;
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@ -515,15 +516,15 @@ static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)
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{
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struct s3c64xx_eint0_domain_data *ddata =
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irq_data_get_irq_chip_data(irqd);
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struct samsung_pin_bank *bank = ddata->bank;
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struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
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u32 val;
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val = readl(bank->eint_base + EINT0MASK_REG);
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val = readl(d->virt_base + EINT0MASK_REG);
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if (mask)
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val |= 1 << ddata->eints[irqd->hwirq];
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else
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val &= ~(1 << ddata->eints[irqd->hwirq]);
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writel(val, bank->eint_base + EINT0MASK_REG);
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writel(val, d->virt_base + EINT0MASK_REG);
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}
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static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)
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@ -540,10 +541,10 @@ static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)
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{
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struct s3c64xx_eint0_domain_data *ddata =
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irq_data_get_irq_chip_data(irqd);
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struct samsung_pin_bank *bank = ddata->bank;
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struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
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writel(1 << ddata->eints[irqd->hwirq],
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bank->eint_base + EINT0PEND_REG);
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d->virt_base + EINT0PEND_REG);
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}
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static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
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@ -551,7 +552,7 @@ static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
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struct s3c64xx_eint0_domain_data *ddata =
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irq_data_get_irq_chip_data(irqd);
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struct samsung_pin_bank *bank = ddata->bank;
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struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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void __iomem *reg;
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int trigger;
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u8 shift;
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@ -566,7 +567,7 @@ static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
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s3c64xx_irq_set_handler(irqd, type);
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/* Set up interrupt trigger */
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reg = bank->eint_base + EINT0CON0_REG;
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reg = d->virt_base + EINT0CON0_REG;
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shift = ddata->eints[irqd->hwirq];
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if (shift >= EINT_MAX_PER_REG) {
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reg += 4;
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@ -598,19 +599,14 @@ static struct irq_chip s3c64xx_eint0_irq_chip = {
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static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_data *irqd = irq_desc_get_irq_data(desc);
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struct s3c64xx_eint0_domain_data *ddata =
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irq_data_get_irq_chip_data(irqd);
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struct samsung_pin_bank *bank = ddata->bank;
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struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc);
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struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
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unsigned int pend, mask;
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chained_irq_enter(chip, desc);
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pend = readl(bank->eint_base + EINT0PEND_REG);
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mask = readl(bank->eint_base + EINT0MASK_REG);
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pend = readl(drvdata->virt_base + EINT0PEND_REG);
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mask = readl(drvdata->virt_base + EINT0MASK_REG);
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pend = pend & range & ~mask;
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pend &= range;
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@ -1013,6 +1013,12 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
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bank->eint_base = virt_base[0];
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bank->pctl_base = virt_base[bdata->pctl_res_idx];
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}
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/*
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* Legacy platforms should provide only one resource with IO memory.
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* Store it as virt_base because legacy driver needs to access it
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* through samsung_pinctrl_drv_data.
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*/
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d->virt_base = virt_base[0];
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for_each_child_of_node(node, np) {
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if (!of_find_property(np, "gpio-controller", NULL))
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@ -247,6 +247,10 @@ struct samsung_pin_ctrl {
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/**
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* struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
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* @node: global list node
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* @virt_base: register base address of the controller; this will be equal
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* to each bank samsung_pin_bank->pctl_base and used on legacy
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* platforms (like S3C24XX or S3C64XX) which has to access the base
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* through samsung_pinctrl_drv_data, not samsung_pin_bank).
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* @dev: device instance representing the controller.
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* @irq: interrpt number used by the controller to notify gpio interrupts.
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* @ctrl: pin controller instance managed by the driver.
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@ -262,6 +266,7 @@ struct samsung_pin_ctrl {
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*/
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struct samsung_pinctrl_drv_data {
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struct list_head node;
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void __iomem *virt_base;
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struct device *dev;
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int irq;
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