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clk: meson: axg-audio: provide clk top signal name

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The peripheral clock on the sm1 goes through some muxes
and dividers before reaching the audio gates. To model that,
without repeating our self too much, the "top" clock signal
is introduced and will serve as a the parent of the gates.

On the axg and g12a, the top clock is just a pass-through to
the audio peripheral clock provided by the main controller.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Jerome Brunet 2019-10-02 11:15:28 +02:00
parent 8ff93f2832
commit cf52db456f
2 changed files with 17 additions and 4 deletions
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18
drivers/clk/meson/axg-audio.c
View File

@ -74,9 +74,7 @@
.hw.init = &(struct clk_init_data) { \ .hw.init = &(struct clk_init_data) { \
.name = "aud_"#_name, \ .name = "aud_"#_name, \
.ops = &clk_regmap_gate_ops, \ .ops = &clk_regmap_gate_ops, \
.parent_data = &(const struct clk_parent_data) { \ .parent_names = (const char *[]){ "aud_top" }, \
.fw_name = "pclk", \
}, \
.num_parents = 1, \ .num_parents = 1, \
}, \ }, \
} }
@ -504,6 +502,18 @@ static struct clk_regmap tdmout_c_lrclk =
AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
/* AXG/G12A Clocks */ /* AXG/G12A Clocks */
static struct clk_hw axg_aud_top = {
.init = &(struct clk_init_data) {
/* Provide aud_top signal name on axg and g12a */
.name = "aud_top",
.ops = &(const struct clk_ops) {},
.parent_data = &(const struct clk_parent_data) {
.fw_name = "pclk",
},
.num_parents = 1,
},
};
static struct clk_regmap mst_a_mclk_sel = static struct clk_regmap mst_a_mclk_sel =
AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL); AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
static struct clk_regmap mst_b_mclk_sel = static struct clk_regmap mst_b_mclk_sel =
@ -691,6 +701,7 @@ static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
[AUD_CLKID_TOP] = &axg_aud_top,
[NR_CLKS] = NULL, [NR_CLKS] = NULL,
}, },
.num = NR_CLKS, .num = NR_CLKS,
@ -835,6 +846,7 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
[AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw, [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
[AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw, [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
[AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw, [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
[AUD_CLKID_TOP] = &axg_aud_top,
[NR_CLKS] = NULL, [NR_CLKS] = NULL,
}, },
.num = NR_CLKS, .num = NR_CLKS,

3
drivers/clk/meson/axg-audio.h
View File

@ -116,9 +116,10 @@
#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153 #define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154 #define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
/* include the CLKIDs which are part of the DT bindings */ /* include the CLKIDs which are part of the DT bindings */
#include <dt-bindings/clock/axg-audio-clkc.h> #include <dt-bindings/clock/axg-audio-clkc.h>
#define NR_CLKS 163 #define NR_CLKS 164
#endif /*__AXG_AUDIO_CLKC_H */ #endif /*__AXG_AUDIO_CLKC_H */