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arm64: dts: qcom: sm8150: Add video clock controller node

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Add device node for video clock controller on Qualcomm
SM8150 platform.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240509-videocc-sm8150-dt-node-v4-2-e9617f65e946@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Satya Priya Kakitapalli 2024-05-09 15:54:04 +05:30 committed by Bjorn Andersson
parent e3e169cd28
commit cfe9685473
2 changed files with 18 additions and 0 deletions
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4
arch/arm64/boot/dts/qcom/sa8155p.dtsi
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@ -38,3 +38,7 @@
*/
compatible = "qcom,sa8155p-rpmhpd";
};
&videocc {
power-domains = <&rpmhpd SA8155P_CX>;
};

14
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@ -14,6 +14,7 @@
#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8150.h>
#include <dt-bindings/thermal/thermal.h>
@ -3738,6 +3739,19 @@
};
};
videocc: clock-controller@ab00000 {
compatible = "qcom,sm8150-videocc";
reg = <0 0x0ab00000 0 0x10000>;
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "bi_tcxo";
power-domains = <&rpmhpd SM8150_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
camnoc_virt: interconnect@ac00000 {
compatible = "qcom,sm8150-camnoc-virt";
reg = <0 0x0ac00000 0 0x1000>;