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arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF

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Align the ID_DFR0_EL1.PerfMon values with ID_AA64DFR0_EL1.PMUver.

Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221113163832.3154370-2-maz@kernel.org
This commit is contained in:
Marc Zyngier 2022-11-13 16:38:17 +00:00
parent 30a0b95b13
commit d017eeabd5
1 changed files with 2 additions and 0 deletions
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2
arch/arm64/include/asm/sysreg.h
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@ -698,6 +698,8 @@
#define ID_DFR0_PERFMON_8_1 0x4
#define ID_DFR0_PERFMON_8_4 0x5
#define ID_DFR0_PERFMON_8_5 0x6
#define ID_DFR0_PERFMON_8_7 0x7
#define ID_DFR0_PERFMON_IMP_DEF 0xf
#define ID_ISAR4_SWP_FRAC_SHIFT 28
#define ID_ISAR4_PSR_M_SHIFT 24