Texas Instruments K3 SoC family changes for 5.6, part 2.
- Add DMA nodes for am65x and j721e - Add McASP nodes for am65x and j721e, showcasing the DMA usage - Add CAL node for am65x - Add OV5640 camera support for am65x -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEEtQ6szHmfiBT7fujkyvq9MXlQGhEFAl4q0XwQHHQta3Jpc3Rv QHRpLmNvbQAKCRDK+r0xeVAaEUBXD/991t8giQUxr6+4XgwS8R60M2kY/rsSzM95 s+AyBjii8Qi6S50p3A2bHrY+iuyu73W6KUvRqfm4sTNlEto9a1UI+X6YrksoNOKU xW9b5BfLGMkTpgl3ZRA3ICZCzWMhxeRb7vvdcvZykgOVtRb5G5vD2IOXPXxNTjun p44sjHgJa1zhMI40yCSsF2t6pwo32iTw9ACphgWQAfluUJRFsqVGKLaTFGCFlhdh wQ83HKPBz1DfB1QBD4qzJbFa6/SMWW/GLBirNwmCSEI3tDPOTTGN4uilBDHLw1iN CPBLhi33sB51K0Sqr2+mKSuUqIboGcjZWL5s5jtWZuF2qSjldJvAws4CTDiPIlKe /YughbjgM5U+baOSzzIIiDSe3M+Ed8Lzgt7DT+7tAtW5kROzGH+xf6v33g3JHWn4 dFhmD+DpjH0vOiys56lP+5sGs8OcRCLb/XhbUlYYf2tUM2RWznpZ4VaYF0WLyuzV uIR0gkyF3S6QfTvMtA7jX2LWYagpGDbLoSsP+wpnxyXUiqnvRxjwW1qpBfn7nob0 D2FR7N0eE12ytoiK5/7siu8MAdrYsvGhsbu5RxZQuVEz58LuLsW6AKPHG1iEWMut epUKyCKLFBUxjOuCsOXKd5SlN8fm2Hd6iAyj/eYBFS4osLzI+DOp+x2GRD6c4Sq+ DJNPJeRY9g== =dL57 -----END PGP SIGNATURE----- Merge tag 'ti-k3-soc-for-v5.6-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt Texas Instruments K3 SoC family changes for 5.6, part 2. - Add DMA nodes for am65x and j721e - Add McASP nodes for am65x and j721e, showcasing the DMA usage - Add CAL node for am65x - Add OV5640 camera support for am65x * tag 'ti-k3-soc-for-v5.6-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: arm64: dts: ti: k3-am654-base-board: Add CSI2 OV5640 camera arm64: dts: ti: k3-am65-main Add CAL node arm64: dts: ti: k3-j721e-main: Add McASP nodes arm64: dts: ti: k3-am654-main: Add McASP nodes arm64: dts: ti: k3-j721e: DMA support arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS arm64: dts: ti: k3-am65: DMA support arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss arm64: dts: ti: k3-am65-main: Correct main NAVSS representation Link: https://lore.kernel.org/r/83546942-6215-9c3a-16cd-be7e7c000c0e@ti.com Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
d030a0dd01
@ -51,17 +51,6 @@
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};
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};
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secure_proxy_main: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x32c00000 0x00 0x100000>,
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<0x00 0x32400000 0x00 0x100000>,
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<0x00 0x32800000 0x00 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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serdes0: serdes@900000 {
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compatible = "ti,phy-am654-serdes";
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reg = <0x0 0x900000 0x0 0x2000>;
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@ -385,11 +374,15 @@
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ti,sci-rm-range-girq = <0x1>;
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};
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cbass_main_navss: interconnect0 {
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compatible = "simple-bus";
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main_navss {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dma-coherent;
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dma-ranges;
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ti,sci-dev-id = <118>;
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intr_main_navss: interrupt-controller1 {
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compatible = "ti,sci-intr";
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@ -414,6 +407,17 @@
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ti,sci-rm-range-global-event = <0x1>;
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};
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secure_proxy_main: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x32c00000 0x00 0x100000>,
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<0x00 0x32400000 0x00 0x100000>,
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<0x00 0x32800000 0x00 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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hwspinlock: spinlock@30e00000 {
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compatible = "ti,am654-hwspinlock";
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reg = <0x00 0x30e00000 0x00 0x1000>;
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@ -527,6 +531,41 @@
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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};
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ringacc: ringacc@3c000000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x0 0x3c000000 0x0 0x400000>,
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<0x0 0x38000000 0x0 0x400000>,
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<0x0 0x31120000 0x0 0x100>,
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<0x0 0x33000000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
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ti,num-rings = <818>;
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ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
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ti,dma-ring-reset-quirk;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <187>;
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msi-parent = <&inta_main_udmass>;
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};
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main_udmap: dma-controller@31150000 {
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compatible = "ti,am654-navss-main-udmap";
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reg = <0x0 0x31150000 0x0 0x100>,
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<0x0 0x34000000 0x0 0x100000>,
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<0x0 0x35000000 0x0 0x100000>;
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reg-names = "gcfg", "rchanrt", "tchanrt";
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msi-parent = <&inta_main_udmass>;
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#dma-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <188>;
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ti,ringacc = <&ringacc>;
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ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
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<0x2>; /* TX_CHAN */
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ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
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<0x5>; /* RX_CHAN */
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ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
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};
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};
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main_gpio0: main_gpio0@600000 {
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@ -624,4 +663,83 @@
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dma-coherent;
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interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
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};
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mcasp0: mcasp@2b00000 {
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compatible = "ti,am33xx-mcasp-audio";
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reg = <0x0 0x02b00000 0x0 0x2000>,
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<0x0 0x02b08000 0x0 0x1000>;
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reg-names = "mpu","dat";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx", "rx";
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dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
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dma-names = "tx", "rx";
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clocks = <&k3_clks 104 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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mcasp1: mcasp@2b10000 {
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compatible = "ti,am33xx-mcasp-audio";
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reg = <0x0 0x02b10000 0x0 0x2000>,
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<0x0 0x02b18000 0x0 0x1000>;
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reg-names = "mpu","dat";
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interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx", "rx";
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dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
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dma-names = "tx", "rx";
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clocks = <&k3_clks 105 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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mcasp2: mcasp@2b20000 {
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compatible = "ti,am33xx-mcasp-audio";
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reg = <0x0 0x02b20000 0x0 0x2000>,
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<0x0 0x02b28000 0x0 0x1000>;
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reg-names = "mpu","dat";
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx", "rx";
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dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
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dma-names = "tx", "rx";
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clocks = <&k3_clks 106 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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cal: cal@6f03000 {
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compatible = "ti,am654-cal";
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reg = <0x0 0x06f03000 0x0 0x400>,
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<0x0 0x06f03800 0x0 0x40>;
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reg-names = "cal_top",
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"cal_rx_core0";
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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ti,camerrx-control = <&scm_conf 0x40c0>;
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clock-names = "fck";
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clocks = <&k3_clks 2 0>;
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power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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csi2_0: port@0 {
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reg = <0>;
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};
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};
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};
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};
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@ -104,6 +104,52 @@
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};
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};
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mcu_navss {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dma-coherent;
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dma-ranges;
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ti,sci-dev-id = <119>;
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mcu_ringacc: ringacc@2b800000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
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ti,num-rings = <286>;
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ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
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ti,dma-ring-reset-quirk;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <195>;
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msi-parent = <&inta_main_udmass>;
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};
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mcu_udmap: dma-controller@285c0000 {
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compatible = "ti,am654-navss-mcu-udmap";
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x2aa00000 0x0 0x40000>;
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reg-names = "gcfg", "rchanrt", "tchanrt";
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msi-parent = <&inta_main_udmass>;
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#dma-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <194>;
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ti,ringacc = <&mcu_ringacc>;
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ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
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<0x2>; /* TX_CHAN */
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ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
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<0x4>; /* RX_CHAN */
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ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
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};
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};
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fss: fss@47000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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@ -53,6 +53,12 @@
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gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
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};
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};
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clk_ov5640_fixed: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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&wkup_pmx0 {
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@ -213,6 +219,23 @@
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c1_pins_default>;
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clock-frequency = <400000>;
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ov5640@3c {
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compatible = "ovti,ov5640";
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reg = <0x3c>;
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clocks = <&clk_ov5640_fixed>;
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clock-names = "xclk";
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port {
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csi2_cam0: endpoint {
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remote-endpoint = <&csi2_phy0>;
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clock-lanes = <0>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&main_i2c2 {
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@ -388,3 +411,11 @@
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#size-cells = <1>;
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};
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};
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&csi2_0 {
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csi2_phy0: endpoint {
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remote-endpoint = <&csi2_cam0>;
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clock-lanes = <0>;
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data-lanes = <1 2>;
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};
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};
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@ -40,17 +40,6 @@
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};
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};
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smmu0: smmu@36600000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0x36600000 0x0 0x100000>;
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power-domains = <&k3_pds 229 TI_SCI_PD_EXCLUSIVE>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror";
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#iommu-cells = <1>;
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};
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main_gpio_intr: interrupt-controller0 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <1>;
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@ -62,11 +51,15 @@
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ti,sci-rm-range-girq = <0x1>;
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};
|
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||||
cbass_main_navss: interconnect0 {
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compatible = "simple-bus";
|
||||
main_navss {
|
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compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
ti,sci-dev-id = <199>;
|
||||
|
||||
main_navss_intr: interrupt-controller1 {
|
||||
compatible = "ti,sci-intr";
|
||||
@ -91,6 +84,27 @@
|
||||
ti,sci-rm-range-global-event = <0xd>;
|
||||
};
|
||||
|
||||
secure_proxy_main: mailbox@32c00000 {
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
#mbox-cells = <1>;
|
||||
reg-names = "target_data", "rt", "scfg";
|
||||
reg = <0x00 0x32c00000 0x00 0x100000>,
|
||||
<0x00 0x32400000 0x00 0x100000>,
|
||||
<0x00 0x32800000 0x00 0x100000>;
|
||||
interrupt-names = "rx_011";
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
smmu0: smmu@36600000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
reg = <0x0 0x36600000 0x0 0x100000>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "eventq", "gerror";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@30e00000 {
|
||||
compatible = "ti,am654-hwspinlock";
|
||||
reg = <0x00 0x30e00000 0x00 0x1000>;
|
||||
@ -204,17 +218,42 @@
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
};
|
||||
|
||||
secure_proxy_main: mailbox@32c00000 {
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
#mbox-cells = <1>;
|
||||
reg-names = "target_data", "rt", "scfg";
|
||||
reg = <0x00 0x32c00000 0x00 0x100000>,
|
||||
<0x00 0x32400000 0x00 0x100000>,
|
||||
<0x00 0x32800000 0x00 0x100000>;
|
||||
interrupt-names = "rx_011";
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
main_ringacc: ringacc@3c000000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x0 0x3c000000 0x0 0x400000>,
|
||||
<0x0 0x38000000 0x0 0x400000>,
|
||||
<0x0 0x31120000 0x0 0x100>,
|
||||
<0x0 0x33000000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <1024>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <211>;
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
};
|
||||
|
||||
main_udmap: dma-controller@31150000 {
|
||||
compatible = "ti,j721e-navss-main-udmap";
|
||||
reg = <0x0 0x31150000 0x0 0x100>,
|
||||
<0x0 0x34000000 0x0 0x100000>,
|
||||
<0x0 0x35000000 0x0 0x100000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <212>;
|
||||
ti,ringacc = <&main_ringacc>;
|
||||
|
||||
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
|
||||
<0x0f>, /* TX_HCHAN */
|
||||
<0x10>; /* TX_UHCHAN */
|
||||
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
|
||||
<0x0b>, /* RX_HCHAN */
|
||||
<0x0c>; /* RX_UHCHAN */
|
||||
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
|
||||
};
|
||||
};
|
||||
|
||||
main_pmx0: pinmux@11c000 {
|
||||
@ -696,4 +735,232 @@
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
|
||||
mcasp0: mcasp@2b00000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b00000 0x0 0x2000>,
|
||||
<0x0 0x02b08000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 174 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp1: mcasp@2b10000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b10000 0x0 0x2000>,
|
||||
<0x0 0x02b18000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 175 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp2: mcasp@2b20000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b20000 0x0 0x2000>,
|
||||
<0x0 0x02b28000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 176 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp3: mcasp@2b30000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b30000 0x0 0x2000>,
|
||||
<0x0 0x02b38000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 177 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp4: mcasp@2b40000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b40000 0x0 0x2000>,
|
||||
<0x0 0x02b48000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 178 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp5: mcasp@2b50000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b50000 0x0 0x2000>,
|
||||
<0x0 0x02b58000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 179 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp6: mcasp@2b60000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b60000 0x0 0x2000>,
|
||||
<0x0 0x02b68000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 180 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp7: mcasp@2b70000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b70000 0x0 0x2000>,
|
||||
<0x0 0x02b78000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 181 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp8: mcasp@2b80000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b80000 0x0 0x2000>,
|
||||
<0x0 0x02b88000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 182 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp9: mcasp@2b90000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b90000 0x0 0x2000>,
|
||||
<0x0 0x02b98000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 183 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp10: mcasp@2ba0000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02ba0000 0x0 0x2000>,
|
||||
<0x0 0x02ba8000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 184 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp11: mcasp@2bb0000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02bb0000 0x0 0x2000>,
|
||||
<0x0 0x02bb8000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 185 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -225,4 +225,49 @@
|
||||
compatible = "ti,am3359-adc";
|
||||
};
|
||||
};
|
||||
|
||||
mcu_navss {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
ti,sci-dev-id = <232>;
|
||||
|
||||
mcu_ringacc: ringacc@2b800000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x0 0x2b800000 0x0 0x400000>,
|
||||
<0x0 0x2b000000 0x0 0x400000>,
|
||||
<0x0 0x28590000 0x0 0x100>,
|
||||
<0x0 0x2a500000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <235>;
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
};
|
||||
|
||||
mcu_udmap: dma-controller@285c0000 {
|
||||
compatible = "ti,j721e-navss-mcu-udmap";
|
||||
reg = <0x0 0x285c0000 0x0 0x100>,
|
||||
<0x0 0x2a800000 0x0 0x40000>,
|
||||
<0x0 0x2aa00000 0x0 0x40000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <236>;
|
||||
ti,ringacc = <&mcu_ringacc>;
|
||||
|
||||
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
|
||||
<0x0f>; /* TX_HCHAN */
|
||||
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
|
||||
<0x0b>; /* RX_HCHAN */
|
||||
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -130,7 +130,7 @@
|
||||
<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
|
||||
<0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
|
||||
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user