ARM: EXYNOS: add clock registers for exynos4x12-cpufreq
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -160,6 +160,15 @@
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#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
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#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)
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#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
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#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28
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#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
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#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0
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#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
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#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4
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#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
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#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8
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#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
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#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
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