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drm/i915: Enable per-lane DP drive settings for bxt/glk

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Now the bxt/glk PHY code is ready for per-lane drive settings
so enable it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240412175818.29217-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2024-04-12 20:58:18 +03:00
parent aeda5f4edb
commit d08184aa90
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/display/intel_dp_link_training.c
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@ -334,7 +334,7 @@ static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
DISPLAY_VER(i915) >= 11;
DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915);
}
/* 128b/132b */