drm/amdgpu/vcn: sriov support for vcn_v4_0_3
initialization table handshake with mmsch Signed-off-by: Samir Dhume <samir.dhume@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Samir Dhume
Alex Deucher
parent
44fd83e920
commit
d117fd2964
@ -31,6 +31,7 @@
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#include "soc15d.h"
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#include "soc15_hw_ip.h"
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#include "vcn_v2_0.h"
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#include "mmsch_v4_0_3.h"
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#include "vcn/vcn_4_0_3_offset.h"
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#include "vcn/vcn_4_0_3_sh_mask.h"
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@ -44,6 +45,7 @@
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#define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
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#define VCN1_VID_SOC_ADDRESS_3_0 0x48300
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static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
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static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
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static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
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static int vcn_v4_0_3_set_powergating_state(void *handle,
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@ -137,6 +139,12 @@ static int vcn_v4_0_3_sw_init(void *handle)
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amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
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}
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if (amdgpu_sriov_vf(adev)) {
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r = amdgpu_virt_alloc_mm_table(adev);
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if (r)
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return r;
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}
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
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adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
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@ -174,6 +182,9 @@ static int vcn_v4_0_3_sw_fini(void *handle)
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drm_dev_exit(idx);
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}
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if (amdgpu_sriov_vf(adev))
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amdgpu_virt_free_mm_table(adev);
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r = amdgpu_vcn_suspend(adev);
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if (r)
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return r;
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@ -196,33 +207,47 @@ static int vcn_v4_0_3_hw_init(void *handle)
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struct amdgpu_ring *ring;
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int i, r, vcn_inst;
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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vcn_inst = GET_INST(VCN, i);
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ring = &adev->vcn.inst[i].ring_enc[0];
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if (ring->use_doorbell) {
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adev->nbio.funcs->vcn_doorbell_range(
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adev, ring->use_doorbell,
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
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9 * vcn_inst,
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adev->vcn.inst[i].aid_id);
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WREG32_SOC15(
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VCN, GET_INST(VCN, ring->me),
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regVCN_RB1_DB_CTRL,
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ring->doorbell_index
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<< VCN_RB1_DB_CTRL__OFFSET__SHIFT |
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VCN_RB1_DB_CTRL__EN_MASK);
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/* Read DB_CTRL to flush the write DB_CTRL command. */
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RREG32_SOC15(
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VCN, GET_INST(VCN, ring->me),
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regVCN_RB1_DB_CTRL);
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}
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r = amdgpu_ring_test_helper(ring);
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if (amdgpu_sriov_vf(adev)) {
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r = vcn_v4_0_3_start_sriov(adev);
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if (r)
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goto done;
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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ring = &adev->vcn.inst[i].ring_enc[0];
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ring->wptr = 0;
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ring->wptr_old = 0;
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vcn_v4_0_3_unified_ring_set_wptr(ring);
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ring->sched.ready = true;
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}
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} else {
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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vcn_inst = GET_INST(VCN, i);
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ring = &adev->vcn.inst[i].ring_enc[0];
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if (ring->use_doorbell) {
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adev->nbio.funcs->vcn_doorbell_range(
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adev, ring->use_doorbell,
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
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9 * vcn_inst,
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adev->vcn.inst[i].aid_id);
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WREG32_SOC15(
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VCN, GET_INST(VCN, ring->me),
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regVCN_RB1_DB_CTRL,
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ring->doorbell_index
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<< VCN_RB1_DB_CTRL__OFFSET__SHIFT |
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VCN_RB1_DB_CTRL__EN_MASK);
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/* Read DB_CTRL to flush the write DB_CTRL command. */
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RREG32_SOC15(
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VCN, GET_INST(VCN, ring->me),
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regVCN_RB1_DB_CTRL);
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}
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r = amdgpu_ring_test_helper(ring);
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if (r)
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goto done;
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}
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}
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done:
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@ -820,6 +845,193 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
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return 0;
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}
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static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)
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{
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int i, vcn_inst;
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struct amdgpu_ring *ring_enc;
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uint64_t cache_addr;
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uint64_t rb_enc_addr;
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uint64_t ctx_addr;
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uint32_t param, resp, expected;
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uint32_t offset, cache_size;
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uint32_t tmp, timeout;
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struct amdgpu_mm_table *table = &adev->virt.mm_table;
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uint32_t *table_loc;
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uint32_t table_size;
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uint32_t size, size_dw;
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uint32_t init_status;
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uint32_t enabled_vcn;
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struct mmsch_v4_0_cmd_direct_write
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direct_wt = { {0} };
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struct mmsch_v4_0_cmd_direct_read_modify_write
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direct_rd_mod_wt = { {0} };
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struct mmsch_v4_0_cmd_end end = { {0} };
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struct mmsch_v4_0_3_init_header header;
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volatile struct amdgpu_vcn4_fw_shared *fw_shared;
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volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
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direct_wt.cmd_header.command_type =
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MMSCH_COMMAND__DIRECT_REG_WRITE;
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direct_rd_mod_wt.cmd_header.command_type =
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MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
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end.cmd_header.command_type = MMSCH_COMMAND__END;
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for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
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vcn_inst = GET_INST(VCN, i);
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memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header));
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header.version = MMSCH_VERSION;
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header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2;
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table_loc = (uint32_t *)table->cpu_addr;
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table_loc += header.total_size;
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table_size = 0;
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MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),
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~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
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cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
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offset = 0;
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_VCPU_CACHE_OFFSET0), 0);
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} else {
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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lower_32_bits(adev->vcn.inst[i].gpu_addr));
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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upper_32_bits(adev->vcn.inst[i].gpu_addr));
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offset = cache_size;
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_VCPU_CACHE_OFFSET0),
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AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
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}
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_VCPU_CACHE_SIZE0),
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cache_size);
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cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset;
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr));
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr));
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_VCPU_CACHE_OFFSET1), 0);
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE);
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cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset +
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AMDGPU_VCN_STACK_SIZE;
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr));
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr));
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_VCPU_CACHE_OFFSET2), 0);
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE);
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fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr;
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rb_setup = &fw_shared->rb_setup;
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ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0];
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ring_enc->wptr = 0;
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rb_enc_addr = ring_enc->gpu_addr;
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rb_setup->is_rb_enabled_flags |= RB_ENABLED;
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rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
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rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
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rb_setup->rb_size = ring_enc->ring_size / 4;
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fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
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lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
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upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
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MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
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regUVD_VCPU_NONCACHE_SIZE0),
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AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
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MMSCH_V4_0_INSERT_END();
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header.vcn0.init_status = 0;
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header.vcn0.table_offset = header.total_size;
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header.vcn0.table_size = table_size;
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header.total_size += table_size;
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/* Send init table to mmsch */
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size = sizeof(struct mmsch_v4_0_3_init_header);
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table_loc = (uint32_t *)table->cpu_addr;
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memcpy((void *)table_loc, &header, size);
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ctx_addr = table->gpu_addr;
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WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
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WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
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tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);
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tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
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tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
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WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp);
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size = header.total_size;
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WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size);
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WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0);
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param = 0x00000001;
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WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param);
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tmp = 0;
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timeout = 1000;
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resp = 0;
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expected = MMSCH_VF_MAILBOX_RESP__OK;
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while (resp != expected) {
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resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP);
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if (resp != 0)
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break;
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udelay(10);
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tmp = tmp + 10;
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if (tmp >= timeout) {
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DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
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" waiting for regMMSCH_VF_MAILBOX_RESP "\
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"(expected=0x%08x, readback=0x%08x)\n",
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tmp, expected, resp);
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return -EBUSY;
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}
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}
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enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;
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init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status;
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if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
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&& init_status != MMSCH_VF_ENGINE_STATUS__PASS) {
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DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
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"status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);
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}
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}
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return 0;
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}
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/**
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* vcn_v4_0_3_start - VCN start
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*
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