drm/i915/gt: Clear LRC image inline
When creating the initial LRC image, we also want to clear the MI_NOOPs and register values. Rather than use a blanket memset beforehand, apply the clears inline, close the context image and force inhibition of the uninitialised reminder. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200102131707.1463945-2-chris@chris-wilson.co.uk
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Chris Wilson
parent
6a505e644c
commit
d1813ca2bb
@ -488,9 +488,15 @@ lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
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return desc;
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}
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static u32 *set_offsets(u32 *regs,
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static inline unsigned int dword_in_page(void *addr)
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{
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return offset_in_page(addr) / sizeof(u32);
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}
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static void set_offsets(u32 *regs,
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const u8 *data,
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const struct intel_engine_cs *engine)
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const struct intel_engine_cs *engine,
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bool clear)
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#define NOP(x) (BIT(7) | (x))
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#define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6)))
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#define POSTED BIT(0)
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@ -498,7 +504,7 @@ static u32 *set_offsets(u32 *regs,
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#define REG16(x) \
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(((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \
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(((x) >> 2) & 0x7f)
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#define END() 0
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#define END(x) 0, (x)
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{
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const u32 base = engine->mmio_base;
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@ -506,7 +512,10 @@ static u32 *set_offsets(u32 *regs,
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u8 count, flags;
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if (*data & BIT(7)) { /* skip */
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regs += *data++ & ~BIT(7);
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count = *data++ & ~BIT(7);
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if (clear)
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memset32(regs, MI_NOOP, count);
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regs += count;
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continue;
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}
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@ -532,12 +541,25 @@ static u32 *set_offsets(u32 *regs,
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offset |= v & ~BIT(7);
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} while (v & BIT(7));
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*regs = base + (offset << 2);
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regs[0] = base + (offset << 2);
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if (clear)
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regs[1] = 0;
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regs += 2;
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} while (--count);
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}
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return regs;
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if (clear) {
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u8 count = *++data;
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/* Clear past the tail for HW access */
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GEM_BUG_ON(dword_in_page(regs) > count);
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memset32(regs, MI_NOOP, count - dword_in_page(regs));
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/* Close the batch; used mainly by live_lrc_layout() */
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*regs = MI_BATCH_BUFFER_END;
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if (INTEL_GEN(engine->i915) >= 10)
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*regs |= BIT(0);
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}
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}
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static const u8 gen8_xcs_offsets[] = {
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@ -572,7 +594,7 @@ static const u8 gen8_xcs_offsets[] = {
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REG16(0x200),
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REG(0x028),
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END(),
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END(80)
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};
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static const u8 gen9_xcs_offsets[] = {
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@ -656,7 +678,7 @@ static const u8 gen9_xcs_offsets[] = {
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REG16(0x67c),
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REG(0x068),
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END(),
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END(176)
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};
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static const u8 gen12_xcs_offsets[] = {
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@ -688,7 +710,7 @@ static const u8 gen12_xcs_offsets[] = {
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REG16(0x274),
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REG16(0x270),
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END(),
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END(80)
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};
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static const u8 gen8_rcs_offsets[] = {
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@ -725,7 +747,7 @@ static const u8 gen8_rcs_offsets[] = {
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LRI(1, 0),
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REG(0x0c8),
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END(),
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END(80)
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};
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static const u8 gen9_rcs_offsets[] = {
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@ -809,7 +831,7 @@ static const u8 gen9_rcs_offsets[] = {
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REG16(0x67c),
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REG(0x68),
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END()
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END(176)
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};
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static const u8 gen11_rcs_offsets[] = {
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@ -850,7 +872,7 @@ static const u8 gen11_rcs_offsets[] = {
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LRI(1, 0),
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REG(0x0c8),
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END(),
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END(80)
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};
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static const u8 gen12_rcs_offsets[] = {
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@ -891,7 +913,7 @@ static const u8 gen12_rcs_offsets[] = {
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LRI(1, 0),
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REG(0x0c8),
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END(),
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END(80)
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};
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#undef END
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@ -1529,7 +1551,7 @@ static bool can_merge_rq(const struct i915_request *prev,
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static void virtual_update_register_offsets(u32 *regs,
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struct intel_engine_cs *engine)
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{
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set_offsets(regs, reg_offsets(engine), engine);
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set_offsets(regs, reg_offsets(engine), engine, false);
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}
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static bool virtual_matches(const struct virtual_engine *ve,
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@ -4043,15 +4065,19 @@ static u32 intel_lr_indirect_ctx_offset(const struct intel_engine_cs *engine)
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static void init_common_reg_state(u32 * const regs,
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const struct intel_engine_cs *engine,
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const struct intel_ring *ring)
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const struct intel_ring *ring,
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bool inhibit)
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{
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regs[CTX_CONTEXT_CONTROL] =
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_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
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_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
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u32 ctl;
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ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
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ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
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if (inhibit)
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ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
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if (INTEL_GEN(engine->i915) < 11)
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regs[CTX_CONTEXT_CONTROL] |=
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_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
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CTX_CTRL_RS_CTX_ENABLE);
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ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
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CTX_CTRL_RS_CTX_ENABLE);
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regs[CTX_CONTEXT_CONTROL] = ctl;
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regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
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}
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@ -4109,7 +4135,7 @@ static void execlists_init_reg_state(u32 *regs,
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const struct intel_context *ce,
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const struct intel_engine_cs *engine,
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const struct intel_ring *ring,
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bool close)
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bool inhibit)
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{
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/*
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* A context is actually a big batch buffer with several
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@ -4121,15 +4147,9 @@ static void execlists_init_reg_state(u32 *regs,
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*
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* Must keep consistent with virtual_update_register_offsets().
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*/
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u32 *bbe = set_offsets(regs, reg_offsets(engine), engine);
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set_offsets(regs, reg_offsets(engine), engine, inhibit);
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if (close) { /* Close the batch; used mainly by live_lrc_layout() */
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*bbe = MI_BATCH_BUFFER_END;
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if (INTEL_GEN(engine->i915) >= 10)
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*bbe |= BIT(0);
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}
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init_common_reg_state(regs, engine, ring);
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init_common_reg_state(regs, engine, ring, inhibit);
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init_ppgtt_reg_state(regs, vm_alias(ce->vm));
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init_wa_bb_reg_state(regs, engine,
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@ -4148,7 +4168,6 @@ populate_lr_context(struct intel_context *ce,
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{
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bool inhibit = true;
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void *vaddr;
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u32 *regs;
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int ret;
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vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
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@ -4178,11 +4197,8 @@ populate_lr_context(struct intel_context *ce,
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/* The second page of the context object contains some fields which must
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* be set up prior to the first execution. */
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regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
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execlists_init_reg_state(regs, ce, engine, ring, inhibit);
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if (inhibit)
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regs[CTX_CONTEXT_CONTROL] |=
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_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
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execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE,
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ce, engine, ring, inhibit);
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ret = 0;
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err_unpin_ctx:
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@ -3362,7 +3362,7 @@ static int live_lrc_layout(void *arg)
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struct intel_gt *gt = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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u32 *mem;
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u32 *lrc;
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int err;
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/*
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@ -3370,13 +3370,13 @@ static int live_lrc_layout(void *arg)
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* match the layout saved by HW.
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*/
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mem = kmalloc(PAGE_SIZE, GFP_KERNEL);
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if (!mem)
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lrc = kmalloc(PAGE_SIZE, GFP_KERNEL);
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if (!lrc)
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return -ENOMEM;
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err = 0;
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for_each_engine(engine, gt, id) {
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u32 *hw, *lrc;
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u32 *hw;
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int dw;
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if (!engine->default_state)
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@ -3390,8 +3390,7 @@ static int live_lrc_layout(void *arg)
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}
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hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
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lrc = memset(mem, 0, PAGE_SIZE);
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execlists_init_reg_state(lrc,
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execlists_init_reg_state(memset(lrc, POISON_INUSE, PAGE_SIZE),
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engine->kernel_context,
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engine,
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engine->kernel_context->ring,
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@ -3461,7 +3460,7 @@ static int live_lrc_layout(void *arg)
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break;
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}
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kfree(mem);
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kfree(lrc);
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return err;
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}
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