cxl/pci: Disable root port interrupts in RCH mode
The RCH root port contains root command AER registers that should not be enabled.[1] Disable these to prevent root port interrupts. [1] CXL 3.0 - 12.2.1.1 RCH Downstream Port-detected Errors Signed-off-by: Terry Bowman <terry.bowman@amd.com> Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20231018171713.1883517-17-rrichter@amd.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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Dan Williams
parent
6ac07883db
commit
d1a9def33d
@@ -763,6 +763,35 @@ static void cxl_dport_map_regs(struct cxl_dport *dport)
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cxl_dport_map_rch_aer(dport);
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cxl_dport_map_rch_aer(dport);
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}
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}
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static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
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{
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void __iomem *aer_base = dport->regs.dport_aer;
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struct pci_host_bridge *bridge;
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u32 aer_cmd_mask, aer_cmd;
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if (!aer_base)
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return;
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bridge = to_pci_host_bridge(dport->dport_dev);
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/*
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* Disable RCH root port command interrupts.
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* CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors
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*
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* This sequence may not be necessary. CXL spec states disabling
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* the root cmd register's interrupts is required. But, PCI spec
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* shows these are disabled by default on reset.
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*/
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if (bridge->native_cxl_error) {
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aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
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PCI_ERR_ROOT_CMD_NONFATAL_EN |
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PCI_ERR_ROOT_CMD_FATAL_EN);
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aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND);
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aer_cmd &= ~aer_cmd_mask;
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writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
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}
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}
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void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
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void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
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{
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{
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struct device *dport_dev = dport->dport_dev;
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struct device *dport_dev = dport->dport_dev;
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@@ -774,6 +803,9 @@ void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
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dport->reg_map.host = host;
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dport->reg_map.host = host;
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cxl_dport_map_regs(dport);
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cxl_dport_map_regs(dport);
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if (dport->rch)
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cxl_disable_rch_root_ints(dport);
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}
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}
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EXPORT_SYMBOL_NS_GPL(cxl_setup_parent_dport, CXL);
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EXPORT_SYMBOL_NS_GPL(cxl_setup_parent_dport, CXL);
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