pinctrl: tegra: Add support to display pin function
The current function for a given pin is not displayed via the debugfs. Add support to display the current function that is set for each pin. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230714113547.15384-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -96,6 +96,7 @@ static const struct cfg_param {
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{"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
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{"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
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{"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
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{"nvidia,function", TEGRA_PINCONF_PARAM_FUNCTION},
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};
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static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
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@ -470,6 +471,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
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*bit = g->drvtype_bit;
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*width = 2;
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break;
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case TEGRA_PINCONF_PARAM_FUNCTION:
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*bank = g->mux_bank;
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*reg = g->mux_reg;
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*bit = g->mux_bit;
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*width = 2;
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break;
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default:
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dev_err(pmx->dev, "Invalid config param %04x\n", param);
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return -ENOTSUPP;
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@ -633,8 +640,16 @@ static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
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val >>= bit;
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val &= (1 << width) - 1;
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seq_printf(s, "\n\t%s=%u",
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strip_prefix(cfg_params[i].property), val);
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if (cfg_params[i].param == TEGRA_PINCONF_PARAM_FUNCTION) {
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u8 idx = pmx->soc->groups[group].funcs[val];
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seq_printf(s, "\n\t%s=%s",
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strip_prefix(cfg_params[i].property),
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pmx->functions[idx].name);
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} else {
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seq_printf(s, "\n\t%s=%u",
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strip_prefix(cfg_params[i].property), val);
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}
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}
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}
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@ -54,6 +54,8 @@ enum tegra_pinconf_param {
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TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
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/* argument: Integer, range is HW-dependant */
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TEGRA_PINCONF_PARAM_DRIVE_TYPE,
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/* argument: pinmux settings */
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TEGRA_PINCONF_PARAM_FUNCTION,
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};
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enum tegra_pinconf_pull {
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