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PCI: microchip: Enable event handlers to access bridge and control pointers

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Minor re-organisation so that event handlers can access both a pointer
to the bridge area of the PCIe Root Port and the control area of the PCIe
Root Port.

Link: https://lore.kernel.org/r/20230728131401.1615724-5-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Daire McNamara 2023-07-28 14:13:58 +01:00 committed by Lorenzo Pieralisi
parent 4d6bf4c495
commit d1d6a0c9e7
1 changed files with 16 additions and 15 deletions
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31
drivers/pci/controller/pcie-microchip-host.c
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@ -654,9 +654,10 @@ static inline u32 reg_to_event(u32 reg, struct event_map field)
return (reg & field.reg_mask) ? BIT(field.event_bit) : 0;
}
static u32 pcie_events(void __iomem *addr)
static u32 pcie_events(struct mc_pcie *port)
{
u32 reg = readl_relaxed(addr);
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT);
u32 val = 0;
int i;
@ -666,9 +667,10 @@ static u32 pcie_events(void __iomem *addr)
return val;
}
static u32 sec_errors(void __iomem *addr)
static u32 sec_errors(struct mc_pcie *port)
{
u32 reg = readl_relaxed(addr);
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT);
u32 val = 0;
int i;
@ -678,9 +680,10 @@ static u32 sec_errors(void __iomem *addr)
return val;
}
static u32 ded_errors(void __iomem *addr)
static u32 ded_errors(struct mc_pcie *port)
{
u32 reg = readl_relaxed(addr);
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT);
u32 val = 0;
int i;
@ -690,9 +693,10 @@ static u32 ded_errors(void __iomem *addr)
return val;
}
static u32 local_events(void __iomem *addr)
static u32 local_events(struct mc_pcie *port)
{
u32 reg = readl_relaxed(addr);
void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
u32 val = 0;
int i;
@ -704,15 +708,12 @@ static u32 local_events(void __iomem *addr)
static u32 get_events(struct mc_pcie *port)
{
void __iomem *bridge_base_addr =
port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
u32 events = 0;
events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT);
events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT);
events |= ded_errors(ctrl_base_addr + DED_ERROR_INT);
events |= local_events(bridge_base_addr + ISTATUS_LOCAL);
events |= pcie_events(port);
events |= sec_errors(port);
events |= ded_errors(port);
events |= local_events(port);
return events;
}