Merge tag 'drm-intel-next-2022-08-29' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
drm/i915 feature pull for v6.1: Features and functionality: - Early Meteorlake (MTL) enabling (José, Radhakrishna, Clint, Imre, Vandita, Ville, Jani) - Support more HDMI pixel clock frequencies on DG2 (Clint) - Sanity check PCI BARs (Piotr Piórkowski) - Enable DC5 on DG2 (Anusha) - DG2 DMC firmware version bump to v2.07 (Madhumitha) - New ADL-S PCI ID (José) Refactoring and cleanups: - Add display sub-struct to struct drm_i915_private (Jani) - Add initial runtime info to device info (Jani) - Split out HDCP and backlight registers to separate files (Jani) Fixes: - Skip wm/ddb readout for disabled pipes (Ville) - HDMI port timing quirk for GLK ECS Liva Q2 (Diego Santa Cruz) - Fix bw init null pointer dereference (Łukasz Bartosik) - Disable PPS power hook for DP AUX backlight (Jouni) - Avoid warnings on registering multiple backlight devices (Arun) - Fix dual-link DSI backlight and CABC ports for display 11+ (Jani) - Fix Type-C PHY ownership programming in HDMI legacy mode (Imre) - Fix unclaimed register access while loading PIPEDMC-C/D (Imre) - Bump up CDCLK for DG2 (Stan) - Prune modes that require HDMI 2.1 FRL (Ankit) - Disable FBC when PSR1 is enabled in display 12-13 (Matt) - Fix TGL+ HDMI transcoder clock and DDI BUF disable order (Imre) - Disable PSR before disable pipe (José) - Disable DMC handlers during firmware loading/disabling on display 12+ (Imre) - Disable clock gating for PIPEDMC-A/B as a workaround (Imre) Merges: - Two drm-next backmerges (Rodrigo, Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87k06rfaku.fsf@intel.com
This commit is contained in:
commit
d1e2d6b78f
@ -1169,7 +1169,7 @@ intel_dp_hotplug(struct intel_encoder *encoder,
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static bool ibx_digital_port_connected(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
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u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
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return intel_de_read(dev_priv, SDEISR) & bit;
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}
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@ -1223,7 +1223,7 @@ static bool gm45_digital_port_connected(struct intel_encoder *encoder)
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static bool ilk_digital_port_connected(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
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u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
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return intel_de_read(dev_priv, DEISR) & bit;
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}
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@ -33,6 +33,7 @@
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#include "icl_dsi_regs.h"
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#include "intel_atomic.h"
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#include "intel_backlight.h"
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#include "intel_backlight_regs.h"
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#include "intel_combo_phy.h"
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#include "intel_combo_phy_regs.h"
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#include "intel_connector.h"
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@ -641,13 +642,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
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u32 tmp;
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enum phy phy;
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mutex_lock(&dev_priv->dpll.lock);
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mutex_lock(&dev_priv->display.dpll.lock);
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tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
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for_each_dsi_phy(phy, intel_dsi->phys)
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tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
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intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
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mutex_unlock(&dev_priv->dpll.lock);
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mutex_unlock(&dev_priv->display.dpll.lock);
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}
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static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
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@ -657,13 +658,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
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u32 tmp;
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enum phy phy;
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mutex_lock(&dev_priv->dpll.lock);
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mutex_lock(&dev_priv->display.dpll.lock);
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tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
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for_each_dsi_phy(phy, intel_dsi->phys)
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tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
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intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
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mutex_unlock(&dev_priv->dpll.lock);
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mutex_unlock(&dev_priv->display.dpll.lock);
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}
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static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
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@ -693,7 +694,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
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enum phy phy;
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u32 val;
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mutex_lock(&dev_priv->dpll.lock);
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mutex_lock(&dev_priv->display.dpll.lock);
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val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
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for_each_dsi_phy(phy, intel_dsi->phys) {
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@ -709,7 +710,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
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intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
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mutex_unlock(&dev_priv->dpll.lock);
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mutex_unlock(&dev_priv->display.dpll.lock);
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}
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static void
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@ -2070,8 +2071,11 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
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else
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intel_dsi->ports = BIT(port);
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intel_dsi->dcs_backlight_ports = intel_connector->panel.vbt.dsi.bl_ports;
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intel_dsi->dcs_cabc_ports = intel_connector->panel.vbt.dsi.cabc_ports;
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if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
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intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
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if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
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intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
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for_each_dsi_port(port, intel_dsi->ports) {
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struct intel_dsi_host *host;
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@ -393,7 +393,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct i915_audio_component *acomp = dev_priv->audio.component;
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struct i915_audio_component *acomp = dev_priv->display.audio.component;
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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enum port port = encoder->port;
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const struct dp_aud_n_m *nm;
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@ -441,7 +441,7 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct i915_audio_component *acomp = dev_priv->audio.component;
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struct i915_audio_component *acomp = dev_priv->display.audio.component;
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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enum port port = encoder->port;
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int n, rate;
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@ -496,7 +496,7 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder,
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enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
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u32 tmp;
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mutex_lock(&dev_priv->audio.mutex);
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mutex_lock(&dev_priv->display.audio.mutex);
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/* Disable timestamps */
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tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
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@ -514,7 +514,7 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder,
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tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
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intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
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mutex_unlock(&dev_priv->audio.mutex);
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mutex_unlock(&dev_priv->display.audio.mutex);
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}
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static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
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@ -639,7 +639,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
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u32 tmp;
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int len, i;
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mutex_lock(&dev_priv->audio.mutex);
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mutex_lock(&dev_priv->display.audio.mutex);
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/* Enable Audio WA for 4k DSC usecases */
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
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@ -677,7 +677,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
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/* Enable timestamps */
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hsw_audio_config_update(encoder, crtc_state);
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mutex_unlock(&dev_priv->audio.mutex);
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mutex_unlock(&dev_priv->display.audio.mutex);
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}
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static void ilk_audio_codec_disable(struct intel_encoder *encoder,
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@ -814,7 +814,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
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const struct drm_connector_state *conn_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct i915_audio_component *acomp = dev_priv->audio.component;
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struct i915_audio_component *acomp = dev_priv->display.audio.component;
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_connector *connector = conn_state->connector;
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const struct drm_display_mode *adjusted_mode =
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@ -838,17 +838,17 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
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connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
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if (dev_priv->audio.funcs)
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dev_priv->audio.funcs->audio_codec_enable(encoder,
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crtc_state,
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conn_state);
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if (dev_priv->display.funcs.audio)
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dev_priv->display.funcs.audio->audio_codec_enable(encoder,
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crtc_state,
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conn_state);
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mutex_lock(&dev_priv->audio.mutex);
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mutex_lock(&dev_priv->display.audio.mutex);
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encoder->audio_connector = connector;
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/* referred in audio callbacks */
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dev_priv->audio.encoder_map[pipe] = encoder;
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mutex_unlock(&dev_priv->audio.mutex);
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dev_priv->display.audio.encoder_map[pipe] = encoder;
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mutex_unlock(&dev_priv->display.audio.mutex);
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if (acomp && acomp->base.audio_ops &&
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acomp->base.audio_ops->pin_eld_notify) {
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@ -878,7 +878,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
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const struct drm_connector_state *old_conn_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct i915_audio_component *acomp = dev_priv->audio.component;
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struct i915_audio_component *acomp = dev_priv->display.audio.component;
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struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
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struct drm_connector *connector = old_conn_state->connector;
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enum port port = encoder->port;
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@ -891,15 +891,15 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
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connector->base.id, connector->name,
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encoder->base.base.id, encoder->base.name, pipe_name(pipe));
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if (dev_priv->audio.funcs)
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dev_priv->audio.funcs->audio_codec_disable(encoder,
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old_crtc_state,
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old_conn_state);
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if (dev_priv->display.funcs.audio)
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dev_priv->display.funcs.audio->audio_codec_disable(encoder,
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old_crtc_state,
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old_conn_state);
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mutex_lock(&dev_priv->audio.mutex);
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mutex_lock(&dev_priv->display.audio.mutex);
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encoder->audio_connector = NULL;
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dev_priv->audio.encoder_map[pipe] = NULL;
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mutex_unlock(&dev_priv->audio.mutex);
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dev_priv->display.audio.encoder_map[pipe] = NULL;
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mutex_unlock(&dev_priv->display.audio.mutex);
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if (acomp && acomp->base.audio_ops &&
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acomp->base.audio_ops->pin_eld_notify) {
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@ -935,13 +935,13 @@ static const struct intel_audio_funcs hsw_audio_funcs = {
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void intel_audio_hooks_init(struct drm_i915_private *dev_priv)
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{
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if (IS_G4X(dev_priv)) {
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dev_priv->audio.funcs = &g4x_audio_funcs;
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dev_priv->display.funcs.audio = &g4x_audio_funcs;
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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dev_priv->audio.funcs = &ilk_audio_funcs;
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dev_priv->display.funcs.audio = &ilk_audio_funcs;
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} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
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dev_priv->audio.funcs = &hsw_audio_funcs;
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dev_priv->display.funcs.audio = &hsw_audio_funcs;
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} else if (HAS_PCH_SPLIT(dev_priv)) {
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dev_priv->audio.funcs = &ilk_audio_funcs;
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dev_priv->display.funcs.audio = &ilk_audio_funcs;
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}
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}
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@ -1046,13 +1046,13 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
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ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK);
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if (dev_priv->audio.power_refcount++ == 0) {
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if (dev_priv->display.audio.power_refcount++ == 0) {
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if (DISPLAY_VER(dev_priv) >= 9) {
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intel_de_write(dev_priv, AUD_FREQ_CNTRL,
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dev_priv->audio.freq_cntrl);
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dev_priv->display.audio.freq_cntrl);
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drm_dbg_kms(&dev_priv->drm,
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"restored AUD_FREQ_CNTRL to 0x%x\n",
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dev_priv->audio.freq_cntrl);
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dev_priv->display.audio.freq_cntrl);
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}
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/* Force CDCLK to 2*BCLK as long as we need audio powered. */
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@ -1073,7 +1073,7 @@ static void i915_audio_component_put_power(struct device *kdev,
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struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
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/* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
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if (--dev_priv->audio.power_refcount == 0)
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if (--dev_priv->display.audio.power_refcount == 0)
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if (IS_GEMINILAKE(dev_priv))
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glk_force_audio_cdclk(dev_priv, false);
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@ -1140,10 +1140,10 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
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/* MST */
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if (pipe >= 0) {
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if (drm_WARN_ON(&dev_priv->drm,
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pipe >= ARRAY_SIZE(dev_priv->audio.encoder_map)))
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pipe >= ARRAY_SIZE(dev_priv->display.audio.encoder_map)))
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return NULL;
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encoder = dev_priv->audio.encoder_map[pipe];
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encoder = dev_priv->display.audio.encoder_map[pipe];
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/*
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* when bootup, audio driver may not know it is
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* MST or not. So it will poll all the port & pipe
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@ -1159,7 +1159,7 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
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return NULL;
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for_each_pipe(dev_priv, pipe) {
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encoder = dev_priv->audio.encoder_map[pipe];
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encoder = dev_priv->display.audio.encoder_map[pipe];
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if (encoder == NULL)
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continue;
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@ -1177,7 +1177,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
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int pipe, int rate)
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{
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struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
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struct i915_audio_component *acomp = dev_priv->audio.component;
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struct i915_audio_component *acomp = dev_priv->display.audio.component;
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struct intel_encoder *encoder;
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struct intel_crtc *crtc;
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unsigned long cookie;
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@ -1187,7 +1187,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
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return 0;
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cookie = i915_audio_component_get_power(kdev);
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mutex_lock(&dev_priv->audio.mutex);
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mutex_lock(&dev_priv->display.audio.mutex);
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/* 1. get the pipe */
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encoder = get_saved_enc(dev_priv, port, pipe);
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@ -1206,7 +1206,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
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hsw_audio_config_update(encoder, crtc->config);
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unlock:
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mutex_unlock(&dev_priv->audio.mutex);
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mutex_unlock(&dev_priv->display.audio.mutex);
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i915_audio_component_put_power(kdev, cookie);
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return err;
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}
|
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@ -1220,13 +1220,13 @@ static int i915_audio_component_get_eld(struct device *kdev, int port,
|
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const u8 *eld;
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int ret = -EINVAL;
|
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|
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mutex_lock(&dev_priv->audio.mutex);
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mutex_lock(&dev_priv->display.audio.mutex);
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intel_encoder = get_saved_enc(dev_priv, port, pipe);
|
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if (!intel_encoder) {
|
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drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
|
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port_name(port));
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mutex_unlock(&dev_priv->audio.mutex);
|
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mutex_unlock(&dev_priv->display.audio.mutex);
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return ret;
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}
|
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|
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@ -1238,7 +1238,7 @@ static int i915_audio_component_get_eld(struct device *kdev, int port,
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memcpy(buf, eld, min(max_bytes, ret));
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}
|
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|
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mutex_unlock(&dev_priv->audio.mutex);
|
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mutex_unlock(&dev_priv->display.audio.mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -1273,7 +1273,7 @@ static int i915_audio_component_bind(struct device *i915_kdev,
|
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BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
|
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for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
|
||||
acomp->aud_sample_rate[i] = 0;
|
||||
dev_priv->audio.component = acomp;
|
||||
dev_priv->display.audio.component = acomp;
|
||||
drm_modeset_unlock_all(&dev_priv->drm);
|
||||
|
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return 0;
|
||||
@ -1288,14 +1288,14 @@ static void i915_audio_component_unbind(struct device *i915_kdev,
|
||||
drm_modeset_lock_all(&dev_priv->drm);
|
||||
acomp->base.ops = NULL;
|
||||
acomp->base.dev = NULL;
|
||||
dev_priv->audio.component = NULL;
|
||||
dev_priv->display.audio.component = NULL;
|
||||
drm_modeset_unlock_all(&dev_priv->drm);
|
||||
|
||||
device_link_remove(hda_kdev, i915_kdev);
|
||||
|
||||
if (dev_priv->audio.power_refcount)
|
||||
if (dev_priv->display.audio.power_refcount)
|
||||
drm_err(&dev_priv->drm, "audio power refcount %d after unbind\n",
|
||||
dev_priv->audio.power_refcount);
|
||||
dev_priv->display.audio.power_refcount);
|
||||
}
|
||||
|
||||
static const struct component_ops i915_audio_component_bind_ops = {
|
||||
@ -1359,13 +1359,13 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv)
|
||||
drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n",
|
||||
aud_freq, aud_freq_init);
|
||||
|
||||
dev_priv->audio.freq_cntrl = aud_freq;
|
||||
dev_priv->display.audio.freq_cntrl = aud_freq;
|
||||
}
|
||||
|
||||
/* init with current cdclk */
|
||||
intel_audio_cdclk_change_post(dev_priv);
|
||||
|
||||
dev_priv->audio.component_registered = true;
|
||||
dev_priv->display.audio.component_registered = true;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1377,11 +1377,11 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv)
|
||||
*/
|
||||
static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if (!dev_priv->audio.component_registered)
|
||||
if (!dev_priv->display.audio.component_registered)
|
||||
return;
|
||||
|
||||
component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
|
||||
dev_priv->audio.component_registered = false;
|
||||
dev_priv->display.audio.component_registered = false;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1403,7 +1403,7 @@ void intel_audio_init(struct drm_i915_private *dev_priv)
|
||||
*/
|
||||
void intel_audio_deinit(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if ((dev_priv)->audio.lpe.platdev != NULL)
|
||||
if (dev_priv->display.audio.lpe.platdev != NULL)
|
||||
intel_lpe_audio_teardown(dev_priv);
|
||||
else
|
||||
i915_audio_component_cleanup(dev_priv);
|
||||
|
@ -9,6 +9,7 @@
|
||||
#include <linux/string_helpers.h>
|
||||
|
||||
#include "intel_backlight.h"
|
||||
#include "intel_backlight_regs.h"
|
||||
#include "intel_connector.h"
|
||||
#include "intel_de.h"
|
||||
#include "intel_display_types.h"
|
||||
@ -16,6 +17,7 @@
|
||||
#include "intel_dsi_dcs_backlight.h"
|
||||
#include "intel_panel.h"
|
||||
#include "intel_pci_config.h"
|
||||
#include "intel_pps.h"
|
||||
|
||||
/**
|
||||
* scale - scale values from one range to another
|
||||
@ -971,26 +973,24 @@ int intel_backlight_device_register(struct intel_connector *connector)
|
||||
if (!name)
|
||||
return -ENOMEM;
|
||||
|
||||
bd = backlight_device_register(name, connector->base.kdev, connector,
|
||||
&intel_backlight_device_ops, &props);
|
||||
|
||||
/*
|
||||
* Using the same name independent of the drm device or connector
|
||||
* prevents registration of multiple backlight devices in the
|
||||
* driver. However, we need to use the default name for backward
|
||||
* compatibility. Use unique names for subsequent backlight devices as a
|
||||
* fallback when the default name already exists.
|
||||
*/
|
||||
if (IS_ERR(bd) && PTR_ERR(bd) == -EEXIST) {
|
||||
bd = backlight_device_get_by_name(name);
|
||||
if (bd) {
|
||||
put_device(&bd->dev);
|
||||
/*
|
||||
* Using the same name independent of the drm device or connector
|
||||
* prevents registration of multiple backlight devices in the
|
||||
* driver. However, we need to use the default name for backward
|
||||
* compatibility. Use unique names for subsequent backlight devices as a
|
||||
* fallback when the default name already exists.
|
||||
*/
|
||||
kfree(name);
|
||||
name = kasprintf(GFP_KERNEL, "card%d-%s-backlight",
|
||||
i915->drm.primary->index, connector->base.name);
|
||||
if (!name)
|
||||
return -ENOMEM;
|
||||
|
||||
bd = backlight_device_register(name, connector->base.kdev, connector,
|
||||
&intel_backlight_device_ops, &props);
|
||||
}
|
||||
bd = backlight_device_register(name, connector->base.kdev, connector,
|
||||
&intel_backlight_device_ops, &props);
|
||||
|
||||
if (IS_ERR(bd)) {
|
||||
drm_err(&i915->drm,
|
||||
@ -1773,9 +1773,13 @@ void intel_backlight_init_funcs(struct intel_panel *panel)
|
||||
panel->backlight.pwm_funcs = &i9xx_pwm_funcs;
|
||||
}
|
||||
|
||||
if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
|
||||
intel_dp_aux_init_backlight_funcs(connector) == 0)
|
||||
return;
|
||||
if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
|
||||
if (intel_dp_aux_init_backlight_funcs(connector) == 0)
|
||||
return;
|
||||
|
||||
if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
|
||||
connector->panel.backlight.power = intel_pps_backlight_power;
|
||||
}
|
||||
|
||||
/* We're using a standard PWM backlight interface */
|
||||
panel->backlight.funcs = &pwm_bl_funcs;
|
||||
|
124
drivers/gpu/drm/i915/display/intel_backlight_regs.h
Normal file
124
drivers/gpu/drm/i915/display/intel_backlight_regs.h
Normal file
@ -0,0 +1,124 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2022 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __INTEL_BACKLIGHT_REGS_H__
|
||||
#define __INTEL_BACKLIGHT_REGS_H__
|
||||
|
||||
#include "i915_reg_defs.h"
|
||||
|
||||
#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
|
||||
#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
|
||||
#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
|
||||
_VLV_BLC_PWM_CTL2_B)
|
||||
|
||||
#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
|
||||
#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
|
||||
#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
|
||||
_VLV_BLC_PWM_CTL_B)
|
||||
|
||||
#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
|
||||
#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
|
||||
#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
|
||||
_VLV_BLC_HIST_CTL_B)
|
||||
|
||||
/* Backlight control */
|
||||
#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
|
||||
#define BLM_PWM_ENABLE (1 << 31)
|
||||
#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
|
||||
#define BLM_PIPE_SELECT (1 << 29)
|
||||
#define BLM_PIPE_SELECT_IVB (3 << 29)
|
||||
#define BLM_PIPE_A (0 << 29)
|
||||
#define BLM_PIPE_B (1 << 29)
|
||||
#define BLM_PIPE_C (2 << 29) /* ivb + */
|
||||
#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
|
||||
#define BLM_TRANSCODER_B BLM_PIPE_B
|
||||
#define BLM_TRANSCODER_C BLM_PIPE_C
|
||||
#define BLM_TRANSCODER_EDP (3 << 29)
|
||||
#define BLM_PIPE(pipe) ((pipe) << 29)
|
||||
#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
|
||||
#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
|
||||
#define BLM_PHASE_IN_ENABLE (1 << 25)
|
||||
#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
|
||||
#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
|
||||
#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
|
||||
#define BLM_PHASE_IN_COUNT_SHIFT (8)
|
||||
#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
|
||||
#define BLM_PHASE_IN_INCR_SHIFT (0)
|
||||
#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
|
||||
#define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
|
||||
/*
|
||||
* This is the most significant 15 bits of the number of backlight cycles in a
|
||||
* complete cycle of the modulated backlight control.
|
||||
*
|
||||
* The actual value is this field multiplied by two.
|
||||
*/
|
||||
#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
|
||||
#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
|
||||
#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
|
||||
/*
|
||||
* This is the number of cycles out of the backlight modulation cycle for which
|
||||
* the backlight is on.
|
||||
*
|
||||
* This field must be no greater than the number of cycles in the complete
|
||||
* backlight modulation cycle.
|
||||
*/
|
||||
#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
|
||||
#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
|
||||
#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
|
||||
#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
|
||||
|
||||
#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
|
||||
#define BLM_HISTOGRAM_ENABLE (1 << 31)
|
||||
|
||||
/* New registers for PCH-split platforms. Safe where new bits show up, the
|
||||
* register layout machtes with gen4 BLC_PWM_CTL[12]. */
|
||||
#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
|
||||
#define BLC_PWM_CPU_CTL _MMIO(0x48254)
|
||||
|
||||
#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
|
||||
|
||||
/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
|
||||
* like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
|
||||
#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
|
||||
#define BLM_PCH_PWM_ENABLE (1 << 31)
|
||||
#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
|
||||
#define BLM_PCH_POLARITY (1 << 29)
|
||||
#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
|
||||
|
||||
/* BXT backlight register definition. */
|
||||
#define _BXT_BLC_PWM_CTL1 0xC8250
|
||||
#define BXT_BLC_PWM_ENABLE (1 << 31)
|
||||
#define BXT_BLC_PWM_POLARITY (1 << 29)
|
||||
#define _BXT_BLC_PWM_FREQ1 0xC8254
|
||||
#define _BXT_BLC_PWM_DUTY1 0xC8258
|
||||
|
||||
#define _BXT_BLC_PWM_CTL2 0xC8350
|
||||
#define _BXT_BLC_PWM_FREQ2 0xC8354
|
||||
#define _BXT_BLC_PWM_DUTY2 0xC8358
|
||||
|
||||
#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
|
||||
_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
|
||||
#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
|
||||
_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
|
||||
#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
|
||||
_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
|
||||
|
||||
/* Utility pin */
|
||||
#define UTIL_PIN_CTL _MMIO(0x48400)
|
||||
#define UTIL_PIN_ENABLE (1 << 31)
|
||||
#define UTIL_PIN_PIPE_MASK (3 << 29)
|
||||
#define UTIL_PIN_PIPE(x) ((x) << 29)
|
||||
#define UTIL_PIN_MODE_MASK (0xf << 24)
|
||||
#define UTIL_PIN_MODE_DATA (0 << 24)
|
||||
#define UTIL_PIN_MODE_PWM (1 << 24)
|
||||
#define UTIL_PIN_MODE_VBLANK (4 << 24)
|
||||
#define UTIL_PIN_MODE_VSYNC (5 << 24)
|
||||
#define UTIL_PIN_MODE_EYE_LEVEL (8 << 24)
|
||||
#define UTIL_PIN_OUTPUT_DATA (1 << 23)
|
||||
#define UTIL_PIN_POLARITY (1 << 22)
|
||||
#define UTIL_PIN_DIRECTION_INPUT (1 << 19)
|
||||
#define UTIL_PIN_INPUT_DATA (1 << 16)
|
||||
|
||||
#endif /* __INTEL_BACKLIGHT_REGS_H__ */
|
@ -1596,6 +1596,8 @@ static void parse_dsi_backlight_ports(struct drm_i915_private *i915,
|
||||
struct intel_panel *panel,
|
||||
enum port port)
|
||||
{
|
||||
enum port port_bc = DISPLAY_VER(i915) >= 11 ? PORT_B : PORT_C;
|
||||
|
||||
if (!panel->vbt.dsi.config->dual_link || i915->vbt.version < 197) {
|
||||
panel->vbt.dsi.bl_ports = BIT(port);
|
||||
if (panel->vbt.dsi.config->cabc_supported)
|
||||
@ -1609,11 +1611,11 @@ static void parse_dsi_backlight_ports(struct drm_i915_private *i915,
|
||||
panel->vbt.dsi.bl_ports = BIT(PORT_A);
|
||||
break;
|
||||
case DL_DCS_PORT_C:
|
||||
panel->vbt.dsi.bl_ports = BIT(PORT_C);
|
||||
panel->vbt.dsi.bl_ports = BIT(port_bc);
|
||||
break;
|
||||
default:
|
||||
case DL_DCS_PORT_A_AND_C:
|
||||
panel->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
|
||||
panel->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(port_bc);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1625,12 +1627,12 @@ static void parse_dsi_backlight_ports(struct drm_i915_private *i915,
|
||||
panel->vbt.dsi.cabc_ports = BIT(PORT_A);
|
||||
break;
|
||||
case DL_DCS_PORT_C:
|
||||
panel->vbt.dsi.cabc_ports = BIT(PORT_C);
|
||||
panel->vbt.dsi.cabc_ports = BIT(port_bc);
|
||||
break;
|
||||
default:
|
||||
case DL_DCS_PORT_A_AND_C:
|
||||
panel->vbt.dsi.cabc_ports =
|
||||
BIT(PORT_A) | BIT(PORT_C);
|
||||
BIT(PORT_A) | BIT(port_bc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -2418,7 +2420,7 @@ static enum port dvo_port_to_port(struct drm_i915_private *i915,
|
||||
[PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
|
||||
};
|
||||
|
||||
if (DISPLAY_VER(i915) == 13)
|
||||
if (DISPLAY_VER(i915) >= 13)
|
||||
return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping),
|
||||
ARRAY_SIZE(xelpd_port_mapping[0]),
|
||||
xelpd_port_mapping,
|
||||
@ -3576,7 +3578,7 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
|
||||
aux_ch = AUX_CH_C;
|
||||
break;
|
||||
case DP_AUX_D:
|
||||
if (DISPLAY_VER(i915) == 13)
|
||||
if (DISPLAY_VER(i915) >= 13)
|
||||
aux_ch = AUX_CH_D_XELPD;
|
||||
else if (IS_ALDERLAKE_S(i915))
|
||||
aux_ch = AUX_CH_USBC3;
|
||||
@ -3586,7 +3588,7 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
|
||||
aux_ch = AUX_CH_D;
|
||||
break;
|
||||
case DP_AUX_E:
|
||||
if (DISPLAY_VER(i915) == 13)
|
||||
if (DISPLAY_VER(i915) >= 13)
|
||||
aux_ch = AUX_CH_E_XELPD;
|
||||
else if (IS_ALDERLAKE_S(i915))
|
||||
aux_ch = AUX_CH_USBC4;
|
||||
@ -3594,25 +3596,25 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
|
||||
aux_ch = AUX_CH_E;
|
||||
break;
|
||||
case DP_AUX_F:
|
||||
if (DISPLAY_VER(i915) == 13)
|
||||
if (DISPLAY_VER(i915) >= 13)
|
||||
aux_ch = AUX_CH_USBC1;
|
||||
else
|
||||
aux_ch = AUX_CH_F;
|
||||
break;
|
||||
case DP_AUX_G:
|
||||
if (DISPLAY_VER(i915) == 13)
|
||||
if (DISPLAY_VER(i915) >= 13)
|
||||
aux_ch = AUX_CH_USBC2;
|
||||
else
|
||||
aux_ch = AUX_CH_G;
|
||||
break;
|
||||
case DP_AUX_H:
|
||||
if (DISPLAY_VER(i915) == 13)
|
||||
if (DISPLAY_VER(i915) >= 13)
|
||||
aux_ch = AUX_CH_USBC3;
|
||||
else
|
||||
aux_ch = AUX_CH_H;
|
||||
break;
|
||||
case DP_AUX_I:
|
||||
if (DISPLAY_VER(i915) == 13)
|
||||
if (DISPLAY_VER(i915) >= 13)
|
||||
aux_ch = AUX_CH_USBC4;
|
||||
else
|
||||
aux_ch = AUX_CH_I;
|
||||
|
@ -147,7 +147,32 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
|
||||
qi->num_points = dram_info->num_qgv_points;
|
||||
qi->num_psf_points = dram_info->num_psf_gv_points;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12)
|
||||
if (DISPLAY_VER(dev_priv) >= 14) {
|
||||
switch (dram_info->type) {
|
||||
case INTEL_DRAM_DDR4:
|
||||
qi->t_bl = 4;
|
||||
qi->max_numchannels = 2;
|
||||
qi->channel_width = 64;
|
||||
qi->deinterleave = 2;
|
||||
break;
|
||||
case INTEL_DRAM_DDR5:
|
||||
qi->t_bl = 8;
|
||||
qi->max_numchannels = 4;
|
||||
qi->channel_width = 32;
|
||||
qi->deinterleave = 2;
|
||||
break;
|
||||
case INTEL_DRAM_LPDDR4:
|
||||
case INTEL_DRAM_LPDDR5:
|
||||
qi->t_bl = 16;
|
||||
qi->max_numchannels = 8;
|
||||
qi->channel_width = 16;
|
||||
qi->deinterleave = 4;
|
||||
break;
|
||||
default:
|
||||
MISSING_CASE(dram_info->type);
|
||||
return -EINVAL;
|
||||
}
|
||||
} else if (DISPLAY_VER(dev_priv) >= 12) {
|
||||
switch (dram_info->type) {
|
||||
case INTEL_DRAM_DDR4:
|
||||
qi->t_bl = is_y_tile ? 8 : 4;
|
||||
@ -181,7 +206,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
|
||||
qi->max_numchannels = 1;
|
||||
break;
|
||||
}
|
||||
else if (DISPLAY_VER(dev_priv) == 11) {
|
||||
} else if (DISPLAY_VER(dev_priv) == 11) {
|
||||
qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
|
||||
qi->max_numchannels = 1;
|
||||
}
|
||||
@ -284,6 +309,13 @@ static const struct intel_sa_info adlp_sa_info = {
|
||||
.derating = 20,
|
||||
};
|
||||
|
||||
static const struct intel_sa_info mtl_sa_info = {
|
||||
.deburst = 32,
|
||||
.deprogbwlimit = 38, /* GB/s */
|
||||
.displayrtids = 256,
|
||||
.derating = 20,
|
||||
};
|
||||
|
||||
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
|
||||
{
|
||||
struct intel_qgv_info qi = {};
|
||||
@ -346,9 +378,9 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
|
||||
* as it will fail and pointless anyway.
|
||||
*/
|
||||
if (qi.num_points == 1)
|
||||
dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
|
||||
dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
|
||||
else
|
||||
dev_priv->sagv_status = I915_SAGV_ENABLED;
|
||||
dev_priv->display.sagv.status = I915_SAGV_ENABLED;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -404,15 +436,17 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
|
||||
int clpchgroup;
|
||||
int j;
|
||||
|
||||
if (i < num_groups - 1)
|
||||
bi_next = &dev_priv->max_bw[i + 1];
|
||||
|
||||
clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
|
||||
|
||||
if (i < num_groups - 1 && clpchgroup < clperchgroup)
|
||||
bi_next->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
|
||||
else
|
||||
bi_next->num_planes = 0;
|
||||
if (i < num_groups - 1) {
|
||||
bi_next = &dev_priv->max_bw[i + 1];
|
||||
|
||||
if (clpchgroup < clperchgroup)
|
||||
bi_next->num_planes = (ipqdepth - clpchgroup) /
|
||||
clpchgroup + 1;
|
||||
else
|
||||
bi_next->num_planes = 0;
|
||||
}
|
||||
|
||||
bi->num_qgv_points = qi.num_points;
|
||||
bi->num_psf_gv_points = qi.num_psf_points;
|
||||
@ -456,9 +490,9 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
|
||||
* as it will fail and pointless anyway.
|
||||
*/
|
||||
if (qi.num_points == 1)
|
||||
dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
|
||||
dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
|
||||
else
|
||||
dev_priv->sagv_status = I915_SAGV_ENABLED;
|
||||
dev_priv->display.sagv.status = I915_SAGV_ENABLED;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -485,7 +519,7 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
|
||||
bi->deratedbw[0] = deratedbw;
|
||||
}
|
||||
|
||||
i915->sagv_status = I915_SAGV_NOT_CONTROLLED;
|
||||
i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
|
||||
}
|
||||
|
||||
static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
|
||||
@ -558,7 +592,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
|
||||
if (!HAS_DISPLAY(dev_priv))
|
||||
return;
|
||||
|
||||
if (IS_DG2(dev_priv))
|
||||
if (DISPLAY_VER(dev_priv) >= 14)
|
||||
tgl_get_bw_info(dev_priv, &mtl_sa_info);
|
||||
else if (IS_DG2(dev_priv))
|
||||
dg2_get_bw_info(dev_priv);
|
||||
else if (IS_ALDERLAKE_P(dev_priv))
|
||||
tgl_get_bw_info(dev_priv, &adlp_sa_info);
|
||||
|
@ -79,26 +79,26 @@ struct intel_cdclk_funcs {
|
||||
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
|
||||
struct intel_cdclk_config *cdclk_config)
|
||||
{
|
||||
dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
|
||||
dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
|
||||
}
|
||||
|
||||
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
|
||||
const struct intel_cdclk_config *cdclk_config,
|
||||
enum pipe pipe)
|
||||
{
|
||||
dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
|
||||
dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
|
||||
}
|
||||
|
||||
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
|
||||
struct intel_cdclk_state *cdclk_config)
|
||||
{
|
||||
return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
|
||||
return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config);
|
||||
}
|
||||
|
||||
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
|
||||
int cdclk)
|
||||
{
|
||||
return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
|
||||
return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
|
||||
}
|
||||
|
||||
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
|
||||
@ -2080,7 +2080,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
|
||||
if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
|
||||
return;
|
||||
|
||||
if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
|
||||
if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
|
||||
return;
|
||||
|
||||
intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
|
||||
@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
|
||||
* functions use cdclk. Not all platforms/ports do,
|
||||
* but we'll lock them all for simplicity.
|
||||
*/
|
||||
mutex_lock(&dev_priv->gmbus_mutex);
|
||||
mutex_lock(&dev_priv->display.gmbus.mutex);
|
||||
for_each_intel_dp(&dev_priv->drm, encoder) {
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
||||
|
||||
mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
|
||||
&dev_priv->gmbus_mutex);
|
||||
&dev_priv->display.gmbus.mutex);
|
||||
}
|
||||
|
||||
intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
|
||||
@ -2113,7 +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
|
||||
|
||||
mutex_unlock(&intel_dp->aux.hw_mutex);
|
||||
}
|
||||
mutex_unlock(&dev_priv->gmbus_mutex);
|
||||
mutex_unlock(&dev_priv->display.gmbus.mutex);
|
||||
|
||||
for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
||||
@ -2300,7 +2300,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
|
||||
min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
|
||||
|
||||
/*
|
||||
* HACK. Currently for TGL platforms we calculate
|
||||
* HACK. Currently for TGL/DG2 platforms we calculate
|
||||
* min_cdclk initially based on pixel_rate divided
|
||||
* by 2, accounting for also plane requirements,
|
||||
* however in some cases the lowest possible CDCLK
|
||||
@ -2308,7 +2308,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
|
||||
* Explicitly stating here that this seems to be currently
|
||||
* rather a Hack, than final solution.
|
||||
*/
|
||||
if (IS_TIGERLAKE(dev_priv)) {
|
||||
if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) {
|
||||
/*
|
||||
* Clamp to max_cdclk_freq in case pixel rate is higher,
|
||||
* in order not to break an 8K, but still leave W/A at place.
|
||||
@ -3036,6 +3036,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
|
||||
|
||||
if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
|
||||
freq = dg1_rawclk(dev_priv);
|
||||
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
|
||||
/*
|
||||
* MTL always uses a 38.4 MHz rawclk. The bspec tells us
|
||||
* "RAWCLK_FREQ defaults to the values for 38.4 and does
|
||||
* not need to be programmed."
|
||||
*/
|
||||
freq = 38400;
|
||||
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
|
||||
freq = cnp_rawclk(dev_priv);
|
||||
else if (HAS_PCH_SPLIT(dev_priv))
|
||||
@ -3187,78 +3194,78 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
|
||||
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if (IS_DG2(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
|
||||
dev_priv->cdclk.table = dg2_cdclk_table;
|
||||
} else if (IS_ALDERLAKE_P(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
|
||||
/* Wa_22011320316:adl-p[a0] */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
|
||||
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
|
||||
else
|
||||
dev_priv->cdclk.table = adlp_cdclk_table;
|
||||
} else if (IS_ROCKETLAKE(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
|
||||
dev_priv->cdclk.table = rkl_cdclk_table;
|
||||
} else if (DISPLAY_VER(dev_priv) >= 12) {
|
||||
dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
|
||||
dev_priv->cdclk.table = icl_cdclk_table;
|
||||
} else if (IS_JSL_EHL(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &ehl_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
|
||||
dev_priv->cdclk.table = icl_cdclk_table;
|
||||
} else if (DISPLAY_VER(dev_priv) >= 11) {
|
||||
dev_priv->cdclk_funcs = &icl_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
|
||||
dev_priv->cdclk.table = icl_cdclk_table;
|
||||
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &bxt_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
|
||||
if (IS_GEMINILAKE(dev_priv))
|
||||
dev_priv->cdclk.table = glk_cdclk_table;
|
||||
else
|
||||
dev_priv->cdclk.table = bxt_cdclk_table;
|
||||
} else if (DISPLAY_VER(dev_priv) == 9) {
|
||||
dev_priv->cdclk_funcs = &skl_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
|
||||
} else if (IS_BROADWELL(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &bdw_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
|
||||
} else if (IS_HASWELL(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &hsw_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
|
||||
} else if (IS_CHERRYVIEW(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &chv_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
|
||||
} else if (IS_VALLEYVIEW(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &vlv_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
|
||||
} else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
|
||||
} else if (IS_IRONLAKE(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &ilk_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
|
||||
} else if (IS_GM45(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &gm45_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
|
||||
} else if (IS_G45(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &g33_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
|
||||
} else if (IS_I965GM(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &i965gm_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
|
||||
} else if (IS_I965G(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
|
||||
} else if (IS_PINEVIEW(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &pnv_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
|
||||
} else if (IS_G33(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &g33_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
|
||||
} else if (IS_I945GM(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &i945gm_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
|
||||
} else if (IS_I945G(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
|
||||
} else if (IS_I915GM(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &i915gm_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
|
||||
} else if (IS_I915G(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &i915g_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
|
||||
} else if (IS_I865G(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &i865g_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
|
||||
} else if (IS_I85X(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &i85x_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
|
||||
} else if (IS_I845G(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &i845g_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
|
||||
} else if (IS_I830(dev_priv)) {
|
||||
dev_priv->cdclk_funcs = &i830_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
|
||||
}
|
||||
|
||||
if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs,
|
||||
if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
|
||||
"Unknown platform. Assuming i830\n"))
|
||||
dev_priv->cdclk_funcs = &i830_cdclk_funcs;
|
||||
dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
|
||||
}
|
||||
|
@ -1167,22 +1167,22 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
||||
|
||||
dev_priv->color_funcs->load_luts(crtc_state);
|
||||
dev_priv->display.funcs.color->load_luts(crtc_state);
|
||||
}
|
||||
|
||||
void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
||||
|
||||
if (dev_priv->color_funcs->color_commit_noarm)
|
||||
dev_priv->color_funcs->color_commit_noarm(crtc_state);
|
||||
if (dev_priv->display.funcs.color->color_commit_noarm)
|
||||
dev_priv->display.funcs.color->color_commit_noarm(crtc_state);
|
||||
}
|
||||
|
||||
void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
||||
|
||||
dev_priv->color_funcs->color_commit_arm(crtc_state);
|
||||
dev_priv->display.funcs.color->color_commit_arm(crtc_state);
|
||||
}
|
||||
|
||||
static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
|
||||
@ -1238,15 +1238,15 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
||||
|
||||
return dev_priv->color_funcs->color_check(crtc_state);
|
||||
return dev_priv->display.funcs.color->color_check(crtc_state);
|
||||
}
|
||||
|
||||
void intel_color_get_config(struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
||||
|
||||
if (dev_priv->color_funcs->read_luts)
|
||||
dev_priv->color_funcs->read_luts(crtc_state);
|
||||
if (dev_priv->display.funcs.color->read_luts)
|
||||
dev_priv->display.funcs.color->read_luts(crtc_state);
|
||||
}
|
||||
|
||||
static bool need_plane_update(struct intel_plane *plane,
|
||||
@ -2225,28 +2225,28 @@ void intel_color_init(struct intel_crtc *crtc)
|
||||
|
||||
if (HAS_GMCH(dev_priv)) {
|
||||
if (IS_CHERRYVIEW(dev_priv)) {
|
||||
dev_priv->color_funcs = &chv_color_funcs;
|
||||
dev_priv->display.funcs.color = &chv_color_funcs;
|
||||
} else if (DISPLAY_VER(dev_priv) >= 4) {
|
||||
dev_priv->color_funcs = &i965_color_funcs;
|
||||
dev_priv->display.funcs.color = &i965_color_funcs;
|
||||
} else {
|
||||
dev_priv->color_funcs = &i9xx_color_funcs;
|
||||
dev_priv->display.funcs.color = &i9xx_color_funcs;
|
||||
}
|
||||
} else {
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
dev_priv->color_funcs = &icl_color_funcs;
|
||||
dev_priv->display.funcs.color = &icl_color_funcs;
|
||||
else if (DISPLAY_VER(dev_priv) == 10)
|
||||
dev_priv->color_funcs = &glk_color_funcs;
|
||||
dev_priv->display.funcs.color = &glk_color_funcs;
|
||||
else if (DISPLAY_VER(dev_priv) == 9)
|
||||
dev_priv->color_funcs = &skl_color_funcs;
|
||||
dev_priv->display.funcs.color = &skl_color_funcs;
|
||||
else if (DISPLAY_VER(dev_priv) == 8)
|
||||
dev_priv->color_funcs = &bdw_color_funcs;
|
||||
dev_priv->display.funcs.color = &bdw_color_funcs;
|
||||
else if (DISPLAY_VER(dev_priv) == 7) {
|
||||
if (IS_HASWELL(dev_priv))
|
||||
dev_priv->color_funcs = &hsw_color_funcs;
|
||||
dev_priv->display.funcs.color = &hsw_color_funcs;
|
||||
else
|
||||
dev_priv->color_funcs = &ivb_color_funcs;
|
||||
dev_priv->display.funcs.color = &ivb_color_funcs;
|
||||
} else
|
||||
dev_priv->color_funcs = &ilk_color_funcs;
|
||||
dev_priv->display.funcs.color = &ilk_color_funcs;
|
||||
}
|
||||
|
||||
drm_crtc_enable_color_mgmt(&crtc->base,
|
||||
|
@ -134,8 +134,8 @@ static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
|
||||
plane->base.base.id, plane->base.name,
|
||||
fb->base.id, fb->width, fb->height, &fb->format->format,
|
||||
fb->modifier, str_yes_no(plane_state->uapi.visible));
|
||||
drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
|
||||
plane_state->hw.rotation, plane_state->scaler_id);
|
||||
drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d, scaling_filter: %d\n",
|
||||
plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter);
|
||||
if (plane_state->uapi.visible)
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
|
||||
@ -262,10 +262,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
|
||||
|
||||
if (DISPLAY_VER(i915) >= 9)
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
|
||||
"num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n",
|
||||
crtc->num_scalers,
|
||||
pipe_config->scaler_state.scaler_users,
|
||||
pipe_config->scaler_state.scaler_id);
|
||||
pipe_config->scaler_state.scaler_id,
|
||||
pipe_config->hw.scaling_filter);
|
||||
|
||||
if (HAS_GMCH(i915))
|
||||
drm_dbg_kms(&i915->drm,
|
||||
|
@ -1425,7 +1425,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
|
||||
static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
|
||||
{
|
||||
mutex_lock(&i915->dpll.lock);
|
||||
mutex_lock(&i915->display.dpll.lock);
|
||||
|
||||
intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
|
||||
|
||||
@ -1435,17 +1435,17 @@ static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
*/
|
||||
intel_de_rmw(i915, reg, clk_off, 0);
|
||||
|
||||
mutex_unlock(&i915->dpll.lock);
|
||||
mutex_unlock(&i915->display.dpll.lock);
|
||||
}
|
||||
|
||||
static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
u32 clk_off)
|
||||
{
|
||||
mutex_lock(&i915->dpll.lock);
|
||||
mutex_lock(&i915->display.dpll.lock);
|
||||
|
||||
intel_de_rmw(i915, reg, 0, clk_off);
|
||||
|
||||
mutex_unlock(&i915->dpll.lock);
|
||||
mutex_unlock(&i915->display.dpll.lock);
|
||||
}
|
||||
|
||||
static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
@ -1720,12 +1720,12 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
|
||||
intel_de_write(i915, DDI_CLK_SEL(port),
|
||||
icl_pll_to_ddi_clk_sel(encoder, crtc_state));
|
||||
|
||||
mutex_lock(&i915->dpll.lock);
|
||||
mutex_lock(&i915->display.dpll.lock);
|
||||
|
||||
intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
|
||||
ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
|
||||
|
||||
mutex_unlock(&i915->dpll.lock);
|
||||
mutex_unlock(&i915->display.dpll.lock);
|
||||
}
|
||||
|
||||
static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
|
||||
@ -1734,12 +1734,12 @@ static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
|
||||
enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
|
||||
enum port port = encoder->port;
|
||||
|
||||
mutex_lock(&i915->dpll.lock);
|
||||
mutex_lock(&i915->display.dpll.lock);
|
||||
|
||||
intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
|
||||
0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
|
||||
|
||||
mutex_unlock(&i915->dpll.lock);
|
||||
mutex_unlock(&i915->display.dpll.lock);
|
||||
|
||||
intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
|
||||
}
|
||||
@ -1824,7 +1824,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
|
||||
if (drm_WARN_ON(&i915->drm, !pll))
|
||||
return;
|
||||
|
||||
mutex_lock(&i915->dpll.lock);
|
||||
mutex_lock(&i915->display.dpll.lock);
|
||||
|
||||
intel_de_rmw(i915, DPLL_CTRL2,
|
||||
DPLL_CTRL2_DDI_CLK_OFF(port) |
|
||||
@ -1832,7 +1832,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
|
||||
DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
|
||||
DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
|
||||
|
||||
mutex_unlock(&i915->dpll.lock);
|
||||
mutex_unlock(&i915->display.dpll.lock);
|
||||
}
|
||||
|
||||
static void skl_ddi_disable_clock(struct intel_encoder *encoder)
|
||||
@ -1840,12 +1840,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
|
||||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum port port = encoder->port;
|
||||
|
||||
mutex_lock(&i915->dpll.lock);
|
||||
mutex_lock(&i915->display.dpll.lock);
|
||||
|
||||
intel_de_rmw(i915, DPLL_CTRL2,
|
||||
0, DPLL_CTRL2_DDI_CLK_OFF(port));
|
||||
|
||||
mutex_unlock(&i915->dpll.lock);
|
||||
mutex_unlock(&i915->display.dpll.lock);
|
||||
}
|
||||
|
||||
static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
|
||||
@ -2691,10 +2691,14 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
|
||||
dig_port->set_infoframes(encoder, false,
|
||||
old_crtc_state, old_conn_state);
|
||||
|
||||
intel_ddi_disable_pipe_clock(old_crtc_state);
|
||||
if (DISPLAY_VER(dev_priv) < 12)
|
||||
intel_ddi_disable_pipe_clock(old_crtc_state);
|
||||
|
||||
intel_disable_ddi_buf(encoder, old_crtc_state);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12)
|
||||
intel_ddi_disable_pipe_clock(old_crtc_state);
|
||||
|
||||
intel_display_power_put(dev_priv,
|
||||
dig_port->ddi_io_power_domain,
|
||||
fetch_and_zero(&dig_port->ddi_io_wakeref));
|
||||
@ -2862,6 +2866,8 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
|
||||
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
||||
struct drm_connector *connector = conn_state->connector;
|
||||
enum port port = encoder->port;
|
||||
enum phy phy = intel_port_to_phy(dev_priv, port);
|
||||
u32 buf_ctl;
|
||||
|
||||
if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
|
||||
crtc_state->hdmi_high_tmds_clock_ratio,
|
||||
@ -2919,8 +2925,12 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
|
||||
* On ADL_P the PHY link rate and lane count must be programmed but
|
||||
* these are both 0 for HDMI.
|
||||
*/
|
||||
intel_de_write(dev_priv, DDI_BUF_CTL(port),
|
||||
dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
|
||||
buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
|
||||
if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
|
||||
drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
|
||||
buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
|
||||
}
|
||||
intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
|
||||
|
||||
intel_audio_codec_enable(encoder, crtc_state, conn_state);
|
||||
}
|
||||
@ -4028,7 +4038,7 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
|
||||
static bool lpt_digital_port_connected(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
|
||||
u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
|
||||
|
||||
return intel_de_read(dev_priv, SDEISR) & bit;
|
||||
}
|
||||
@ -4036,7 +4046,7 @@ static bool lpt_digital_port_connected(struct intel_encoder *encoder)
|
||||
static bool hsw_digital_port_connected(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
|
||||
u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
|
||||
|
||||
return intel_de_read(dev_priv, DEISR) & bit;
|
||||
}
|
||||
@ -4044,7 +4054,7 @@ static bool hsw_digital_port_connected(struct intel_encoder *encoder)
|
||||
static bool bdw_digital_port_connected(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
|
||||
u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
|
||||
|
||||
return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
|
||||
}
|
||||
|
@ -163,16 +163,16 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
|
||||
*/
|
||||
void intel_update_watermarks(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if (dev_priv->wm_disp->update_wm)
|
||||
dev_priv->wm_disp->update_wm(dev_priv);
|
||||
if (dev_priv->display.funcs.wm->update_wm)
|
||||
dev_priv->display.funcs.wm->update_wm(dev_priv);
|
||||
}
|
||||
|
||||
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
if (dev_priv->wm_disp->compute_pipe_wm)
|
||||
return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
|
||||
if (dev_priv->display.funcs.wm->compute_pipe_wm)
|
||||
return dev_priv->display.funcs.wm->compute_pipe_wm(state, crtc);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -180,20 +180,20 @@ static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
if (!dev_priv->wm_disp->compute_intermediate_wm)
|
||||
if (!dev_priv->display.funcs.wm->compute_intermediate_wm)
|
||||
return 0;
|
||||
if (drm_WARN_ON(&dev_priv->drm,
|
||||
!dev_priv->wm_disp->compute_pipe_wm))
|
||||
!dev_priv->display.funcs.wm->compute_pipe_wm))
|
||||
return 0;
|
||||
return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
|
||||
return dev_priv->display.funcs.wm->compute_intermediate_wm(state, crtc);
|
||||
}
|
||||
|
||||
static bool intel_initial_watermarks(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
if (dev_priv->wm_disp->initial_watermarks) {
|
||||
dev_priv->wm_disp->initial_watermarks(state, crtc);
|
||||
if (dev_priv->display.funcs.wm->initial_watermarks) {
|
||||
dev_priv->display.funcs.wm->initial_watermarks(state, crtc);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
@ -203,23 +203,23 @@ static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
if (dev_priv->wm_disp->atomic_update_watermarks)
|
||||
dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
|
||||
if (dev_priv->display.funcs.wm->atomic_update_watermarks)
|
||||
dev_priv->display.funcs.wm->atomic_update_watermarks(state, crtc);
|
||||
}
|
||||
|
||||
static void intel_optimize_watermarks(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
if (dev_priv->wm_disp->optimize_watermarks)
|
||||
dev_priv->wm_disp->optimize_watermarks(state, crtc);
|
||||
if (dev_priv->display.funcs.wm->optimize_watermarks)
|
||||
dev_priv->display.funcs.wm->optimize_watermarks(state, crtc);
|
||||
}
|
||||
|
||||
static int intel_compute_global_watermarks(struct intel_atomic_state *state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
if (dev_priv->wm_disp->compute_global_watermarks)
|
||||
return dev_priv->wm_disp->compute_global_watermarks(state);
|
||||
if (dev_priv->display.funcs.wm->compute_global_watermarks)
|
||||
return dev_priv->display.funcs.wm->compute_global_watermarks(state);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1486,7 +1486,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state)
|
||||
* Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
|
||||
* TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
|
||||
*/
|
||||
if (i915->dpll.mgr) {
|
||||
if (i915->display.dpll.mgr) {
|
||||
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
|
||||
if (intel_crtc_needs_modeset(new_crtc_state))
|
||||
continue;
|
||||
@ -2080,22 +2080,20 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
|
||||
{
|
||||
if (phy == PHY_NONE)
|
||||
return false;
|
||||
else if (IS_DG2(dev_priv))
|
||||
/*
|
||||
* DG2 outputs labelled as "combo PHY" in the bspec use
|
||||
* SNPS PHYs with completely different programming,
|
||||
* hence we always return false here.
|
||||
*/
|
||||
return false;
|
||||
else if (IS_ALDERLAKE_S(dev_priv))
|
||||
return phy <= PHY_E;
|
||||
else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
|
||||
return phy <= PHY_D;
|
||||
else if (IS_JSL_EHL(dev_priv))
|
||||
return phy <= PHY_C;
|
||||
else if (DISPLAY_VER(dev_priv) >= 11)
|
||||
else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
|
||||
return phy <= PHY_B;
|
||||
else
|
||||
/*
|
||||
* DG2 outputs labelled as "combo PHY" in the bspec use
|
||||
* SNPS PHYs with completely different programming,
|
||||
* hence we always return false here.
|
||||
*/
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -2401,7 +2399,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
|
||||
if (DISPLAY_VER(dev_priv) != 2)
|
||||
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
|
||||
|
||||
if (!dev_priv->wm_disp->initial_watermarks)
|
||||
if (!dev_priv->display.funcs.wm->initial_watermarks)
|
||||
intel_update_watermarks(dev_priv);
|
||||
|
||||
/* clock the pipe down to 640x480@60 to potentially save power */
|
||||
@ -4145,7 +4143,7 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
|
||||
|
||||
if (!i915->display->get_pipe_config(crtc, crtc_state))
|
||||
if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
|
||||
return false;
|
||||
|
||||
crtc_state->hw.active = true;
|
||||
@ -5840,7 +5838,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
|
||||
|
||||
PIPE_CONF_CHECK_BOOL(double_wide);
|
||||
|
||||
if (dev_priv->dpll.mgr) {
|
||||
if (dev_priv->display.dpll.mgr) {
|
||||
PIPE_CONF_CHECK_P(shared_dpll);
|
||||
|
||||
PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
|
||||
@ -7120,7 +7118,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
|
||||
|
||||
intel_crtc_update_active_timings(new_crtc_state);
|
||||
|
||||
dev_priv->display->crtc_enable(state, crtc);
|
||||
dev_priv->display.funcs.display->crtc_enable(state, crtc);
|
||||
|
||||
if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
|
||||
return;
|
||||
@ -7199,7 +7197,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
|
||||
*/
|
||||
intel_crtc_disable_pipe_crc(crtc);
|
||||
|
||||
dev_priv->display->crtc_disable(state, crtc);
|
||||
dev_priv->display.funcs.display->crtc_disable(state, crtc);
|
||||
crtc->active = false;
|
||||
intel_fbc_disable(crtc);
|
||||
intel_disable_shared_dpll(old_crtc_state);
|
||||
@ -7588,7 +7586,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
|
||||
}
|
||||
|
||||
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
|
||||
dev_priv->display->commit_modeset_enables(state);
|
||||
dev_priv->display.funcs.display->commit_modeset_enables(state);
|
||||
|
||||
intel_encoders_update_complete(state);
|
||||
|
||||
@ -8319,7 +8317,7 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
|
||||
.atomic_state_free = intel_atomic_state_free,
|
||||
};
|
||||
|
||||
static const struct drm_i915_display_funcs skl_display_funcs = {
|
||||
static const struct intel_display_funcs skl_display_funcs = {
|
||||
.get_pipe_config = hsw_get_pipe_config,
|
||||
.crtc_enable = hsw_crtc_enable,
|
||||
.crtc_disable = hsw_crtc_disable,
|
||||
@ -8327,7 +8325,7 @@ static const struct drm_i915_display_funcs skl_display_funcs = {
|
||||
.get_initial_plane_config = skl_get_initial_plane_config,
|
||||
};
|
||||
|
||||
static const struct drm_i915_display_funcs ddi_display_funcs = {
|
||||
static const struct intel_display_funcs ddi_display_funcs = {
|
||||
.get_pipe_config = hsw_get_pipe_config,
|
||||
.crtc_enable = hsw_crtc_enable,
|
||||
.crtc_disable = hsw_crtc_disable,
|
||||
@ -8335,7 +8333,7 @@ static const struct drm_i915_display_funcs ddi_display_funcs = {
|
||||
.get_initial_plane_config = i9xx_get_initial_plane_config,
|
||||
};
|
||||
|
||||
static const struct drm_i915_display_funcs pch_split_display_funcs = {
|
||||
static const struct intel_display_funcs pch_split_display_funcs = {
|
||||
.get_pipe_config = ilk_get_pipe_config,
|
||||
.crtc_enable = ilk_crtc_enable,
|
||||
.crtc_disable = ilk_crtc_disable,
|
||||
@ -8343,7 +8341,7 @@ static const struct drm_i915_display_funcs pch_split_display_funcs = {
|
||||
.get_initial_plane_config = i9xx_get_initial_plane_config,
|
||||
};
|
||||
|
||||
static const struct drm_i915_display_funcs vlv_display_funcs = {
|
||||
static const struct intel_display_funcs vlv_display_funcs = {
|
||||
.get_pipe_config = i9xx_get_pipe_config,
|
||||
.crtc_enable = valleyview_crtc_enable,
|
||||
.crtc_disable = i9xx_crtc_disable,
|
||||
@ -8351,7 +8349,7 @@ static const struct drm_i915_display_funcs vlv_display_funcs = {
|
||||
.get_initial_plane_config = i9xx_get_initial_plane_config,
|
||||
};
|
||||
|
||||
static const struct drm_i915_display_funcs i9xx_display_funcs = {
|
||||
static const struct intel_display_funcs i9xx_display_funcs = {
|
||||
.get_pipe_config = i9xx_get_pipe_config,
|
||||
.crtc_enable = i9xx_crtc_enable,
|
||||
.crtc_disable = i9xx_crtc_disable,
|
||||
@ -8374,16 +8372,16 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
|
||||
intel_dpll_init_clock_hook(dev_priv);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 9) {
|
||||
dev_priv->display = &skl_display_funcs;
|
||||
dev_priv->display.funcs.display = &skl_display_funcs;
|
||||
} else if (HAS_DDI(dev_priv)) {
|
||||
dev_priv->display = &ddi_display_funcs;
|
||||
dev_priv->display.funcs.display = &ddi_display_funcs;
|
||||
} else if (HAS_PCH_SPLIT(dev_priv)) {
|
||||
dev_priv->display = &pch_split_display_funcs;
|
||||
dev_priv->display.funcs.display = &pch_split_display_funcs;
|
||||
} else if (IS_CHERRYVIEW(dev_priv) ||
|
||||
IS_VALLEYVIEW(dev_priv)) {
|
||||
dev_priv->display = &vlv_display_funcs;
|
||||
dev_priv->display.funcs.display = &vlv_display_funcs;
|
||||
} else {
|
||||
dev_priv->display = &i9xx_display_funcs;
|
||||
dev_priv->display.funcs.display = &i9xx_display_funcs;
|
||||
}
|
||||
|
||||
intel_fdi_init_hook(dev_priv);
|
||||
@ -8456,7 +8454,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
|
||||
int i;
|
||||
|
||||
/* Only supported on platforms that use atomic watermark design */
|
||||
if (!dev_priv->wm_disp->optimize_watermarks)
|
||||
if (!dev_priv->display.funcs.wm->optimize_watermarks)
|
||||
return;
|
||||
|
||||
state = drm_atomic_state_alloc(&dev_priv->drm);
|
||||
@ -8692,8 +8690,6 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
|
||||
i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
|
||||
WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
|
||||
|
||||
i915->window2_delay = 0; /* No DSB so no window2 delay */
|
||||
|
||||
intel_mode_config_init(i915);
|
||||
|
||||
ret = intel_cdclk_init(i915);
|
||||
|
@ -375,7 +375,7 @@ enum hpd_pin {
|
||||
|
||||
#define for_each_pipe(__dev_priv, __p) \
|
||||
for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
|
||||
for_each_if(INTEL_INFO(__dev_priv)->display.pipe_mask & BIT(__p))
|
||||
for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
|
||||
|
||||
#define for_each_pipe_masked(__dev_priv, __p, __mask) \
|
||||
for_each_pipe(__dev_priv, __p) \
|
||||
@ -383,7 +383,7 @@ enum hpd_pin {
|
||||
|
||||
#define for_each_cpu_transcoder(__dev_priv, __t) \
|
||||
for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
|
||||
for_each_if (INTEL_INFO(__dev_priv)->display.cpu_transcoder_mask & BIT(__t))
|
||||
for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
|
||||
|
||||
#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
|
||||
for_each_cpu_transcoder(__dev_priv, __t) \
|
||||
|
261
drivers/gpu/drm/i915/display/intel_display_core.h
Normal file
261
drivers/gpu/drm/i915/display/intel_display_core.h
Normal file
@ -0,0 +1,261 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2022 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __INTEL_DISPLAY_CORE_H__
|
||||
#define __INTEL_DISPLAY_CORE_H__
|
||||
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#include "intel_display.h"
|
||||
#include "intel_dmc.h"
|
||||
#include "intel_dpll_mgr.h"
|
||||
#include "intel_gmbus.h"
|
||||
#include "intel_pm_types.h"
|
||||
|
||||
struct drm_i915_private;
|
||||
struct i915_audio_component;
|
||||
struct intel_atomic_state;
|
||||
struct intel_audio_funcs;
|
||||
struct intel_cdclk_funcs;
|
||||
struct intel_color_funcs;
|
||||
struct intel_crtc;
|
||||
struct intel_crtc_state;
|
||||
struct intel_dpll_funcs;
|
||||
struct intel_dpll_mgr;
|
||||
struct intel_fbdev;
|
||||
struct intel_fdi_funcs;
|
||||
struct intel_hotplug_funcs;
|
||||
struct intel_initial_plane_config;
|
||||
struct intel_overlay;
|
||||
|
||||
struct intel_display_funcs {
|
||||
/*
|
||||
* Returns the active state of the crtc, and if the crtc is active,
|
||||
* fills out the pipe-config with the hw state.
|
||||
*/
|
||||
bool (*get_pipe_config)(struct intel_crtc *,
|
||||
struct intel_crtc_state *);
|
||||
void (*get_initial_plane_config)(struct intel_crtc *,
|
||||
struct intel_initial_plane_config *);
|
||||
void (*crtc_enable)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void (*crtc_disable)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void (*commit_modeset_enables)(struct intel_atomic_state *state);
|
||||
};
|
||||
|
||||
/* functions used for watermark calcs for display. */
|
||||
struct intel_wm_funcs {
|
||||
/* update_wm is for legacy wm management */
|
||||
void (*update_wm)(struct drm_i915_private *dev_priv);
|
||||
int (*compute_pipe_wm)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
int (*compute_intermediate_wm)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void (*initial_watermarks)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void (*atomic_update_watermarks)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void (*optimize_watermarks)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
int (*compute_global_watermarks)(struct intel_atomic_state *state);
|
||||
};
|
||||
|
||||
struct intel_audio {
|
||||
/* hda/i915 audio component */
|
||||
struct i915_audio_component *component;
|
||||
bool component_registered;
|
||||
/* mutex for audio/video sync */
|
||||
struct mutex mutex;
|
||||
int power_refcount;
|
||||
u32 freq_cntrl;
|
||||
|
||||
/* Used to save the pipe-to-encoder mapping for audio */
|
||||
struct intel_encoder *encoder_map[I915_MAX_PIPES];
|
||||
|
||||
/* necessary resource sharing with HDMI LPE audio driver. */
|
||||
struct {
|
||||
struct platform_device *platdev;
|
||||
int irq;
|
||||
} lpe;
|
||||
};
|
||||
|
||||
/*
|
||||
* dpll and cdclk state is protected by connection_mutex dpll.lock serializes
|
||||
* intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per
|
||||
* dpll, because on some platforms plls share registers.
|
||||
*/
|
||||
struct intel_dpll {
|
||||
struct mutex lock;
|
||||
|
||||
int num_shared_dpll;
|
||||
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
|
||||
const struct intel_dpll_mgr *mgr;
|
||||
|
||||
struct {
|
||||
int nssc;
|
||||
int ssc;
|
||||
} ref_clks;
|
||||
};
|
||||
|
||||
struct intel_hotplug {
|
||||
struct delayed_work hotplug_work;
|
||||
|
||||
const u32 *hpd, *pch_hpd;
|
||||
|
||||
struct {
|
||||
unsigned long last_jiffies;
|
||||
int count;
|
||||
enum {
|
||||
HPD_ENABLED = 0,
|
||||
HPD_DISABLED = 1,
|
||||
HPD_MARK_DISABLED = 2
|
||||
} state;
|
||||
} stats[HPD_NUM_PINS];
|
||||
u32 event_bits;
|
||||
u32 retry_bits;
|
||||
struct delayed_work reenable_work;
|
||||
|
||||
u32 long_port_mask;
|
||||
u32 short_port_mask;
|
||||
struct work_struct dig_port_work;
|
||||
|
||||
struct work_struct poll_init_work;
|
||||
bool poll_enabled;
|
||||
|
||||
unsigned int hpd_storm_threshold;
|
||||
/* Whether or not to count short HPD IRQs in HPD storms */
|
||||
u8 hpd_short_storm_enabled;
|
||||
|
||||
/*
|
||||
* if we get a HPD irq from DP and a HPD irq from non-DP
|
||||
* the non-DP HPD could block the workqueue on a mode config
|
||||
* mutex getting, that userspace may have taken. However
|
||||
* userspace is waiting on the DP workqueue to run which is
|
||||
* blocked behind the non-DP one.
|
||||
*/
|
||||
struct workqueue_struct *dp_wq;
|
||||
};
|
||||
|
||||
struct intel_wm {
|
||||
/*
|
||||
* Raw watermark latency values:
|
||||
* in 0.1us units for WM0,
|
||||
* in 0.5us units for WM1+.
|
||||
*/
|
||||
/* primary */
|
||||
u16 pri_latency[5];
|
||||
/* sprite */
|
||||
u16 spr_latency[5];
|
||||
/* cursor */
|
||||
u16 cur_latency[5];
|
||||
/*
|
||||
* Raw watermark memory latency values
|
||||
* for SKL for all 8 levels
|
||||
* in 1us units.
|
||||
*/
|
||||
u16 skl_latency[8];
|
||||
|
||||
/* current hardware state */
|
||||
union {
|
||||
struct ilk_wm_values hw;
|
||||
struct vlv_wm_values vlv;
|
||||
struct g4x_wm_values g4x;
|
||||
};
|
||||
|
||||
u8 max_level;
|
||||
|
||||
/*
|
||||
* Should be held around atomic WM register writing; also
|
||||
* protects * intel_crtc->wm.active and
|
||||
* crtc_state->wm.need_postvbl_update.
|
||||
*/
|
||||
struct mutex wm_mutex;
|
||||
};
|
||||
|
||||
struct intel_display {
|
||||
/* Display functions */
|
||||
struct {
|
||||
/* Top level crtc-ish functions */
|
||||
const struct intel_display_funcs *display;
|
||||
|
||||
/* Display CDCLK functions */
|
||||
const struct intel_cdclk_funcs *cdclk;
|
||||
|
||||
/* Display pll funcs */
|
||||
const struct intel_dpll_funcs *dpll;
|
||||
|
||||
/* irq display functions */
|
||||
const struct intel_hotplug_funcs *hotplug;
|
||||
|
||||
/* pm display functions */
|
||||
const struct intel_wm_funcs *wm;
|
||||
|
||||
/* fdi display functions */
|
||||
const struct intel_fdi_funcs *fdi;
|
||||
|
||||
/* Display internal color functions */
|
||||
const struct intel_color_funcs *color;
|
||||
|
||||
/* Display internal audio functions */
|
||||
const struct intel_audio_funcs *audio;
|
||||
} funcs;
|
||||
|
||||
/* Grouping using anonymous structs. Keep sorted. */
|
||||
struct {
|
||||
/* list of fbdev register on this device */
|
||||
struct intel_fbdev *fbdev;
|
||||
struct work_struct suspend_work;
|
||||
} fbdev;
|
||||
|
||||
struct {
|
||||
/*
|
||||
* Base address of where the gmbus and gpio blocks are located
|
||||
* (either on PCH or on SoC for platforms without PCH).
|
||||
*/
|
||||
u32 mmio_base;
|
||||
|
||||
/*
|
||||
* gmbus.mutex protects against concurrent usage of the single
|
||||
* hw gmbus controller on different i2c buses.
|
||||
*/
|
||||
struct mutex mutex;
|
||||
|
||||
struct intel_gmbus *bus[GMBUS_NUM_PINS];
|
||||
|
||||
wait_queue_head_t wait_queue;
|
||||
} gmbus;
|
||||
|
||||
struct {
|
||||
u32 mmio_base;
|
||||
|
||||
/* protects panel power sequencer state */
|
||||
struct mutex mutex;
|
||||
} pps;
|
||||
|
||||
struct {
|
||||
enum {
|
||||
I915_SAGV_UNKNOWN = 0,
|
||||
I915_SAGV_DISABLED,
|
||||
I915_SAGV_ENABLED,
|
||||
I915_SAGV_NOT_CONTROLLED
|
||||
} status;
|
||||
|
||||
u32 block_time_us;
|
||||
} sagv;
|
||||
|
||||
/* Grouping using named structs. Keep sorted. */
|
||||
struct intel_audio audio;
|
||||
struct intel_dmc dmc;
|
||||
struct intel_dpll dpll;
|
||||
struct intel_hotplug hotplug;
|
||||
struct intel_overlay *overlay;
|
||||
struct intel_wm wm;
|
||||
};
|
||||
|
||||
#endif /* __INTEL_DISPLAY_CORE_H__ */
|
@ -129,7 +129,7 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
|
||||
struct drm_framebuffer *drm_fb;
|
||||
|
||||
#ifdef CONFIG_DRM_FBDEV_EMULATION
|
||||
fbdev_fb = intel_fbdev_framebuffer(dev_priv->fbdev);
|
||||
fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev);
|
||||
if (fbdev_fb) {
|
||||
seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
|
||||
fbdev_fb->base.width,
|
||||
@ -722,10 +722,11 @@ static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc)
|
||||
|
||||
/* Not all platformas have a scaler */
|
||||
if (num_scalers) {
|
||||
seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
|
||||
seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d scaling_filter=%d",
|
||||
num_scalers,
|
||||
crtc_state->scaler_state.scaler_users,
|
||||
crtc_state->scaler_state.scaler_id);
|
||||
crtc_state->scaler_state.scaler_id,
|
||||
crtc_state->hw.scaling_filter);
|
||||
|
||||
for (i = 0; i < num_scalers; i++) {
|
||||
const struct intel_scaler *sc =
|
||||
@ -932,11 +933,11 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
|
||||
drm_modeset_lock_all(dev);
|
||||
|
||||
seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
|
||||
dev_priv->dpll.ref_clks.nssc,
|
||||
dev_priv->dpll.ref_clks.ssc);
|
||||
dev_priv->display.dpll.ref_clks.nssc,
|
||||
dev_priv->display.dpll.ref_clks.ssc);
|
||||
|
||||
for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
|
||||
struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
|
||||
for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
|
||||
struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
|
||||
|
||||
seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
|
||||
pll->info->id);
|
||||
@ -1427,9 +1428,9 @@ static int pri_wm_latency_show(struct seq_file *m, void *data)
|
||||
const u16 *latencies;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 9)
|
||||
latencies = dev_priv->wm.skl_latency;
|
||||
latencies = dev_priv->display.wm.skl_latency;
|
||||
else
|
||||
latencies = dev_priv->wm.pri_latency;
|
||||
latencies = dev_priv->display.wm.pri_latency;
|
||||
|
||||
wm_latency_show(m, latencies);
|
||||
|
||||
@ -1442,9 +1443,9 @@ static int spr_wm_latency_show(struct seq_file *m, void *data)
|
||||
const u16 *latencies;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 9)
|
||||
latencies = dev_priv->wm.skl_latency;
|
||||
latencies = dev_priv->display.wm.skl_latency;
|
||||
else
|
||||
latencies = dev_priv->wm.spr_latency;
|
||||
latencies = dev_priv->display.wm.spr_latency;
|
||||
|
||||
wm_latency_show(m, latencies);
|
||||
|
||||
@ -1457,9 +1458,9 @@ static int cur_wm_latency_show(struct seq_file *m, void *data)
|
||||
const u16 *latencies;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 9)
|
||||
latencies = dev_priv->wm.skl_latency;
|
||||
latencies = dev_priv->display.wm.skl_latency;
|
||||
else
|
||||
latencies = dev_priv->wm.cur_latency;
|
||||
latencies = dev_priv->display.wm.cur_latency;
|
||||
|
||||
wm_latency_show(m, latencies);
|
||||
|
||||
@ -1550,9 +1551,9 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
|
||||
u16 *latencies;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 9)
|
||||
latencies = dev_priv->wm.skl_latency;
|
||||
latencies = dev_priv->display.wm.skl_latency;
|
||||
else
|
||||
latencies = dev_priv->wm.pri_latency;
|
||||
latencies = dev_priv->display.wm.pri_latency;
|
||||
|
||||
return wm_latency_write(file, ubuf, len, offp, latencies);
|
||||
}
|
||||
@ -1565,9 +1566,9 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
|
||||
u16 *latencies;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 9)
|
||||
latencies = dev_priv->wm.skl_latency;
|
||||
latencies = dev_priv->display.wm.skl_latency;
|
||||
else
|
||||
latencies = dev_priv->wm.spr_latency;
|
||||
latencies = dev_priv->display.wm.spr_latency;
|
||||
|
||||
return wm_latency_write(file, ubuf, len, offp, latencies);
|
||||
}
|
||||
@ -1580,9 +1581,9 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
|
||||
u16 *latencies;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 9)
|
||||
latencies = dev_priv->wm.skl_latency;
|
||||
latencies = dev_priv->display.wm.skl_latency;
|
||||
else
|
||||
latencies = dev_priv->wm.cur_latency;
|
||||
latencies = dev_priv->display.wm.cur_latency;
|
||||
|
||||
return wm_latency_write(file, ubuf, len, offp, latencies);
|
||||
}
|
||||
@ -1617,14 +1618,14 @@ static const struct file_operations i915_cur_wm_latency_fops = {
|
||||
static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = m->private;
|
||||
struct i915_hotplug *hotplug = &dev_priv->hotplug;
|
||||
struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
|
||||
|
||||
/* Synchronize with everything first in case there's been an HPD
|
||||
* storm, but we haven't finished handling it in the kernel yet
|
||||
*/
|
||||
intel_synchronize_irq(dev_priv);
|
||||
flush_work(&dev_priv->hotplug.dig_port_work);
|
||||
flush_delayed_work(&dev_priv->hotplug.hotplug_work);
|
||||
flush_work(&dev_priv->display.hotplug.dig_port_work);
|
||||
flush_delayed_work(&dev_priv->display.hotplug.hotplug_work);
|
||||
|
||||
seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
|
||||
seq_printf(m, "Detected: %s\n",
|
||||
@ -1639,7 +1640,7 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
|
||||
{
|
||||
struct seq_file *m = file->private_data;
|
||||
struct drm_i915_private *dev_priv = m->private;
|
||||
struct i915_hotplug *hotplug = &dev_priv->hotplug;
|
||||
struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
|
||||
unsigned int new_threshold;
|
||||
int i;
|
||||
char *newline;
|
||||
@ -1678,7 +1679,7 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
|
||||
/* Re-enable hpd immediately if we were in an irq storm */
|
||||
flush_delayed_work(&dev_priv->hotplug.reenable_work);
|
||||
flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
|
||||
|
||||
return len;
|
||||
}
|
||||
@ -1702,7 +1703,7 @@ static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
|
||||
struct drm_i915_private *dev_priv = m->private;
|
||||
|
||||
seq_printf(m, "Enabled: %s\n",
|
||||
str_yes_no(dev_priv->hotplug.hpd_short_storm_enabled));
|
||||
str_yes_no(dev_priv->display.hotplug.hpd_short_storm_enabled));
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1720,7 +1721,7 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
|
||||
{
|
||||
struct seq_file *m = file->private_data;
|
||||
struct drm_i915_private *dev_priv = m->private;
|
||||
struct i915_hotplug *hotplug = &dev_priv->hotplug;
|
||||
struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
|
||||
char *newline;
|
||||
char tmp[16];
|
||||
int i;
|
||||
@ -1756,7 +1757,7 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
|
||||
/* Re-enable hpd immediately if we were in an irq storm */
|
||||
flush_delayed_work(&dev_priv->hotplug.reenable_work);
|
||||
flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
@ -7,6 +7,7 @@
|
||||
|
||||
#include "i915_drv.h"
|
||||
#include "i915_irq.h"
|
||||
#include "intel_backlight_regs.h"
|
||||
#include "intel_cdclk.h"
|
||||
#include "intel_combo_phy.h"
|
||||
#include "intel_de.h"
|
||||
@ -268,7 +269,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
|
||||
if (target_dc_state != states[i])
|
||||
continue;
|
||||
|
||||
if (dev_priv->dmc.allowed_dc_mask & target_dc_state)
|
||||
if (dev_priv->display.dmc.allowed_dc_mask & target_dc_state)
|
||||
break;
|
||||
|
||||
target_dc_state = states[i + 1];
|
||||
@ -301,7 +302,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
|
||||
|
||||
state = sanitize_target_dc_state(dev_priv, state);
|
||||
|
||||
if (state == dev_priv->dmc.target_dc_state)
|
||||
if (state == dev_priv->display.dmc.target_dc_state)
|
||||
goto unlock;
|
||||
|
||||
dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
|
||||
@ -312,7 +313,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
|
||||
if (!dc_off_enabled)
|
||||
intel_power_well_enable(dev_priv, power_well);
|
||||
|
||||
dev_priv->dmc.target_dc_state = state;
|
||||
dev_priv->display.dmc.target_dc_state = state;
|
||||
|
||||
if (!dc_off_enabled)
|
||||
intel_power_well_disable(dev_priv, power_well);
|
||||
@ -908,7 +909,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
|
||||
return 0;
|
||||
|
||||
if (IS_DG2(dev_priv))
|
||||
max_dc = 0;
|
||||
max_dc = 1;
|
||||
else if (IS_DG1(dev_priv))
|
||||
max_dc = 3;
|
||||
else if (DISPLAY_VER(dev_priv) >= 12)
|
||||
@ -981,10 +982,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
|
||||
dev_priv->params.disable_power_well =
|
||||
sanitize_disable_power_well_option(dev_priv,
|
||||
dev_priv->params.disable_power_well);
|
||||
dev_priv->dmc.allowed_dc_mask =
|
||||
dev_priv->display.dmc.allowed_dc_mask =
|
||||
get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
|
||||
|
||||
dev_priv->dmc.target_dc_state =
|
||||
dev_priv->display.dmc.target_dc_state =
|
||||
sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
|
||||
|
||||
mutex_init(&power_domains->lock);
|
||||
@ -1101,7 +1102,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
|
||||
unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
|
||||
u32 mask, val, i;
|
||||
|
||||
if (IS_ALDERLAKE_P(dev_priv))
|
||||
if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
|
||||
return;
|
||||
|
||||
mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
|
||||
@ -1381,6 +1382,9 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
|
||||
reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
|
||||
}
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 14)
|
||||
reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN;
|
||||
|
||||
val = intel_de_read(dev_priv, reg);
|
||||
|
||||
if (enable)
|
||||
@ -1433,6 +1437,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
|
||||
return;
|
||||
|
||||
gen9_disable_dc_states(dev_priv);
|
||||
/* TODO: disable DMC program */
|
||||
|
||||
gen9_dbuf_disable(dev_priv);
|
||||
|
||||
@ -1500,6 +1505,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
|
||||
return;
|
||||
|
||||
gen9_disable_dc_states(dev_priv);
|
||||
/* TODO: disable DMC program */
|
||||
|
||||
gen9_dbuf_disable(dev_priv);
|
||||
|
||||
@ -1675,6 +1681,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
|
||||
return;
|
||||
|
||||
gen9_disable_dc_states(dev_priv);
|
||||
intel_dmc_disable_program(dev_priv);
|
||||
|
||||
/* 1. Disable all display engine functions -> aready done */
|
||||
|
||||
@ -2039,7 +2046,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
|
||||
* resources as required and also enable deeper system power states
|
||||
* that would be blocked if the firmware was inactive.
|
||||
*/
|
||||
if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
|
||||
if (!(i915->display.dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
|
||||
suspend_mode == I915_DRM_SUSPEND_IDLE &&
|
||||
intel_dmc_has_payload(i915)) {
|
||||
intel_display_power_flush_work(i915);
|
||||
@ -2232,10 +2239,10 @@ void intel_display_power_resume(struct drm_i915_private *i915)
|
||||
bxt_disable_dc9(i915);
|
||||
icl_display_core_init(i915, true);
|
||||
if (intel_dmc_has_payload(i915)) {
|
||||
if (i915->dmc.allowed_dc_mask &
|
||||
if (i915->display.dmc.allowed_dc_mask &
|
||||
DC_STATE_EN_UPTO_DC6)
|
||||
skl_enable_dc6(i915);
|
||||
else if (i915->dmc.allowed_dc_mask &
|
||||
else if (i915->display.dmc.allowed_dc_mask &
|
||||
DC_STATE_EN_UPTO_DC5)
|
||||
gen9_enable_dc5(i915);
|
||||
}
|
||||
@ -2243,7 +2250,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
|
||||
bxt_disable_dc9(i915);
|
||||
bxt_display_core_init(i915, true);
|
||||
if (intel_dmc_has_payload(i915) &&
|
||||
(i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
|
||||
(i915->display.dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
|
||||
gen9_enable_dc5(i915);
|
||||
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
|
||||
hsw_disable_pc8(i915);
|
||||
|
@ -5,6 +5,7 @@
|
||||
|
||||
#include "i915_drv.h"
|
||||
#include "i915_irq.h"
|
||||
#include "intel_backlight_regs.h"
|
||||
#include "intel_combo_phy.h"
|
||||
#include "intel_combo_phy_regs.h"
|
||||
#include "intel_crt.h"
|
||||
@ -710,8 +711,8 @@ void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"Resetting DC state tracking from %02x to %02x\n",
|
||||
dev_priv->dmc.dc_state, val);
|
||||
dev_priv->dmc.dc_state = val;
|
||||
dev_priv->display.dmc.dc_state, val);
|
||||
dev_priv->display.dmc.dc_state = val;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -746,8 +747,8 @@ void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
|
||||
return;
|
||||
|
||||
if (drm_WARN_ON_ONCE(&dev_priv->drm,
|
||||
state & ~dev_priv->dmc.allowed_dc_mask))
|
||||
state &= dev_priv->dmc.allowed_dc_mask;
|
||||
state & ~dev_priv->display.dmc.allowed_dc_mask))
|
||||
state &= dev_priv->display.dmc.allowed_dc_mask;
|
||||
|
||||
val = intel_de_read(dev_priv, DC_STATE_EN);
|
||||
mask = gen9_dc_mask(dev_priv);
|
||||
@ -755,16 +756,16 @@ void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
|
||||
val & mask, state);
|
||||
|
||||
/* Check if DMC is ignoring our DC state requests */
|
||||
if ((val & mask) != dev_priv->dmc.dc_state)
|
||||
if ((val & mask) != dev_priv->display.dmc.dc_state)
|
||||
drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
|
||||
dev_priv->dmc.dc_state, val & mask);
|
||||
dev_priv->display.dmc.dc_state, val & mask);
|
||||
|
||||
val &= ~mask;
|
||||
val |= state;
|
||||
|
||||
gen9_write_dc_state(dev_priv, val);
|
||||
|
||||
dev_priv->dmc.dc_state = val & mask;
|
||||
dev_priv->display.dmc.dc_state = val & mask;
|
||||
}
|
||||
|
||||
static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
|
||||
@ -958,7 +959,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_cdclk_config cdclk_config = {};
|
||||
|
||||
if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
|
||||
if (dev_priv->display.dmc.target_dc_state == DC_STATE_EN_DC3CO) {
|
||||
tgl_disable_dc3co(dev_priv);
|
||||
return;
|
||||
}
|
||||
@ -1000,7 +1001,7 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
|
||||
if (!intel_dmc_has_payload(dev_priv))
|
||||
return;
|
||||
|
||||
switch (dev_priv->dmc.target_dc_state) {
|
||||
switch (dev_priv->display.dmc.target_dc_state) {
|
||||
case DC_STATE_EN_DC3CO:
|
||||
tgl_enable_dc3co(dev_priv);
|
||||
break;
|
||||
|
@ -52,8 +52,8 @@
|
||||
|
||||
#define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
|
||||
|
||||
#define DG2_DMC_PATH DMC_PATH(dg2, 2, 06)
|
||||
#define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 06)
|
||||
#define DG2_DMC_PATH DMC_PATH(dg2, 2, 07)
|
||||
#define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 07)
|
||||
MODULE_FIRMWARE(DG2_DMC_PATH);
|
||||
|
||||
#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 16)
|
||||
@ -250,7 +250,7 @@ struct stepping_info {
|
||||
|
||||
static bool has_dmc_id_fw(struct drm_i915_private *i915, int dmc_id)
|
||||
{
|
||||
return i915->dmc.dmc_info[dmc_id].payload;
|
||||
return i915->display.dmc.dmc_info[dmc_id].payload;
|
||||
}
|
||||
|
||||
bool intel_dmc_has_payload(struct drm_i915_private *i915)
|
||||
@ -277,6 +277,17 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
|
||||
intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
|
||||
}
|
||||
|
||||
static void disable_event_handler(struct drm_i915_private *i915,
|
||||
i915_reg_t ctl_reg, i915_reg_t htp_reg)
|
||||
{
|
||||
intel_de_write(i915, ctl_reg,
|
||||
REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
|
||||
DMC_EVT_CTL_TYPE_EDGE_0_1) |
|
||||
REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
|
||||
DMC_EVT_CTL_EVENT_ID_FALSE));
|
||||
intel_de_write(i915, htp_reg, 0);
|
||||
}
|
||||
|
||||
static void
|
||||
disable_flip_queue_event(struct drm_i915_private *i915,
|
||||
i915_reg_t ctl_reg, i915_reg_t htp_reg)
|
||||
@ -299,12 +310,7 @@ disable_flip_queue_event(struct drm_i915_private *i915,
|
||||
return;
|
||||
}
|
||||
|
||||
intel_de_write(i915, ctl_reg,
|
||||
REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
|
||||
DMC_EVT_CTL_TYPE_EDGE_0_1) |
|
||||
REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
|
||||
DMC_EVT_CTL_EVENT_ID_FALSE));
|
||||
intel_de_write(i915, htp_reg, 0);
|
||||
disable_event_handler(i915, ctl_reg, htp_reg);
|
||||
}
|
||||
|
||||
static bool
|
||||
@ -356,6 +362,51 @@ disable_all_flip_queue_events(struct drm_i915_private *i915)
|
||||
}
|
||||
}
|
||||
|
||||
static void disable_all_event_handlers(struct drm_i915_private *i915)
|
||||
{
|
||||
int id;
|
||||
|
||||
/* TODO: disable the event handlers on pre-GEN12 platforms as well */
|
||||
if (DISPLAY_VER(i915) < 12)
|
||||
return;
|
||||
|
||||
for (id = DMC_FW_MAIN; id < DMC_FW_MAX; id++) {
|
||||
int handler;
|
||||
|
||||
if (!has_dmc_id_fw(i915, id))
|
||||
continue;
|
||||
|
||||
for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++)
|
||||
disable_event_handler(i915,
|
||||
DMC_EVT_CTL(i915, id, handler),
|
||||
DMC_EVT_HTP(i915, id, handler));
|
||||
}
|
||||
}
|
||||
|
||||
static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
|
||||
{
|
||||
enum pipe pipe;
|
||||
|
||||
if (DISPLAY_VER(i915) != 13)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Wa_16015201720:adl-p,dg2
|
||||
* The WA requires clock gating to be disabled all the time
|
||||
* for pipe A and B.
|
||||
* For pipe C and D clock gating needs to be disabled only
|
||||
* during initializing the firmware.
|
||||
*/
|
||||
if (enable)
|
||||
for (pipe = PIPE_A; pipe <= PIPE_D; pipe++)
|
||||
intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe),
|
||||
0, PIPEDMC_GATING_DIS);
|
||||
else
|
||||
for (pipe = PIPE_C; pipe <= PIPE_D; pipe++)
|
||||
intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe),
|
||||
PIPEDMC_GATING_DIS, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_dmc_load_program() - write the firmware from memory to register.
|
||||
* @dev_priv: i915 drm device.
|
||||
@ -366,12 +417,16 @@ disable_all_flip_queue_events(struct drm_i915_private *i915)
|
||||
*/
|
||||
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_dmc *dmc = &dev_priv->dmc;
|
||||
struct intel_dmc *dmc = &dev_priv->display.dmc;
|
||||
u32 id, i;
|
||||
|
||||
if (!intel_dmc_has_payload(dev_priv))
|
||||
return;
|
||||
|
||||
pipedmc_clock_gating_wa(dev_priv, true);
|
||||
|
||||
disable_all_event_handlers(dev_priv);
|
||||
|
||||
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
|
||||
|
||||
preempt_disable();
|
||||
@ -393,7 +448,7 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
|
||||
}
|
||||
}
|
||||
|
||||
dev_priv->dmc.dc_state = 0;
|
||||
dev_priv->display.dmc.dc_state = 0;
|
||||
|
||||
gen9_set_dc_state_debugmask(dev_priv);
|
||||
|
||||
@ -403,12 +458,31 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
|
||||
* here.
|
||||
*/
|
||||
disable_all_flip_queue_events(dev_priv);
|
||||
|
||||
pipedmc_clock_gating_wa(dev_priv, false);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_dmc_disable_program() - disable the firmware
|
||||
* @i915: i915 drm device
|
||||
*
|
||||
* Disable all event handlers in the firmware, making sure the firmware is
|
||||
* inactive after the display is uninitialized.
|
||||
*/
|
||||
void intel_dmc_disable_program(struct drm_i915_private *i915)
|
||||
{
|
||||
if (!intel_dmc_has_payload(i915))
|
||||
return;
|
||||
|
||||
pipedmc_clock_gating_wa(i915, true);
|
||||
disable_all_event_handlers(i915);
|
||||
pipedmc_clock_gating_wa(i915, false);
|
||||
}
|
||||
|
||||
void assert_dmc_loaded(struct drm_i915_private *i915)
|
||||
{
|
||||
drm_WARN_ONCE(&i915->drm,
|
||||
!intel_de_read(i915, DMC_PROGRAM(i915->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
|
||||
!intel_de_read(i915, DMC_PROGRAM(i915->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
|
||||
"DMC program storage start is NULL\n");
|
||||
drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
|
||||
"DMC SSP Base Not fine\n");
|
||||
@ -445,7 +519,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
|
||||
{
|
||||
unsigned int i, id;
|
||||
|
||||
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
|
||||
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
|
||||
|
||||
for (i = 0; i < num_entries; i++) {
|
||||
id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
|
||||
@ -473,7 +547,7 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
|
||||
const u32 *mmioaddr, u32 mmio_count,
|
||||
int header_ver, u8 dmc_id)
|
||||
{
|
||||
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
|
||||
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
|
||||
u32 start_range, end_range;
|
||||
int i;
|
||||
|
||||
@ -511,7 +585,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
|
||||
const struct intel_dmc_header_base *dmc_header,
|
||||
size_t rem_size, u8 dmc_id)
|
||||
{
|
||||
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
|
||||
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
|
||||
struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
|
||||
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
|
||||
const u32 *mmioaddr, *mmiodata;
|
||||
@ -622,7 +696,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
|
||||
const struct stepping_info *si,
|
||||
size_t rem_size)
|
||||
{
|
||||
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
|
||||
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
|
||||
u32 package_size = sizeof(struct intel_package_header);
|
||||
u32 num_entries, max_entries;
|
||||
const struct intel_fw_info *fw_info;
|
||||
@ -676,7 +750,7 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
|
||||
struct intel_css_header *css_header,
|
||||
size_t rem_size)
|
||||
{
|
||||
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
|
||||
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
|
||||
|
||||
if (rem_size < sizeof(struct intel_css_header)) {
|
||||
drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
|
||||
@ -713,7 +787,7 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
|
||||
struct intel_css_header *css_header;
|
||||
struct intel_package_header *package_header;
|
||||
struct intel_dmc_header_base *dmc_header;
|
||||
struct intel_dmc *dmc = &dev_priv->dmc;
|
||||
struct intel_dmc *dmc = &dev_priv->display.dmc;
|
||||
struct stepping_info display_info = { '*', '*'};
|
||||
const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info);
|
||||
u32 readcount = 0;
|
||||
@ -740,7 +814,7 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
|
||||
readcount += r;
|
||||
|
||||
for (id = 0; id < DMC_FW_MAX; id++) {
|
||||
if (!dev_priv->dmc.dmc_info[id].present)
|
||||
if (!dev_priv->display.dmc.dmc_info[id].present)
|
||||
continue;
|
||||
|
||||
offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
|
||||
@ -756,15 +830,15 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
|
||||
|
||||
static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
|
||||
dev_priv->dmc.wakeref =
|
||||
drm_WARN_ON(&dev_priv->drm, dev_priv->display.dmc.wakeref);
|
||||
dev_priv->display.dmc.wakeref =
|
||||
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
|
||||
}
|
||||
|
||||
static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
intel_wakeref_t wakeref __maybe_unused =
|
||||
fetch_and_zero(&dev_priv->dmc.wakeref);
|
||||
fetch_and_zero(&dev_priv->display.dmc.wakeref);
|
||||
|
||||
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
|
||||
}
|
||||
@ -775,10 +849,10 @@ static void dmc_load_work_fn(struct work_struct *work)
|
||||
struct intel_dmc *dmc;
|
||||
const struct firmware *fw = NULL;
|
||||
|
||||
dev_priv = container_of(work, typeof(*dev_priv), dmc.work);
|
||||
dmc = &dev_priv->dmc;
|
||||
dev_priv = container_of(work, typeof(*dev_priv), display.dmc.work);
|
||||
dmc = &dev_priv->display.dmc;
|
||||
|
||||
request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
|
||||
request_firmware(&fw, dev_priv->display.dmc.fw_path, dev_priv->drm.dev);
|
||||
parse_dmc_fw(dev_priv, fw);
|
||||
|
||||
if (intel_dmc_has_payload(dev_priv)) {
|
||||
@ -787,7 +861,7 @@ static void dmc_load_work_fn(struct work_struct *work)
|
||||
|
||||
drm_info(&dev_priv->drm,
|
||||
"Finished loading DMC firmware %s (v%u.%u)\n",
|
||||
dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
|
||||
dev_priv->display.dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
|
||||
DMC_VERSION_MINOR(dmc->version));
|
||||
} else {
|
||||
drm_notice(&dev_priv->drm,
|
||||
@ -810,9 +884,9 @@ static void dmc_load_work_fn(struct work_struct *work)
|
||||
*/
|
||||
void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_dmc *dmc = &dev_priv->dmc;
|
||||
struct intel_dmc *dmc = &dev_priv->display.dmc;
|
||||
|
||||
INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn);
|
||||
INIT_WORK(&dev_priv->display.dmc.work, dmc_load_work_fn);
|
||||
|
||||
if (!HAS_DMC(dev_priv))
|
||||
return;
|
||||
@ -895,7 +969,7 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
|
||||
}
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
|
||||
schedule_work(&dev_priv->dmc.work);
|
||||
schedule_work(&dev_priv->display.dmc.work);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -911,7 +985,7 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv)
|
||||
if (!HAS_DMC(dev_priv))
|
||||
return;
|
||||
|
||||
flush_work(&dev_priv->dmc.work);
|
||||
flush_work(&dev_priv->display.dmc.work);
|
||||
|
||||
/* Drop the reference held in case DMC isn't loaded. */
|
||||
if (!intel_dmc_has_payload(dev_priv))
|
||||
@ -953,16 +1027,16 @@ void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
|
||||
return;
|
||||
|
||||
intel_dmc_ucode_suspend(dev_priv);
|
||||
drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
|
||||
drm_WARN_ON(&dev_priv->drm, dev_priv->display.dmc.wakeref);
|
||||
|
||||
for (id = 0; id < DMC_FW_MAX; id++)
|
||||
kfree(dev_priv->dmc.dmc_info[id].payload);
|
||||
kfree(dev_priv->display.dmc.dmc_info[id].payload);
|
||||
}
|
||||
|
||||
void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
|
||||
struct drm_i915_private *i915)
|
||||
{
|
||||
struct intel_dmc *dmc = &i915->dmc;
|
||||
struct intel_dmc *dmc = &i915->display.dmc;
|
||||
|
||||
if (!HAS_DMC(i915))
|
||||
return;
|
||||
@ -984,7 +1058,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
|
||||
if (!HAS_DMC(i915))
|
||||
return -ENODEV;
|
||||
|
||||
dmc = &i915->dmc;
|
||||
dmc = &i915->display.dmc;
|
||||
|
||||
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
|
||||
|
||||
|
@ -47,6 +47,7 @@ struct intel_dmc {
|
||||
|
||||
void intel_dmc_ucode_init(struct drm_i915_private *i915);
|
||||
void intel_dmc_load_program(struct drm_i915_private *i915);
|
||||
void intel_dmc_disable_program(struct drm_i915_private *i915);
|
||||
void intel_dmc_ucode_fini(struct drm_i915_private *i915);
|
||||
void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
|
||||
void intel_dmc_ucode_resume(struct drm_i915_private *i915);
|
||||
|
@ -28,6 +28,8 @@
|
||||
#define _DMC_REG(i915, dmc_id, reg) \
|
||||
((reg) - __DMC_REG_MMIO_BASE + _DMC_REG_MMIO_BASE(i915, dmc_id))
|
||||
|
||||
#define DMC_EVENT_HANDLER_COUNT_GEN12 8
|
||||
|
||||
#define _DMC_EVT_HTP_0 0x8f004
|
||||
|
||||
#define DMC_EVT_HTP(i915, dmc_id, handler) \
|
||||
|
@ -1377,7 +1377,18 @@ static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define DSC_SUPPORTED_VERSION_MIN 1
|
||||
static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
|
||||
|
||||
return DISPLAY_VER(i915) >= 14 ? 2 : 1;
|
||||
}
|
||||
|
||||
static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
|
||||
{
|
||||
return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
|
||||
DP_DSC_MINOR_SHIFT;
|
||||
}
|
||||
|
||||
static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
|
||||
struct intel_crtc_state *crtc_state)
|
||||
@ -1416,9 +1427,8 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
|
||||
(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
|
||||
DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
|
||||
vdsc_cfg->dsc_version_minor =
|
||||
min(DSC_SUPPORTED_VERSION_MIN,
|
||||
(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
|
||||
DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
|
||||
min(intel_dp_source_dsc_version_minor(intel_dp),
|
||||
intel_dp_sink_dsc_version_minor(intel_dp));
|
||||
|
||||
vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
|
||||
DP_DSC_RGB;
|
||||
@ -5032,9 +5042,9 @@ static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
|
||||
struct drm_i915_private *i915 = to_i915(connector->dev);
|
||||
|
||||
spin_lock_irq(&i915->irq_lock);
|
||||
i915->hotplug.event_bits |= BIT(encoder->hpd_pin);
|
||||
i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
|
||||
spin_unlock_irq(&i915->irq_lock);
|
||||
queue_delayed_work(system_wq, &i915->hotplug.hotplug_work, 0);
|
||||
queue_delayed_work(system_wq, &i915->display.hotplug.hotplug_work, 0);
|
||||
}
|
||||
|
||||
static const struct drm_connector_funcs intel_dp_connector_funcs = {
|
||||
@ -5302,8 +5312,6 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
|
||||
|
||||
intel_panel_init(intel_connector);
|
||||
|
||||
if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
|
||||
intel_connector->panel.backlight.power = intel_pps_backlight_power;
|
||||
intel_backlight_setup(intel_connector, pipe);
|
||||
|
||||
intel_edp_add_properties(intel_dp);
|
||||
|
@ -42,7 +42,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
|
||||
bool done;
|
||||
|
||||
#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
||||
done = wait_event_timeout(i915->gmbus_wait_queue, C,
|
||||
done = wait_event_timeout(i915->display.gmbus.wait_queue, C,
|
||||
msecs_to_jiffies_timeout(timeout_ms));
|
||||
|
||||
/* just trace the final value */
|
||||
|
@ -17,6 +17,7 @@
|
||||
#include "intel_dp.h"
|
||||
#include "intel_dp_hdcp.h"
|
||||
#include "intel_hdcp.h"
|
||||
#include "intel_hdcp_regs.h"
|
||||
|
||||
static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
|
||||
{
|
||||
|
@ -1420,7 +1420,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
|
||||
if (!crtc_state->hw.enable)
|
||||
return 0;
|
||||
|
||||
ret = i915->dpll_funcs->crtc_compute_clock(state, crtc);
|
||||
ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc);
|
||||
if (ret) {
|
||||
drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
|
||||
crtc->base.base.id, crtc->base.name);
|
||||
@ -1446,10 +1446,10 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
|
||||
if (!crtc_state->hw.enable)
|
||||
return 0;
|
||||
|
||||
if (!i915->dpll_funcs->crtc_get_shared_dpll)
|
||||
if (!i915->display.funcs.dpll->crtc_get_shared_dpll)
|
||||
return 0;
|
||||
|
||||
ret = i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
|
||||
ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc);
|
||||
if (ret) {
|
||||
drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
|
||||
crtc->base.base.id, crtc->base.name);
|
||||
@ -1463,23 +1463,23 @@ void
|
||||
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if (IS_DG2(dev_priv))
|
||||
dev_priv->dpll_funcs = &dg2_dpll_funcs;
|
||||
dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
|
||||
else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
|
||||
dev_priv->dpll_funcs = &hsw_dpll_funcs;
|
||||
dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
|
||||
else if (HAS_PCH_SPLIT(dev_priv))
|
||||
dev_priv->dpll_funcs = &ilk_dpll_funcs;
|
||||
dev_priv->display.funcs.dpll = &ilk_dpll_funcs;
|
||||
else if (IS_CHERRYVIEW(dev_priv))
|
||||
dev_priv->dpll_funcs = &chv_dpll_funcs;
|
||||
dev_priv->display.funcs.dpll = &chv_dpll_funcs;
|
||||
else if (IS_VALLEYVIEW(dev_priv))
|
||||
dev_priv->dpll_funcs = &vlv_dpll_funcs;
|
||||
dev_priv->display.funcs.dpll = &vlv_dpll_funcs;
|
||||
else if (IS_G4X(dev_priv))
|
||||
dev_priv->dpll_funcs = &g4x_dpll_funcs;
|
||||
dev_priv->display.funcs.dpll = &g4x_dpll_funcs;
|
||||
else if (IS_PINEVIEW(dev_priv))
|
||||
dev_priv->dpll_funcs = &pnv_dpll_funcs;
|
||||
dev_priv->display.funcs.dpll = &pnv_dpll_funcs;
|
||||
else if (DISPLAY_VER(dev_priv) != 2)
|
||||
dev_priv->dpll_funcs = &i9xx_dpll_funcs;
|
||||
dev_priv->display.funcs.dpll = &i9xx_dpll_funcs;
|
||||
else
|
||||
dev_priv->dpll_funcs = &i8xx_dpll_funcs;
|
||||
dev_priv->display.funcs.dpll = &i8xx_dpll_funcs;
|
||||
}
|
||||
|
||||
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
|
||||
|
@ -113,8 +113,8 @@ intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
|
||||
enum intel_dpll_id i;
|
||||
|
||||
/* Copy shared dpll state */
|
||||
for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
|
||||
struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
|
||||
for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
|
||||
struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
|
||||
|
||||
shared_dpll[i] = pll->state;
|
||||
}
|
||||
@ -149,7 +149,7 @@ struct intel_shared_dpll *
|
||||
intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
|
||||
enum intel_dpll_id id)
|
||||
{
|
||||
return &dev_priv->dpll.shared_dplls[id];
|
||||
return &dev_priv->display.dpll.shared_dplls[id];
|
||||
}
|
||||
|
||||
/**
|
||||
@ -164,11 +164,11 @@ enum intel_dpll_id
|
||||
intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
|
||||
struct intel_shared_dpll *pll)
|
||||
{
|
||||
long pll_idx = pll - dev_priv->dpll.shared_dplls;
|
||||
long pll_idx = pll - dev_priv->display.dpll.shared_dplls;
|
||||
|
||||
if (drm_WARN_ON(&dev_priv->drm,
|
||||
pll_idx < 0 ||
|
||||
pll_idx >= dev_priv->dpll.num_shared_dpll))
|
||||
pll_idx >= dev_priv->display.dpll.num_shared_dpll))
|
||||
return -1;
|
||||
|
||||
return pll_idx;
|
||||
@ -245,7 +245,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
|
||||
if (drm_WARN_ON(&dev_priv->drm, pll == NULL))
|
||||
return;
|
||||
|
||||
mutex_lock(&dev_priv->dpll.lock);
|
||||
mutex_lock(&dev_priv->display.dpll.lock);
|
||||
old_mask = pll->active_mask;
|
||||
|
||||
if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) ||
|
||||
@ -271,7 +271,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
|
||||
pll->on = true;
|
||||
|
||||
out:
|
||||
mutex_unlock(&dev_priv->dpll.lock);
|
||||
mutex_unlock(&dev_priv->display.dpll.lock);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -294,7 +294,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
|
||||
if (pll == NULL)
|
||||
return;
|
||||
|
||||
mutex_lock(&dev_priv->dpll.lock);
|
||||
mutex_lock(&dev_priv->display.dpll.lock);
|
||||
if (drm_WARN(&dev_priv->drm, !(pll->active_mask & pipe_mask),
|
||||
"%s not used by [CRTC:%d:%s]\n", pll->info->name,
|
||||
crtc->base.base.id, crtc->base.name))
|
||||
@ -317,7 +317,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
|
||||
pll->on = false;
|
||||
|
||||
out:
|
||||
mutex_unlock(&dev_priv->dpll.lock);
|
||||
mutex_unlock(&dev_priv->display.dpll.lock);
|
||||
}
|
||||
|
||||
static struct intel_shared_dpll *
|
||||
@ -336,7 +336,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
|
||||
drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
|
||||
|
||||
for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
|
||||
pll = &dev_priv->dpll.shared_dplls[i];
|
||||
pll = &dev_priv->display.dpll.shared_dplls[i];
|
||||
|
||||
/* Only want to check enabled timings first */
|
||||
if (shared_dpll[i].pipe_mask == 0) {
|
||||
@ -436,9 +436,9 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
|
||||
if (!state->dpll_set)
|
||||
return;
|
||||
|
||||
for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
|
||||
for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
|
||||
struct intel_shared_dpll *pll =
|
||||
&dev_priv->dpll.shared_dplls[i];
|
||||
&dev_priv->display.dpll.shared_dplls[i];
|
||||
|
||||
swap(pll->state, shared_dpll[i]);
|
||||
}
|
||||
@ -537,7 +537,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
|
||||
if (HAS_PCH_IBX(dev_priv)) {
|
||||
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
|
||||
i = (enum intel_dpll_id) crtc->pipe;
|
||||
pll = &dev_priv->dpll.shared_dplls[i];
|
||||
pll = &dev_priv->display.dpll.shared_dplls[i];
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"[CRTC:%d:%s] using pre-allocated %s\n",
|
||||
@ -948,7 +948,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
|
||||
case WRPLL_REF_SPECIAL_HSW:
|
||||
/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
|
||||
if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
|
||||
refclk = dev_priv->dpll.ref_clks.nssc;
|
||||
refclk = dev_priv->display.dpll.ref_clks.nssc;
|
||||
break;
|
||||
}
|
||||
fallthrough;
|
||||
@ -958,7 +958,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
|
||||
* code only cares about 5% accuracy, and spread is a max of
|
||||
* 0.5% downspread.
|
||||
*/
|
||||
refclk = dev_priv->dpll.ref_clks.ssc;
|
||||
refclk = dev_priv->display.dpll.ref_clks.ssc;
|
||||
break;
|
||||
case WRPLL_REF_LCPLL:
|
||||
refclk = 2700000;
|
||||
@ -1145,12 +1145,12 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
|
||||
|
||||
static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
|
||||
{
|
||||
i915->dpll.ref_clks.ssc = 135000;
|
||||
i915->display.dpll.ref_clks.ssc = 135000;
|
||||
/* Non-SSC is only used on non-ULT HSW. */
|
||||
if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
|
||||
i915->dpll.ref_clks.nssc = 24000;
|
||||
i915->display.dpll.ref_clks.nssc = 24000;
|
||||
else
|
||||
i915->dpll.ref_clks.nssc = 135000;
|
||||
i915->display.dpll.ref_clks.nssc = 135000;
|
||||
}
|
||||
|
||||
static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
|
||||
@ -1634,7 +1634,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
|
||||
ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
|
||||
|
||||
ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
|
||||
i915->dpll.ref_clks.nssc, &wrpll_params);
|
||||
i915->display.dpll.ref_clks.nssc, &wrpll_params);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -1659,7 +1659,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
|
||||
const struct intel_shared_dpll *pll,
|
||||
const struct intel_dpll_hw_state *pll_state)
|
||||
{
|
||||
int ref_clock = i915->dpll.ref_clks.nssc;
|
||||
int ref_clock = i915->display.dpll.ref_clks.nssc;
|
||||
u32 p0, p1, p2, dco_freq;
|
||||
|
||||
p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
|
||||
@ -1858,7 +1858,7 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
|
||||
static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
|
||||
{
|
||||
/* No SSC ref */
|
||||
i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
|
||||
i915->display.dpll.ref_clks.nssc = i915->cdclk.hw.ref;
|
||||
}
|
||||
|
||||
static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
|
||||
@ -2171,7 +2171,7 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
|
||||
}
|
||||
}
|
||||
|
||||
chv_calc_dpll_params(i915->dpll.ref_clks.nssc, clk_div);
|
||||
chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div);
|
||||
|
||||
drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
|
||||
clk_div->dot != crtc_state->port_clock);
|
||||
@ -2279,7 +2279,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
|
||||
clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, pll_state->ebb0);
|
||||
clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, pll_state->ebb0);
|
||||
|
||||
return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
|
||||
return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock);
|
||||
}
|
||||
|
||||
static int bxt_compute_dpll(struct intel_atomic_state *state,
|
||||
@ -2324,8 +2324,8 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
|
||||
|
||||
static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
|
||||
{
|
||||
i915->dpll.ref_clks.ssc = 100000;
|
||||
i915->dpll.ref_clks.nssc = 100000;
|
||||
i915->display.dpll.ref_clks.ssc = 100000;
|
||||
i915->display.dpll.ref_clks.nssc = 100000;
|
||||
/* DSI non-SSC ref 19.2MHz */
|
||||
}
|
||||
|
||||
@ -2468,7 +2468,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
|
||||
return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
|
||||
IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
|
||||
IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
|
||||
i915->dpll.ref_clks.nssc == 38400;
|
||||
i915->display.dpll.ref_clks.nssc == 38400;
|
||||
}
|
||||
|
||||
struct icl_combo_pll_params {
|
||||
@ -2562,7 +2562,7 @@ static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
||||
const struct icl_combo_pll_params *params =
|
||||
dev_priv->dpll.ref_clks.nssc == 24000 ?
|
||||
dev_priv->display.dpll.ref_clks.nssc == 24000 ?
|
||||
icl_dp_combo_pll_24MHz_values :
|
||||
icl_dp_combo_pll_19_2MHz_values;
|
||||
int clock = crtc_state->port_clock;
|
||||
@ -2585,9 +2585,9 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12) {
|
||||
switch (dev_priv->dpll.ref_clks.nssc) {
|
||||
switch (dev_priv->display.dpll.ref_clks.nssc) {
|
||||
default:
|
||||
MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
|
||||
MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc);
|
||||
fallthrough;
|
||||
case 19200:
|
||||
case 38400:
|
||||
@ -2598,9 +2598,9 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (dev_priv->dpll.ref_clks.nssc) {
|
||||
switch (dev_priv->display.dpll.ref_clks.nssc) {
|
||||
default:
|
||||
MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
|
||||
MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc);
|
||||
fallthrough;
|
||||
case 19200:
|
||||
case 38400:
|
||||
@ -2630,7 +2630,7 @@ static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
|
||||
|
||||
static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
|
||||
{
|
||||
int ref_clock = i915->dpll.ref_clks.nssc;
|
||||
int ref_clock = i915->display.dpll.ref_clks.nssc;
|
||||
|
||||
/*
|
||||
* For ICL+, the spec states: if reference frequency is 38.4,
|
||||
@ -2857,7 +2857,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
|
||||
struct intel_dpll_hw_state *pll_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
||||
int refclk_khz = dev_priv->dpll.ref_clks.nssc;
|
||||
int refclk_khz = dev_priv->display.dpll.ref_clks.nssc;
|
||||
int clock = crtc_state->port_clock;
|
||||
u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
|
||||
u32 iref_ndiv, iref_trim, iref_pulse_w;
|
||||
@ -3063,7 +3063,7 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
|
||||
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
|
||||
u64 tmp;
|
||||
|
||||
ref_clock = dev_priv->dpll.ref_clks.nssc;
|
||||
ref_clock = dev_priv->display.dpll.ref_clks.nssc;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12) {
|
||||
m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
|
||||
@ -3440,7 +3440,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
|
||||
hw_state->mg_pll_tdc_coldst_bias =
|
||||
intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
|
||||
|
||||
if (dev_priv->dpll.ref_clks.nssc == 38400) {
|
||||
if (dev_priv->display.dpll.ref_clks.nssc == 38400) {
|
||||
hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
|
||||
hw_state->mg_pll_bias_mask = 0;
|
||||
} else {
|
||||
@ -3967,7 +3967,7 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
|
||||
static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
|
||||
{
|
||||
/* No SSC ref */
|
||||
i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
|
||||
i915->display.dpll.ref_clks.nssc = i915->cdclk.hw.ref;
|
||||
}
|
||||
|
||||
static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
|
||||
@ -4192,7 +4192,7 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
|
||||
dpll_mgr = &pch_pll_mgr;
|
||||
|
||||
if (!dpll_mgr) {
|
||||
dev_priv->dpll.num_shared_dpll = 0;
|
||||
dev_priv->display.dpll.num_shared_dpll = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
@ -4200,14 +4200,14 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
|
||||
|
||||
for (i = 0; dpll_info[i].name; i++) {
|
||||
drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id);
|
||||
dev_priv->dpll.shared_dplls[i].info = &dpll_info[i];
|
||||
dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i];
|
||||
}
|
||||
|
||||
dev_priv->dpll.mgr = dpll_mgr;
|
||||
dev_priv->dpll.num_shared_dpll = i;
|
||||
mutex_init(&dev_priv->dpll.lock);
|
||||
dev_priv->display.dpll.mgr = dpll_mgr;
|
||||
dev_priv->display.dpll.num_shared_dpll = i;
|
||||
mutex_init(&dev_priv->display.dpll.lock);
|
||||
|
||||
BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
|
||||
BUG_ON(dev_priv->display.dpll.num_shared_dpll > I915_NUM_PLLS);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -4229,7 +4229,7 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
|
||||
const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
|
||||
|
||||
if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
|
||||
return -EINVAL;
|
||||
@ -4262,7 +4262,7 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
|
||||
const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
|
||||
|
||||
if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
|
||||
return -EINVAL;
|
||||
@ -4285,7 +4285,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
|
||||
const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
|
||||
|
||||
/*
|
||||
* FIXME: this function is called for every platform having a
|
||||
@ -4314,7 +4314,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
|
||||
struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
|
||||
const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
|
||||
|
||||
if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
|
||||
return;
|
||||
@ -4385,16 +4385,16 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
|
||||
|
||||
void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
|
||||
{
|
||||
if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
|
||||
i915->dpll.mgr->update_ref_clks(i915);
|
||||
if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks)
|
||||
i915->display.dpll.mgr->update_ref_clks(i915);
|
||||
}
|
||||
|
||||
void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < i915->dpll.num_shared_dpll; i++)
|
||||
readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
|
||||
for (i = 0; i < i915->display.dpll.num_shared_dpll; i++)
|
||||
readout_dpll_hw_state(i915, &i915->display.dpll.shared_dplls[i]);
|
||||
}
|
||||
|
||||
static void sanitize_dpll_state(struct drm_i915_private *i915,
|
||||
@ -4420,8 +4420,8 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < i915->dpll.num_shared_dpll; i++)
|
||||
sanitize_dpll_state(i915, &i915->dpll.shared_dplls[i]);
|
||||
for (i = 0; i < i915->display.dpll.num_shared_dpll; i++)
|
||||
sanitize_dpll_state(i915, &i915->display.dpll.shared_dplls[i]);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -4434,8 +4434,8 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
|
||||
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
|
||||
const struct intel_dpll_hw_state *hw_state)
|
||||
{
|
||||
if (dev_priv->dpll.mgr) {
|
||||
dev_priv->dpll.mgr->dump_hw_state(dev_priv, hw_state);
|
||||
if (dev_priv->display.dpll.mgr) {
|
||||
dev_priv->display.dpll.mgr->dump_hw_state(dev_priv, hw_state);
|
||||
} else {
|
||||
/* fallback for platforms that don't use the shared dpll
|
||||
* infrastructure
|
||||
@ -4533,7 +4533,7 @@ void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < i915->dpll.num_shared_dpll; i++)
|
||||
verify_single_dpll_state(i915, &i915->dpll.shared_dplls[i],
|
||||
for (i = 0; i < i915->display.dpll.num_shared_dpll; i++)
|
||||
verify_single_dpll_state(i915, &i915->display.dpll.shared_dplls[i],
|
||||
NULL, NULL);
|
||||
}
|
||||
|
@ -89,9 +89,6 @@ struct intel_dsi {
|
||||
u8 escape_clk_div;
|
||||
u8 dual_link;
|
||||
|
||||
u16 dcs_backlight_ports;
|
||||
u16 dcs_cabc_ports;
|
||||
|
||||
/* RGB or BGR */
|
||||
bool bgr_enabled;
|
||||
|
||||
|
@ -53,7 +53,7 @@ static u32 dcs_get_backlight(struct intel_connector *connector, enum pipe unused
|
||||
enum port port;
|
||||
size_t len = panel->backlight.max > U8_MAX ? 2 : 1;
|
||||
|
||||
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
|
||||
for_each_dsi_port(port, panel->vbt.dsi.bl_ports) {
|
||||
dsi_device = intel_dsi->dsi_hosts[port]->device;
|
||||
mipi_dsi_dcs_read(dsi_device, MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
|
||||
&data, len);
|
||||
@ -80,7 +80,7 @@ static void dcs_set_backlight(const struct drm_connector_state *conn_state, u32
|
||||
data[1] = level;
|
||||
}
|
||||
|
||||
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
|
||||
for_each_dsi_port(port, panel->vbt.dsi.bl_ports) {
|
||||
dsi_device = intel_dsi->dsi_hosts[port]->device;
|
||||
mode_flags = dsi_device->mode_flags;
|
||||
dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
|
||||
@ -93,12 +93,13 @@ static void dcs_set_backlight(const struct drm_connector_state *conn_state, u32
|
||||
static void dcs_disable_backlight(const struct drm_connector_state *conn_state, u32 level)
|
||||
{
|
||||
struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder));
|
||||
struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel;
|
||||
struct mipi_dsi_device *dsi_device;
|
||||
enum port port;
|
||||
|
||||
dcs_set_backlight(conn_state, 0);
|
||||
|
||||
for_each_dsi_port(port, intel_dsi->dcs_cabc_ports) {
|
||||
for_each_dsi_port(port, panel->vbt.dsi.cabc_ports) {
|
||||
u8 cabc = POWER_SAVE_OFF;
|
||||
|
||||
dsi_device = intel_dsi->dsi_hosts[port]->device;
|
||||
@ -106,7 +107,7 @@ static void dcs_disable_backlight(const struct drm_connector_state *conn_state,
|
||||
&cabc, sizeof(cabc));
|
||||
}
|
||||
|
||||
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
|
||||
for_each_dsi_port(port, panel->vbt.dsi.bl_ports) {
|
||||
u8 ctrl = 0;
|
||||
|
||||
dsi_device = intel_dsi->dsi_hosts[port]->device;
|
||||
@ -127,10 +128,11 @@ static void dcs_enable_backlight(const struct intel_crtc_state *crtc_state,
|
||||
const struct drm_connector_state *conn_state, u32 level)
|
||||
{
|
||||
struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder));
|
||||
struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel;
|
||||
struct mipi_dsi_device *dsi_device;
|
||||
enum port port;
|
||||
|
||||
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
|
||||
for_each_dsi_port(port, panel->vbt.dsi.bl_ports) {
|
||||
u8 ctrl = 0;
|
||||
|
||||
dsi_device = intel_dsi->dsi_hosts[port]->device;
|
||||
@ -146,7 +148,7 @@ static void dcs_enable_backlight(const struct intel_crtc_state *crtc_state,
|
||||
&ctrl, sizeof(ctrl));
|
||||
}
|
||||
|
||||
for_each_dsi_port(port, intel_dsi->dcs_cabc_ports) {
|
||||
for_each_dsi_port(port, panel->vbt.dsi.cabc_ports) {
|
||||
u8 cabc = POWER_SAVE_MEDIUM;
|
||||
|
||||
dsi_device = intel_dsi->dsi_hosts[port]->device;
|
||||
|
@ -55,7 +55,7 @@
|
||||
|
||||
#define for_each_fbc_id(__dev_priv, __fbc_id) \
|
||||
for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
|
||||
for_each_if(INTEL_INFO(__dev_priv)->display.fbc_mask & BIT(__fbc_id))
|
||||
for_each_if(RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
|
||||
|
||||
#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
|
||||
for_each_fbc_id((__dev_priv), (__fbc_id)) \
|
||||
@ -1098,6 +1098,12 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Wa_14016291713 */
|
||||
if (IS_DISPLAY_VER(i915, 12, 13) && crtc_state->has_psr) {
|
||||
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!pixel_format_is_valid(plane_state)) {
|
||||
plane_state->no_fbc_reason = "pixel format not supported";
|
||||
return 0;
|
||||
@ -1704,10 +1710,10 @@ void intel_fbc_init(struct drm_i915_private *i915)
|
||||
enum intel_fbc_id fbc_id;
|
||||
|
||||
if (!drm_mm_initialized(&i915->mm.stolen))
|
||||
mkwrite_device_info(i915)->display.fbc_mask = 0;
|
||||
RUNTIME_INFO(i915)->fbc_mask = 0;
|
||||
|
||||
if (need_fbc_vtd_wa(i915))
|
||||
mkwrite_device_info(i915)->display.fbc_mask = 0;
|
||||
RUNTIME_INFO(i915)->fbc_mask = 0;
|
||||
|
||||
i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
|
||||
drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
|
||||
|
@ -19,6 +19,7 @@ struct intel_plane_state;
|
||||
|
||||
enum intel_fbc_id {
|
||||
INTEL_FBC_A,
|
||||
INTEL_FBC_B,
|
||||
|
||||
I915_MAX_FBCS,
|
||||
};
|
||||
|
@ -500,7 +500,7 @@ static void intel_fbdev_suspend_worker(struct work_struct *work)
|
||||
{
|
||||
intel_fbdev_set_suspend(&container_of(work,
|
||||
struct drm_i915_private,
|
||||
fbdev_suspend_work)->drm,
|
||||
display.fbdev.suspend_work)->drm,
|
||||
FBINFO_STATE_RUNNING,
|
||||
true);
|
||||
}
|
||||
@ -530,8 +530,8 @@ int intel_fbdev_init(struct drm_device *dev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_priv->fbdev = ifbdev;
|
||||
INIT_WORK(&dev_priv->fbdev_suspend_work, intel_fbdev_suspend_worker);
|
||||
dev_priv->display.fbdev.fbdev = ifbdev;
|
||||
INIT_WORK(&dev_priv->display.fbdev.suspend_work, intel_fbdev_suspend_worker);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -548,7 +548,7 @@ static void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
|
||||
|
||||
void intel_fbdev_initial_config_async(struct drm_device *dev)
|
||||
{
|
||||
struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
|
||||
struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev;
|
||||
|
||||
if (!ifbdev)
|
||||
return;
|
||||
@ -568,12 +568,12 @@ static void intel_fbdev_sync(struct intel_fbdev *ifbdev)
|
||||
|
||||
void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_fbdev *ifbdev = dev_priv->fbdev;
|
||||
struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;
|
||||
|
||||
if (!ifbdev)
|
||||
return;
|
||||
|
||||
cancel_work_sync(&dev_priv->fbdev_suspend_work);
|
||||
cancel_work_sync(&dev_priv->display.fbdev.suspend_work);
|
||||
if (!current_is_async())
|
||||
intel_fbdev_sync(ifbdev);
|
||||
|
||||
@ -582,7 +582,7 @@ void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
|
||||
|
||||
void intel_fbdev_fini(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->fbdev);
|
||||
struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->display.fbdev.fbdev);
|
||||
|
||||
if (!ifbdev)
|
||||
return;
|
||||
@ -596,7 +596,7 @@ void intel_fbdev_fini(struct drm_i915_private *dev_priv)
|
||||
*/
|
||||
static void intel_fbdev_hpd_set_suspend(struct drm_i915_private *i915, int state)
|
||||
{
|
||||
struct intel_fbdev *ifbdev = i915->fbdev;
|
||||
struct intel_fbdev *ifbdev = i915->display.fbdev.fbdev;
|
||||
bool send_hpd = false;
|
||||
|
||||
mutex_lock(&ifbdev->hpd_lock);
|
||||
@ -614,7 +614,7 @@ static void intel_fbdev_hpd_set_suspend(struct drm_i915_private *i915, int state
|
||||
void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct intel_fbdev *ifbdev = dev_priv->fbdev;
|
||||
struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;
|
||||
struct fb_info *info;
|
||||
|
||||
if (!ifbdev || !ifbdev->vma)
|
||||
@ -631,7 +631,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
|
||||
* ourselves, so only flush outstanding work upon suspend!
|
||||
*/
|
||||
if (state != FBINFO_STATE_RUNNING)
|
||||
flush_work(&dev_priv->fbdev_suspend_work);
|
||||
flush_work(&dev_priv->display.fbdev.suspend_work);
|
||||
|
||||
console_lock();
|
||||
} else {
|
||||
@ -645,7 +645,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
|
||||
/* Don't block our own workqueue as this can
|
||||
* be run in parallel with other i915.ko tasks.
|
||||
*/
|
||||
schedule_work(&dev_priv->fbdev_suspend_work);
|
||||
schedule_work(&dev_priv->display.fbdev.suspend_work);
|
||||
return;
|
||||
}
|
||||
}
|
||||
@ -666,7 +666,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
|
||||
|
||||
void intel_fbdev_output_poll_changed(struct drm_device *dev)
|
||||
{
|
||||
struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
|
||||
struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev;
|
||||
bool send_hpd;
|
||||
|
||||
if (!ifbdev)
|
||||
@ -685,7 +685,7 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev)
|
||||
|
||||
void intel_fbdev_restore_mode(struct drm_device *dev)
|
||||
{
|
||||
struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
|
||||
struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev;
|
||||
|
||||
if (!ifbdev)
|
||||
return;
|
||||
|
@ -113,7 +113,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
|
||||
dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
|
||||
dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state);
|
||||
}
|
||||
|
||||
/* units of 100MHz */
|
||||
@ -1066,11 +1066,11 @@ void
|
||||
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if (IS_IRONLAKE(dev_priv)) {
|
||||
dev_priv->fdi_funcs = &ilk_funcs;
|
||||
dev_priv->display.funcs.fdi = &ilk_funcs;
|
||||
} else if (IS_SANDYBRIDGE(dev_priv)) {
|
||||
dev_priv->fdi_funcs = &gen6_funcs;
|
||||
dev_priv->display.funcs.fdi = &gen6_funcs;
|
||||
} else if (IS_IVYBRIDGE(dev_priv)) {
|
||||
/* FIXME: detect B0+ stepping and use auto training */
|
||||
dev_priv->fdi_funcs = &ivb_funcs;
|
||||
dev_priv->display.funcs.fdi = &ivb_funcs;
|
||||
}
|
||||
}
|
||||
|
@ -311,6 +311,8 @@ void intel_frontbuffer_track(struct intel_frontbuffer *old,
|
||||
*/
|
||||
BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
|
||||
BITS_PER_TYPE(atomic_t));
|
||||
BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32);
|
||||
BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE);
|
||||
|
||||
if (old) {
|
||||
drm_WARN_ON(old->obj->base.dev,
|
||||
|
@ -25,6 +25,7 @@
|
||||
#define __INTEL_FRONTBUFFER_H__
|
||||
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/bits.h>
|
||||
#include <linux/kref.h>
|
||||
|
||||
#include "gem/i915_gem_object_types.h"
|
||||
@ -48,6 +49,23 @@ struct intel_frontbuffer {
|
||||
struct rcu_head rcu;
|
||||
};
|
||||
|
||||
/*
|
||||
* Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
|
||||
* considered to be the frontbuffer for the given plane interface-wise. This
|
||||
* doesn't mean that the hw necessarily already scans it out, but that any
|
||||
* rendering (by the cpu or gpu) will land in the frontbuffer eventually.
|
||||
*
|
||||
* We have one bit per pipe and per scanout plane type.
|
||||
*/
|
||||
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
|
||||
#define INTEL_FRONTBUFFER(pipe, plane_id) \
|
||||
BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe));
|
||||
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
|
||||
BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
|
||||
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
|
||||
GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
|
||||
INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
|
||||
|
||||
void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915,
|
||||
unsigned frontbuffer_bits);
|
||||
void intel_frontbuffer_flip_complete(struct drm_i915_private *i915,
|
||||
|
@ -369,7 +369,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
|
||||
if (!has_gmbus_irq(dev_priv))
|
||||
irq_en = 0;
|
||||
|
||||
add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
|
||||
add_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
|
||||
intel_de_write_fw(dev_priv, GMBUS4, irq_en);
|
||||
|
||||
status |= GMBUS_SATOER;
|
||||
@ -380,7 +380,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
|
||||
50);
|
||||
|
||||
intel_de_write_fw(dev_priv, GMBUS4, 0);
|
||||
remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
|
||||
remove_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
|
||||
|
||||
if (gmbus2 & GMBUS_SATOER)
|
||||
return -ENXIO;
|
||||
@ -400,7 +400,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
|
||||
if (has_gmbus_irq(dev_priv))
|
||||
irq_enable = GMBUS_IDLE_EN;
|
||||
|
||||
add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
|
||||
add_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
|
||||
intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
|
||||
|
||||
ret = intel_wait_for_register_fw(&dev_priv->uncore,
|
||||
@ -408,7 +408,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
|
||||
10);
|
||||
|
||||
intel_de_write_fw(dev_priv, GMBUS4, 0);
|
||||
remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
|
||||
remove_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -791,7 +791,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
|
||||
int ret;
|
||||
|
||||
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
|
||||
mutex_lock(&dev_priv->gmbus_mutex);
|
||||
mutex_lock(&dev_priv->display.gmbus.mutex);
|
||||
|
||||
/*
|
||||
* In order to output Aksv to the receiver, use an indexed write to
|
||||
@ -800,7 +800,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
|
||||
*/
|
||||
ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
|
||||
|
||||
mutex_unlock(&dev_priv->gmbus_mutex);
|
||||
mutex_unlock(&dev_priv->display.gmbus.mutex);
|
||||
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
|
||||
|
||||
return ret;
|
||||
@ -826,7 +826,7 @@ static void gmbus_lock_bus(struct i2c_adapter *adapter,
|
||||
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
||||
struct drm_i915_private *dev_priv = bus->dev_priv;
|
||||
|
||||
mutex_lock(&dev_priv->gmbus_mutex);
|
||||
mutex_lock(&dev_priv->display.gmbus.mutex);
|
||||
}
|
||||
|
||||
static int gmbus_trylock_bus(struct i2c_adapter *adapter,
|
||||
@ -835,7 +835,7 @@ static int gmbus_trylock_bus(struct i2c_adapter *adapter,
|
||||
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
||||
struct drm_i915_private *dev_priv = bus->dev_priv;
|
||||
|
||||
return mutex_trylock(&dev_priv->gmbus_mutex);
|
||||
return mutex_trylock(&dev_priv->display.gmbus.mutex);
|
||||
}
|
||||
|
||||
static void gmbus_unlock_bus(struct i2c_adapter *adapter,
|
||||
@ -844,7 +844,7 @@ static void gmbus_unlock_bus(struct i2c_adapter *adapter,
|
||||
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
||||
struct drm_i915_private *dev_priv = bus->dev_priv;
|
||||
|
||||
mutex_unlock(&dev_priv->gmbus_mutex);
|
||||
mutex_unlock(&dev_priv->display.gmbus.mutex);
|
||||
}
|
||||
|
||||
static const struct i2c_lock_operations gmbus_lock_ops = {
|
||||
@ -864,18 +864,18 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
|
||||
int ret;
|
||||
|
||||
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
||||
dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
|
||||
dev_priv->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
|
||||
else if (!HAS_GMCH(dev_priv))
|
||||
/*
|
||||
* Broxton uses the same PCH offsets for South Display Engine,
|
||||
* even though it doesn't have a PCH.
|
||||
*/
|
||||
dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
|
||||
dev_priv->display.gmbus.mmio_base = PCH_DISPLAY_BASE;
|
||||
|
||||
mutex_init(&dev_priv->gmbus_mutex);
|
||||
init_waitqueue_head(&dev_priv->gmbus_wait_queue);
|
||||
mutex_init(&dev_priv->display.gmbus.mutex);
|
||||
init_waitqueue_head(&dev_priv->display.gmbus.wait_queue);
|
||||
|
||||
for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
|
||||
for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus.bus); pin++) {
|
||||
const struct gmbus_pin *gmbus_pin;
|
||||
struct intel_gmbus *bus;
|
||||
|
||||
@ -922,7 +922,7 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
|
||||
goto err;
|
||||
}
|
||||
|
||||
dev_priv->gmbus[pin] = bus;
|
||||
dev_priv->display.gmbus.bus[pin] = bus;
|
||||
}
|
||||
|
||||
intel_gmbus_reset(dev_priv);
|
||||
@ -938,11 +938,11 @@ err:
|
||||
struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
|
||||
unsigned int pin)
|
||||
{
|
||||
if (drm_WARN_ON(&dev_priv->drm, pin >= ARRAY_SIZE(dev_priv->gmbus) ||
|
||||
!dev_priv->gmbus[pin]))
|
||||
if (drm_WARN_ON(&dev_priv->drm, pin >= ARRAY_SIZE(dev_priv->display.gmbus.bus) ||
|
||||
!dev_priv->display.gmbus.bus[pin]))
|
||||
return NULL;
|
||||
|
||||
return &dev_priv->gmbus[pin]->adapter;
|
||||
return &dev_priv->display.gmbus.bus[pin]->adapter;
|
||||
}
|
||||
|
||||
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
|
||||
@ -950,7 +950,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
|
||||
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
||||
struct drm_i915_private *dev_priv = bus->dev_priv;
|
||||
|
||||
mutex_lock(&dev_priv->gmbus_mutex);
|
||||
mutex_lock(&dev_priv->display.gmbus.mutex);
|
||||
|
||||
bus->force_bit += force_bit ? 1 : -1;
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
@ -958,7 +958,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
|
||||
force_bit ? "en" : "dis", adapter->name,
|
||||
bus->force_bit);
|
||||
|
||||
mutex_unlock(&dev_priv->gmbus_mutex);
|
||||
mutex_unlock(&dev_priv->display.gmbus.mutex);
|
||||
}
|
||||
|
||||
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
|
||||
@ -972,16 +972,16 @@ void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
unsigned int pin;
|
||||
|
||||
for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
|
||||
for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus.bus); pin++) {
|
||||
struct intel_gmbus *bus;
|
||||
|
||||
bus = dev_priv->gmbus[pin];
|
||||
bus = dev_priv->display.gmbus.bus[pin];
|
||||
if (!bus)
|
||||
continue;
|
||||
|
||||
i2c_del_adapter(&bus->adapter);
|
||||
|
||||
kfree(bus);
|
||||
dev_priv->gmbus[pin] = NULL;
|
||||
dev_priv->display.gmbus.bus[pin] = NULL;
|
||||
}
|
||||
}
|
||||
|
@ -23,6 +23,7 @@
|
||||
#include "intel_display_power_well.h"
|
||||
#include "intel_display_types.h"
|
||||
#include "intel_hdcp.h"
|
||||
#include "intel_hdcp_regs.h"
|
||||
#include "intel_pcode.h"
|
||||
|
||||
#define KEY_LOAD_TRIES 5
|
||||
@ -1131,8 +1132,8 @@ static void intel_hdcp_prop_work(struct work_struct *work)
|
||||
|
||||
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
|
||||
{
|
||||
return INTEL_INFO(dev_priv)->display.has_hdcp &&
|
||||
(DISPLAY_VER(dev_priv) >= 12 || port < PORT_E);
|
||||
return RUNTIME_INFO(dev_priv)->has_hdcp &&
|
||||
(DISPLAY_VER(dev_priv) >= 12 || port < PORT_E);
|
||||
}
|
||||
|
||||
static int
|
||||
|
270
drivers/gpu/drm/i915/display/intel_hdcp_regs.h
Normal file
270
drivers/gpu/drm/i915/display/intel_hdcp_regs.h
Normal file
@ -0,0 +1,270 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2022 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __INTEL_HDCP_REGS_H__
|
||||
#define __INTEL_HDCP_REGS_H__
|
||||
|
||||
#include "i915_reg_defs.h"
|
||||
|
||||
/* HDCP Key Registers */
|
||||
#define HDCP_KEY_CONF _MMIO(0x66c00)
|
||||
#define HDCP_AKSV_SEND_TRIGGER REG_BIT(31)
|
||||
#define HDCP_CLEAR_KEYS_TRIGGER REG_BIT(30)
|
||||
#define HDCP_KEY_LOAD_TRIGGER REG_BIT(8)
|
||||
#define HDCP_KEY_STATUS _MMIO(0x66c04)
|
||||
#define HDCP_FUSE_IN_PROGRESS REG_BIT(7)
|
||||
#define HDCP_FUSE_ERROR REG_BIT(6)
|
||||
#define HDCP_FUSE_DONE REG_BIT(5)
|
||||
#define HDCP_KEY_LOAD_STATUS REG_BIT(1)
|
||||
#define HDCP_KEY_LOAD_DONE REG_BIT(0)
|
||||
#define HDCP_AKSV_LO _MMIO(0x66c10)
|
||||
#define HDCP_AKSV_HI _MMIO(0x66c14)
|
||||
|
||||
/* HDCP Repeater Registers */
|
||||
#define HDCP_REP_CTL _MMIO(0x66d00)
|
||||
#define HDCP_TRANSA_REP_PRESENT REG_BIT(31)
|
||||
#define HDCP_TRANSB_REP_PRESENT REG_BIT(30)
|
||||
#define HDCP_TRANSC_REP_PRESENT REG_BIT(29)
|
||||
#define HDCP_TRANSD_REP_PRESENT REG_BIT(28)
|
||||
#define HDCP_DDIB_REP_PRESENT REG_BIT(30)
|
||||
#define HDCP_DDIA_REP_PRESENT REG_BIT(29)
|
||||
#define HDCP_DDIC_REP_PRESENT REG_BIT(28)
|
||||
#define HDCP_DDID_REP_PRESENT REG_BIT(27)
|
||||
#define HDCP_DDIF_REP_PRESENT REG_BIT(26)
|
||||
#define HDCP_DDIE_REP_PRESENT REG_BIT(25)
|
||||
#define HDCP_TRANSA_SHA1_M0 (1 << 20)
|
||||
#define HDCP_TRANSB_SHA1_M0 (2 << 20)
|
||||
#define HDCP_TRANSC_SHA1_M0 (3 << 20)
|
||||
#define HDCP_TRANSD_SHA1_M0 (4 << 20)
|
||||
#define HDCP_DDIB_SHA1_M0 (1 << 20)
|
||||
#define HDCP_DDIA_SHA1_M0 (2 << 20)
|
||||
#define HDCP_DDIC_SHA1_M0 (3 << 20)
|
||||
#define HDCP_DDID_SHA1_M0 (4 << 20)
|
||||
#define HDCP_DDIF_SHA1_M0 (5 << 20)
|
||||
#define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
|
||||
#define HDCP_SHA1_BUSY REG_BIT(16)
|
||||
#define HDCP_SHA1_READY REG_BIT(17)
|
||||
#define HDCP_SHA1_COMPLETE REG_BIT(18)
|
||||
#define HDCP_SHA1_V_MATCH REG_BIT(19)
|
||||
#define HDCP_SHA1_TEXT_32 (1 << 1)
|
||||
#define HDCP_SHA1_COMPLETE_HASH (2 << 1)
|
||||
#define HDCP_SHA1_TEXT_24 (4 << 1)
|
||||
#define HDCP_SHA1_TEXT_16 (5 << 1)
|
||||
#define HDCP_SHA1_TEXT_8 (6 << 1)
|
||||
#define HDCP_SHA1_TEXT_0 (7 << 1)
|
||||
#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
|
||||
#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
|
||||
#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
|
||||
#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
|
||||
#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
|
||||
#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
|
||||
#define HDCP_SHA_TEXT _MMIO(0x66d18)
|
||||
|
||||
/* HDCP Auth Registers */
|
||||
#define _PORTA_HDCP_AUTHENC 0x66800
|
||||
#define _PORTB_HDCP_AUTHENC 0x66500
|
||||
#define _PORTC_HDCP_AUTHENC 0x66600
|
||||
#define _PORTD_HDCP_AUTHENC 0x66700
|
||||
#define _PORTE_HDCP_AUTHENC 0x66A00
|
||||
#define _PORTF_HDCP_AUTHENC 0x66900
|
||||
#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
|
||||
_PORTA_HDCP_AUTHENC, \
|
||||
_PORTB_HDCP_AUTHENC, \
|
||||
_PORTC_HDCP_AUTHENC, \
|
||||
_PORTD_HDCP_AUTHENC, \
|
||||
_PORTE_HDCP_AUTHENC, \
|
||||
_PORTF_HDCP_AUTHENC) + (x))
|
||||
#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
|
||||
#define _TRANSA_HDCP_CONF 0x66400
|
||||
#define _TRANSB_HDCP_CONF 0x66500
|
||||
#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
|
||||
_TRANSB_HDCP_CONF)
|
||||
#define HDCP_CONF(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_CONF(trans) : \
|
||||
PORT_HDCP_CONF(port))
|
||||
|
||||
#define HDCP_CONF_CAPTURE_AN REG_BIT(0)
|
||||
#define HDCP_CONF_AUTH_AND_ENC (REG_BIT(1) | REG_BIT(0))
|
||||
#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
|
||||
#define _TRANSA_HDCP_ANINIT 0x66404
|
||||
#define _TRANSB_HDCP_ANINIT 0x66504
|
||||
#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP_ANINIT, \
|
||||
_TRANSB_HDCP_ANINIT)
|
||||
#define HDCP_ANINIT(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_ANINIT(trans) : \
|
||||
PORT_HDCP_ANINIT(port))
|
||||
|
||||
#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
|
||||
#define _TRANSA_HDCP_ANLO 0x66408
|
||||
#define _TRANSB_HDCP_ANLO 0x66508
|
||||
#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
|
||||
_TRANSB_HDCP_ANLO)
|
||||
#define HDCP_ANLO(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_ANLO(trans) : \
|
||||
PORT_HDCP_ANLO(port))
|
||||
|
||||
#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
|
||||
#define _TRANSA_HDCP_ANHI 0x6640C
|
||||
#define _TRANSB_HDCP_ANHI 0x6650C
|
||||
#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
|
||||
_TRANSB_HDCP_ANHI)
|
||||
#define HDCP_ANHI(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_ANHI(trans) : \
|
||||
PORT_HDCP_ANHI(port))
|
||||
|
||||
#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
|
||||
#define _TRANSA_HDCP_BKSVLO 0x66410
|
||||
#define _TRANSB_HDCP_BKSVLO 0x66510
|
||||
#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP_BKSVLO, \
|
||||
_TRANSB_HDCP_BKSVLO)
|
||||
#define HDCP_BKSVLO(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_BKSVLO(trans) : \
|
||||
PORT_HDCP_BKSVLO(port))
|
||||
|
||||
#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
|
||||
#define _TRANSA_HDCP_BKSVHI 0x66414
|
||||
#define _TRANSB_HDCP_BKSVHI 0x66514
|
||||
#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP_BKSVHI, \
|
||||
_TRANSB_HDCP_BKSVHI)
|
||||
#define HDCP_BKSVHI(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_BKSVHI(trans) : \
|
||||
PORT_HDCP_BKSVHI(port))
|
||||
|
||||
#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
|
||||
#define _TRANSA_HDCP_RPRIME 0x66418
|
||||
#define _TRANSB_HDCP_RPRIME 0x66518
|
||||
#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP_RPRIME, \
|
||||
_TRANSB_HDCP_RPRIME)
|
||||
#define HDCP_RPRIME(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_RPRIME(trans) : \
|
||||
PORT_HDCP_RPRIME(port))
|
||||
|
||||
#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
|
||||
#define _TRANSA_HDCP_STATUS 0x6641C
|
||||
#define _TRANSB_HDCP_STATUS 0x6651C
|
||||
#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP_STATUS, \
|
||||
_TRANSB_HDCP_STATUS)
|
||||
#define HDCP_STATUS(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_STATUS(trans) : \
|
||||
PORT_HDCP_STATUS(port))
|
||||
|
||||
#define HDCP_STATUS_STREAM_A_ENC REG_BIT(31)
|
||||
#define HDCP_STATUS_STREAM_B_ENC REG_BIT(30)
|
||||
#define HDCP_STATUS_STREAM_C_ENC REG_BIT(29)
|
||||
#define HDCP_STATUS_STREAM_D_ENC REG_BIT(28)
|
||||
#define HDCP_STATUS_AUTH REG_BIT(21)
|
||||
#define HDCP_STATUS_ENC REG_BIT(20)
|
||||
#define HDCP_STATUS_RI_MATCH REG_BIT(19)
|
||||
#define HDCP_STATUS_R0_READY REG_BIT(18)
|
||||
#define HDCP_STATUS_AN_READY REG_BIT(17)
|
||||
#define HDCP_STATUS_CIPHER REG_BIT(16)
|
||||
#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
|
||||
|
||||
/* HDCP2.2 Registers */
|
||||
#define _PORTA_HDCP2_BASE 0x66800
|
||||
#define _PORTB_HDCP2_BASE 0x66500
|
||||
#define _PORTC_HDCP2_BASE 0x66600
|
||||
#define _PORTD_HDCP2_BASE 0x66700
|
||||
#define _PORTE_HDCP2_BASE 0x66A00
|
||||
#define _PORTF_HDCP2_BASE 0x66900
|
||||
#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
|
||||
_PORTA_HDCP2_BASE, \
|
||||
_PORTB_HDCP2_BASE, \
|
||||
_PORTC_HDCP2_BASE, \
|
||||
_PORTD_HDCP2_BASE, \
|
||||
_PORTE_HDCP2_BASE, \
|
||||
_PORTF_HDCP2_BASE) + (x))
|
||||
|
||||
#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
|
||||
#define _TRANSA_HDCP2_AUTH 0x66498
|
||||
#define _TRANSB_HDCP2_AUTH 0x66598
|
||||
#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
|
||||
_TRANSB_HDCP2_AUTH)
|
||||
#define AUTH_LINK_AUTHENTICATED REG_BIT(31)
|
||||
#define AUTH_LINK_TYPE REG_BIT(30)
|
||||
#define AUTH_FORCE_CLR_INPUTCTR REG_BIT(19)
|
||||
#define AUTH_CLR_KEYS REG_BIT(18)
|
||||
#define HDCP2_AUTH(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP2_AUTH(trans) : \
|
||||
PORT_HDCP2_AUTH(port))
|
||||
|
||||
#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0)
|
||||
#define _TRANSA_HDCP2_CTL 0x664B0
|
||||
#define _TRANSB_HDCP2_CTL 0x665B0
|
||||
#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
|
||||
_TRANSB_HDCP2_CTL)
|
||||
#define CTL_LINK_ENCRYPTION_REQ REG_BIT(31)
|
||||
#define HDCP2_CTL(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP2_CTL(trans) : \
|
||||
PORT_HDCP2_CTL(port))
|
||||
|
||||
#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4)
|
||||
#define _TRANSA_HDCP2_STATUS 0x664B4
|
||||
#define _TRANSB_HDCP2_STATUS 0x665B4
|
||||
#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP2_STATUS, \
|
||||
_TRANSB_HDCP2_STATUS)
|
||||
#define LINK_TYPE_STATUS REG_BIT(22)
|
||||
#define LINK_AUTH_STATUS REG_BIT(21)
|
||||
#define LINK_ENCRYPTION_STATUS REG_BIT(20)
|
||||
#define HDCP2_STATUS(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP2_STATUS(trans) : \
|
||||
PORT_HDCP2_STATUS(port))
|
||||
|
||||
#define _PIPEA_HDCP2_STREAM_STATUS 0x668C0
|
||||
#define _PIPEB_HDCP2_STREAM_STATUS 0x665C0
|
||||
#define _PIPEC_HDCP2_STREAM_STATUS 0x666C0
|
||||
#define _PIPED_HDCP2_STREAM_STATUS 0x667C0
|
||||
#define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \
|
||||
_PIPEA_HDCP2_STREAM_STATUS, \
|
||||
_PIPEB_HDCP2_STREAM_STATUS, \
|
||||
_PIPEC_HDCP2_STREAM_STATUS, \
|
||||
_PIPED_HDCP2_STREAM_STATUS))
|
||||
|
||||
#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0
|
||||
#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0
|
||||
#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP2_STREAM_STATUS, \
|
||||
_TRANSB_HDCP2_STREAM_STATUS)
|
||||
#define STREAM_ENCRYPTION_STATUS REG_BIT(31)
|
||||
#define STREAM_TYPE_STATUS REG_BIT(30)
|
||||
#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP2_STREAM_STATUS(trans) : \
|
||||
PIPE_HDCP2_STREAM_STATUS(pipe))
|
||||
|
||||
#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
|
||||
#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
|
||||
#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
|
||||
_PORTA_HDCP2_AUTH_STREAM, \
|
||||
_PORTB_HDCP2_AUTH_STREAM)
|
||||
#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
|
||||
#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
|
||||
#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP2_AUTH_STREAM, \
|
||||
_TRANSB_HDCP2_AUTH_STREAM)
|
||||
#define AUTH_STREAM_TYPE REG_BIT(31)
|
||||
#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP2_AUTH_STREAM(trans) : \
|
||||
PORT_HDCP2_AUTH_STREAM(port))
|
||||
|
||||
#endif /* __INTEL_HDCP_REGS_H__ */
|
@ -50,6 +50,7 @@
|
||||
#include "intel_dp.h"
|
||||
#include "intel_gmbus.h"
|
||||
#include "intel_hdcp.h"
|
||||
#include "intel_hdcp_regs.h"
|
||||
#include "intel_hdmi.h"
|
||||
#include "intel_lspcon.h"
|
||||
#include "intel_panel.h"
|
||||
@ -2001,6 +2002,15 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
|
||||
clock *= 2;
|
||||
}
|
||||
|
||||
/*
|
||||
* HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
|
||||
* enumerated only if FRL is supported. Current platforms do not support
|
||||
* FRL so prune the higher resolution modes that require doctclock more
|
||||
* than 600MHz.
|
||||
*/
|
||||
if (clock > 600000)
|
||||
return MODE_CLOCK_HIGH;
|
||||
|
||||
ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
|
||||
|
||||
status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
|
||||
|
@ -119,13 +119,13 @@ intel_connector_hpd_pin(struct intel_connector *connector)
|
||||
* responsible for further action.
|
||||
*
|
||||
* The number of IRQs that are allowed within @HPD_STORM_DETECT_PERIOD is
|
||||
* stored in @dev_priv->hotplug.hpd_storm_threshold which defaults to
|
||||
* stored in @dev_priv->display.hotplug.hpd_storm_threshold which defaults to
|
||||
* @HPD_STORM_DEFAULT_THRESHOLD. Long IRQs count as +10 to this threshold, and
|
||||
* short IRQs count as +1. If this threshold is exceeded, it's considered an
|
||||
* IRQ storm and the IRQ state is set to @HPD_MARK_DISABLED.
|
||||
*
|
||||
* By default, most systems will only count long IRQs towards
|
||||
* &dev_priv->hotplug.hpd_storm_threshold. However, some older systems also
|
||||
* &dev_priv->display.hotplug.hpd_storm_threshold. However, some older systems also
|
||||
* suffer from short IRQ storms and must also track these. Because short IRQ
|
||||
* storms are naturally caused by sideband interactions with DP MST devices,
|
||||
* short IRQ detection is only enabled for systems without DP MST support.
|
||||
@ -140,7 +140,7 @@ intel_connector_hpd_pin(struct intel_connector *connector)
|
||||
static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
|
||||
enum hpd_pin pin, bool long_hpd)
|
||||
{
|
||||
struct i915_hotplug *hpd = &dev_priv->hotplug;
|
||||
struct intel_hotplug *hpd = &dev_priv->display.hotplug;
|
||||
unsigned long start = hpd->stats[pin].last_jiffies;
|
||||
unsigned long end = start + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD);
|
||||
const int increment = long_hpd ? 10 : 1;
|
||||
@ -148,7 +148,7 @@ static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
|
||||
bool storm = false;
|
||||
|
||||
if (!threshold ||
|
||||
(!long_hpd && !dev_priv->hotplug.hpd_short_storm_enabled))
|
||||
(!long_hpd && !dev_priv->display.hotplug.hpd_short_storm_enabled))
|
||||
return false;
|
||||
|
||||
if (!time_in_range(jiffies, start, end)) {
|
||||
@ -191,7 +191,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
|
||||
|
||||
pin = intel_connector_hpd_pin(connector);
|
||||
if (pin == HPD_NONE ||
|
||||
dev_priv->hotplug.stats[pin].state != HPD_MARK_DISABLED)
|
||||
dev_priv->display.hotplug.stats[pin].state != HPD_MARK_DISABLED)
|
||||
continue;
|
||||
|
||||
drm_info(&dev_priv->drm,
|
||||
@ -199,7 +199,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
|
||||
"switching from hotplug detection to polling\n",
|
||||
connector->base.name);
|
||||
|
||||
dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
|
||||
dev_priv->display.hotplug.stats[pin].state = HPD_DISABLED;
|
||||
connector->base.polled = DRM_CONNECTOR_POLL_CONNECT |
|
||||
DRM_CONNECTOR_POLL_DISCONNECT;
|
||||
hpd_disabled = true;
|
||||
@ -209,7 +209,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
|
||||
/* Enable polling and queue hotplug re-enabling. */
|
||||
if (hpd_disabled) {
|
||||
drm_kms_helper_poll_enable(dev);
|
||||
mod_delayed_work(system_wq, &dev_priv->hotplug.reenable_work,
|
||||
mod_delayed_work(system_wq, &dev_priv->display.hotplug.reenable_work,
|
||||
msecs_to_jiffies(HPD_STORM_REENABLE_DELAY));
|
||||
}
|
||||
}
|
||||
@ -218,7 +218,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
|
||||
{
|
||||
struct drm_i915_private *dev_priv =
|
||||
container_of(work, typeof(*dev_priv),
|
||||
hotplug.reenable_work.work);
|
||||
display.hotplug.reenable_work.work);
|
||||
struct drm_device *dev = &dev_priv->drm;
|
||||
struct drm_connector_list_iter conn_iter;
|
||||
struct intel_connector *connector;
|
||||
@ -233,7 +233,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
|
||||
for_each_intel_connector_iter(connector, &conn_iter) {
|
||||
pin = intel_connector_hpd_pin(connector);
|
||||
if (pin == HPD_NONE ||
|
||||
dev_priv->hotplug.stats[pin].state != HPD_DISABLED)
|
||||
dev_priv->display.hotplug.stats[pin].state != HPD_DISABLED)
|
||||
continue;
|
||||
|
||||
if (connector->base.polled != connector->polled)
|
||||
@ -245,8 +245,8 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
|
||||
drm_connector_list_iter_end(&conn_iter);
|
||||
|
||||
for_each_hpd_pin(pin) {
|
||||
if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED)
|
||||
dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
|
||||
if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED)
|
||||
dev_priv->display.hotplug.stats[pin].state = HPD_ENABLED;
|
||||
}
|
||||
|
||||
intel_hpd_irq_setup(dev_priv);
|
||||
@ -297,16 +297,16 @@ static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder)
|
||||
static void i915_digport_work_func(struct work_struct *work)
|
||||
{
|
||||
struct drm_i915_private *dev_priv =
|
||||
container_of(work, struct drm_i915_private, hotplug.dig_port_work);
|
||||
container_of(work, struct drm_i915_private, display.hotplug.dig_port_work);
|
||||
u32 long_port_mask, short_port_mask;
|
||||
struct intel_encoder *encoder;
|
||||
u32 old_bits = 0;
|
||||
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
long_port_mask = dev_priv->hotplug.long_port_mask;
|
||||
dev_priv->hotplug.long_port_mask = 0;
|
||||
short_port_mask = dev_priv->hotplug.short_port_mask;
|
||||
dev_priv->hotplug.short_port_mask = 0;
|
||||
long_port_mask = dev_priv->display.hotplug.long_port_mask;
|
||||
dev_priv->display.hotplug.long_port_mask = 0;
|
||||
short_port_mask = dev_priv->display.hotplug.short_port_mask;
|
||||
dev_priv->display.hotplug.short_port_mask = 0;
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
|
||||
for_each_intel_encoder(&dev_priv->drm, encoder) {
|
||||
@ -335,9 +335,9 @@ static void i915_digport_work_func(struct work_struct *work)
|
||||
|
||||
if (old_bits) {
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
dev_priv->hotplug.event_bits |= old_bits;
|
||||
dev_priv->display.hotplug.event_bits |= old_bits;
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
|
||||
queue_delayed_work(system_wq, &dev_priv->display.hotplug.hotplug_work, 0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -353,10 +353,10 @@ void intel_hpd_trigger_irq(struct intel_digital_port *dig_port)
|
||||
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
|
||||
|
||||
spin_lock_irq(&i915->irq_lock);
|
||||
i915->hotplug.short_port_mask |= BIT(dig_port->base.port);
|
||||
i915->display.hotplug.short_port_mask |= BIT(dig_port->base.port);
|
||||
spin_unlock_irq(&i915->irq_lock);
|
||||
|
||||
queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work);
|
||||
queue_work(i915->display.hotplug.dp_wq, &i915->display.hotplug.dig_port_work);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -366,7 +366,7 @@ static void i915_hotplug_work_func(struct work_struct *work)
|
||||
{
|
||||
struct drm_i915_private *dev_priv =
|
||||
container_of(work, struct drm_i915_private,
|
||||
hotplug.hotplug_work.work);
|
||||
display.hotplug.hotplug_work.work);
|
||||
struct drm_device *dev = &dev_priv->drm;
|
||||
struct drm_connector_list_iter conn_iter;
|
||||
struct intel_connector *connector;
|
||||
@ -379,10 +379,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
|
||||
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
|
||||
hpd_event_bits = dev_priv->hotplug.event_bits;
|
||||
dev_priv->hotplug.event_bits = 0;
|
||||
hpd_retry_bits = dev_priv->hotplug.retry_bits;
|
||||
dev_priv->hotplug.retry_bits = 0;
|
||||
hpd_event_bits = dev_priv->display.hotplug.event_bits;
|
||||
dev_priv->display.hotplug.event_bits = 0;
|
||||
hpd_retry_bits = dev_priv->display.hotplug.retry_bits;
|
||||
dev_priv->display.hotplug.retry_bits = 0;
|
||||
|
||||
/* Enable polling for connectors which had HPD IRQ storms */
|
||||
intel_hpd_irq_storm_switch_to_polling(dev_priv);
|
||||
@ -435,10 +435,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
|
||||
retry &= ~changed;
|
||||
if (retry) {
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
dev_priv->hotplug.retry_bits |= retry;
|
||||
dev_priv->display.hotplug.retry_bits |= retry;
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
|
||||
mod_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work,
|
||||
mod_delayed_work(system_wq, &dev_priv->display.hotplug.hotplug_work,
|
||||
msecs_to_jiffies(HPD_RETRY_DELAY));
|
||||
}
|
||||
}
|
||||
@ -502,10 +502,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
|
||||
|
||||
if (long_hpd) {
|
||||
long_hpd_pulse_mask |= BIT(pin);
|
||||
dev_priv->hotplug.long_port_mask |= BIT(port);
|
||||
dev_priv->display.hotplug.long_port_mask |= BIT(port);
|
||||
} else {
|
||||
short_hpd_pulse_mask |= BIT(pin);
|
||||
dev_priv->hotplug.short_port_mask |= BIT(port);
|
||||
dev_priv->display.hotplug.short_port_mask |= BIT(port);
|
||||
}
|
||||
}
|
||||
|
||||
@ -516,7 +516,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
|
||||
if (!(BIT(pin) & pin_mask))
|
||||
continue;
|
||||
|
||||
if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED) {
|
||||
if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED) {
|
||||
/*
|
||||
* On GMCH platforms the interrupt mask bits only
|
||||
* prevent irq generation, not the setting of the
|
||||
@ -529,7 +529,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
|
||||
continue;
|
||||
}
|
||||
|
||||
if (dev_priv->hotplug.stats[pin].state != HPD_ENABLED)
|
||||
if (dev_priv->display.hotplug.stats[pin].state != HPD_ENABLED)
|
||||
continue;
|
||||
|
||||
/*
|
||||
@ -540,13 +540,13 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
|
||||
if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {
|
||||
long_hpd = long_hpd_pulse_mask & BIT(pin);
|
||||
} else {
|
||||
dev_priv->hotplug.event_bits |= BIT(pin);
|
||||
dev_priv->display.hotplug.event_bits |= BIT(pin);
|
||||
long_hpd = true;
|
||||
queue_hp = true;
|
||||
}
|
||||
|
||||
if (intel_hpd_irq_storm_detect(dev_priv, pin, long_hpd)) {
|
||||
dev_priv->hotplug.event_bits &= ~BIT(pin);
|
||||
dev_priv->display.hotplug.event_bits &= ~BIT(pin);
|
||||
storm_detected = true;
|
||||
queue_hp = true;
|
||||
}
|
||||
@ -567,9 +567,9 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
|
||||
* deadlock.
|
||||
*/
|
||||
if (queue_dig)
|
||||
queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work);
|
||||
queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work);
|
||||
if (queue_hp)
|
||||
queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
|
||||
queue_delayed_work(system_wq, &dev_priv->display.hotplug.hotplug_work, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -594,8 +594,8 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
|
||||
return;
|
||||
|
||||
for_each_hpd_pin(i) {
|
||||
dev_priv->hotplug.stats[i].count = 0;
|
||||
dev_priv->hotplug.stats[i].state = HPD_ENABLED;
|
||||
dev_priv->display.hotplug.stats[i].count = 0;
|
||||
dev_priv->display.hotplug.stats[i].state = HPD_ENABLED;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -611,7 +611,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
|
||||
{
|
||||
struct drm_i915_private *dev_priv =
|
||||
container_of(work, struct drm_i915_private,
|
||||
hotplug.poll_init_work);
|
||||
display.hotplug.poll_init_work);
|
||||
struct drm_device *dev = &dev_priv->drm;
|
||||
struct drm_connector_list_iter conn_iter;
|
||||
struct intel_connector *connector;
|
||||
@ -619,7 +619,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
|
||||
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
|
||||
enabled = READ_ONCE(dev_priv->hotplug.poll_enabled);
|
||||
enabled = READ_ONCE(dev_priv->display.hotplug.poll_enabled);
|
||||
|
||||
drm_connector_list_iter_begin(dev, &conn_iter);
|
||||
for_each_intel_connector_iter(connector, &conn_iter) {
|
||||
@ -672,7 +672,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
|
||||
!INTEL_DISPLAY_ENABLED(dev_priv))
|
||||
return;
|
||||
|
||||
WRITE_ONCE(dev_priv->hotplug.poll_enabled, true);
|
||||
WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, true);
|
||||
|
||||
/*
|
||||
* We might already be holding dev->mode_config.mutex, so do this in a
|
||||
@ -680,7 +680,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
|
||||
* As well, there's no issue if we race here since we always reschedule
|
||||
* this worker anyway
|
||||
*/
|
||||
schedule_work(&dev_priv->hotplug.poll_init_work);
|
||||
schedule_work(&dev_priv->display.hotplug.poll_init_work);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -707,17 +707,17 @@ void intel_hpd_poll_disable(struct drm_i915_private *dev_priv)
|
||||
if (!HAS_DISPLAY(dev_priv))
|
||||
return;
|
||||
|
||||
WRITE_ONCE(dev_priv->hotplug.poll_enabled, false);
|
||||
schedule_work(&dev_priv->hotplug.poll_init_work);
|
||||
WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, false);
|
||||
schedule_work(&dev_priv->display.hotplug.poll_init_work);
|
||||
}
|
||||
|
||||
void intel_hpd_init_work(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
INIT_DELAYED_WORK(&dev_priv->hotplug.hotplug_work,
|
||||
INIT_DELAYED_WORK(&dev_priv->display.hotplug.hotplug_work,
|
||||
i915_hotplug_work_func);
|
||||
INIT_WORK(&dev_priv->hotplug.dig_port_work, i915_digport_work_func);
|
||||
INIT_WORK(&dev_priv->hotplug.poll_init_work, i915_hpd_poll_init_work);
|
||||
INIT_DELAYED_WORK(&dev_priv->hotplug.reenable_work,
|
||||
INIT_WORK(&dev_priv->display.hotplug.dig_port_work, i915_digport_work_func);
|
||||
INIT_WORK(&dev_priv->display.hotplug.poll_init_work, i915_hpd_poll_init_work);
|
||||
INIT_DELAYED_WORK(&dev_priv->display.hotplug.reenable_work,
|
||||
intel_hpd_irq_storm_reenable_work);
|
||||
}
|
||||
|
||||
@ -728,17 +728,17 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
|
||||
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
|
||||
dev_priv->hotplug.long_port_mask = 0;
|
||||
dev_priv->hotplug.short_port_mask = 0;
|
||||
dev_priv->hotplug.event_bits = 0;
|
||||
dev_priv->hotplug.retry_bits = 0;
|
||||
dev_priv->display.hotplug.long_port_mask = 0;
|
||||
dev_priv->display.hotplug.short_port_mask = 0;
|
||||
dev_priv->display.hotplug.event_bits = 0;
|
||||
dev_priv->display.hotplug.retry_bits = 0;
|
||||
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
|
||||
cancel_work_sync(&dev_priv->hotplug.dig_port_work);
|
||||
cancel_delayed_work_sync(&dev_priv->hotplug.hotplug_work);
|
||||
cancel_work_sync(&dev_priv->hotplug.poll_init_work);
|
||||
cancel_delayed_work_sync(&dev_priv->hotplug.reenable_work);
|
||||
cancel_work_sync(&dev_priv->display.hotplug.dig_port_work);
|
||||
cancel_delayed_work_sync(&dev_priv->display.hotplug.hotplug_work);
|
||||
cancel_work_sync(&dev_priv->display.hotplug.poll_init_work);
|
||||
cancel_delayed_work_sync(&dev_priv->display.hotplug.reenable_work);
|
||||
}
|
||||
|
||||
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
|
||||
@ -749,8 +749,8 @@ bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
|
||||
return false;
|
||||
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
if (dev_priv->hotplug.stats[pin].state == HPD_ENABLED) {
|
||||
dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
|
||||
if (dev_priv->display.hotplug.stats[pin].state == HPD_ENABLED) {
|
||||
dev_priv->display.hotplug.stats[pin].state = HPD_DISABLED;
|
||||
ret = true;
|
||||
}
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
@ -764,6 +764,6 @@ void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
|
||||
return;
|
||||
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
|
||||
dev_priv->display.hotplug.stats[pin].state = HPD_ENABLED;
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
}
|
||||
|
@ -73,8 +73,9 @@
|
||||
#include "i915_drv.h"
|
||||
#include "intel_de.h"
|
||||
#include "intel_lpe_audio.h"
|
||||
#include "intel_pci_config.h"
|
||||
|
||||
#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->audio.lpe.platdev != NULL)
|
||||
#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev != NULL)
|
||||
|
||||
static struct platform_device *
|
||||
lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
|
||||
@ -96,13 +97,13 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
rsc[0].start = rsc[0].end = dev_priv->audio.lpe.irq;
|
||||
rsc[0].start = rsc[0].end = dev_priv->display.audio.lpe.irq;
|
||||
rsc[0].flags = IORESOURCE_IRQ;
|
||||
rsc[0].name = "hdmi-lpe-audio-irq";
|
||||
|
||||
rsc[1].start = pci_resource_start(pdev, 0) +
|
||||
rsc[1].start = pci_resource_start(pdev, GTTMMADR_BAR) +
|
||||
I915_HDMI_LPE_AUDIO_BASE;
|
||||
rsc[1].end = pci_resource_start(pdev, 0) +
|
||||
rsc[1].end = pci_resource_start(pdev, GTTMMADR_BAR) +
|
||||
I915_HDMI_LPE_AUDIO_BASE + I915_HDMI_LPE_AUDIO_SIZE - 1;
|
||||
rsc[1].flags = IORESOURCE_MEM;
|
||||
rsc[1].name = "hdmi-lpe-audio-mmio";
|
||||
@ -148,7 +149,7 @@ static void lpe_audio_platdev_destroy(struct drm_i915_private *dev_priv)
|
||||
* than us fiddle with its internals.
|
||||
*/
|
||||
|
||||
platform_device_unregister(dev_priv->audio.lpe.platdev);
|
||||
platform_device_unregister(dev_priv->display.audio.lpe.platdev);
|
||||
}
|
||||
|
||||
static void lpe_audio_irq_unmask(struct irq_data *d)
|
||||
@ -167,7 +168,7 @@ static struct irq_chip lpe_audio_irqchip = {
|
||||
|
||||
static int lpe_audio_irq_init(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
int irq = dev_priv->audio.lpe.irq;
|
||||
int irq = dev_priv->display.audio.lpe.irq;
|
||||
|
||||
drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
|
||||
irq_set_chip_and_handler_name(irq,
|
||||
@ -204,15 +205,15 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
dev_priv->audio.lpe.irq = irq_alloc_desc(0);
|
||||
if (dev_priv->audio.lpe.irq < 0) {
|
||||
dev_priv->display.audio.lpe.irq = irq_alloc_desc(0);
|
||||
if (dev_priv->display.audio.lpe.irq < 0) {
|
||||
drm_err(&dev_priv->drm, "Failed to allocate IRQ desc: %d\n",
|
||||
dev_priv->audio.lpe.irq);
|
||||
ret = dev_priv->audio.lpe.irq;
|
||||
dev_priv->display.audio.lpe.irq);
|
||||
ret = dev_priv->display.audio.lpe.irq;
|
||||
goto err;
|
||||
}
|
||||
|
||||
drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->audio.lpe.irq);
|
||||
drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->display.audio.lpe.irq);
|
||||
|
||||
ret = lpe_audio_irq_init(dev_priv);
|
||||
|
||||
@ -223,10 +224,10 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv)
|
||||
goto err_free_irq;
|
||||
}
|
||||
|
||||
dev_priv->audio.lpe.platdev = lpe_audio_platdev_create(dev_priv);
|
||||
dev_priv->display.audio.lpe.platdev = lpe_audio_platdev_create(dev_priv);
|
||||
|
||||
if (IS_ERR(dev_priv->audio.lpe.platdev)) {
|
||||
ret = PTR_ERR(dev_priv->audio.lpe.platdev);
|
||||
if (IS_ERR(dev_priv->display.audio.lpe.platdev)) {
|
||||
ret = PTR_ERR(dev_priv->display.audio.lpe.platdev);
|
||||
drm_err(&dev_priv->drm,
|
||||
"Failed to create lpe audio platform device: %d\n",
|
||||
ret);
|
||||
@ -241,10 +242,10 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv)
|
||||
|
||||
return 0;
|
||||
err_free_irq:
|
||||
irq_free_desc(dev_priv->audio.lpe.irq);
|
||||
irq_free_desc(dev_priv->display.audio.lpe.irq);
|
||||
err:
|
||||
dev_priv->audio.lpe.irq = -1;
|
||||
dev_priv->audio.lpe.platdev = NULL;
|
||||
dev_priv->display.audio.lpe.irq = -1;
|
||||
dev_priv->display.audio.lpe.platdev = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -262,7 +263,7 @@ void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv)
|
||||
if (!HAS_LPE_AUDIO(dev_priv))
|
||||
return;
|
||||
|
||||
ret = generic_handle_irq(dev_priv->audio.lpe.irq);
|
||||
ret = generic_handle_irq(dev_priv->display.audio.lpe.irq);
|
||||
if (ret)
|
||||
drm_err_ratelimited(&dev_priv->drm,
|
||||
"error handling LPE audio irq: %d\n", ret);
|
||||
@ -303,10 +304,10 @@ void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv)
|
||||
|
||||
lpe_audio_platdev_destroy(dev_priv);
|
||||
|
||||
irq_free_desc(dev_priv->audio.lpe.irq);
|
||||
irq_free_desc(dev_priv->display.audio.lpe.irq);
|
||||
|
||||
dev_priv->audio.lpe.irq = -1;
|
||||
dev_priv->audio.lpe.platdev = NULL;
|
||||
dev_priv->display.audio.lpe.irq = -1;
|
||||
dev_priv->display.audio.lpe.platdev = NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -333,7 +334,7 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
|
||||
if (!HAS_LPE_AUDIO(dev_priv))
|
||||
return;
|
||||
|
||||
pdata = dev_get_platdata(&dev_priv->audio.lpe.platdev->dev);
|
||||
pdata = dev_get_platdata(&dev_priv->display.audio.lpe.platdev->dev);
|
||||
ppdata = &pdata->port[port - PORT_B];
|
||||
|
||||
spin_lock_irqsave(&pdata->lpe_audio_slock, irqflags);
|
||||
@ -361,7 +362,7 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
|
||||
}
|
||||
|
||||
if (pdata->notify_audio_lpe)
|
||||
pdata->notify_audio_lpe(dev_priv->audio.lpe.platdev, port - PORT_B);
|
||||
pdata->notify_audio_lpe(dev_priv->display.audio.lpe.platdev, port - PORT_B);
|
||||
|
||||
spin_unlock_irqrestore(&pdata->lpe_audio_slock, irqflags);
|
||||
}
|
||||
|
@ -70,7 +70,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
|
||||
|
||||
drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
|
||||
|
||||
i915->display->crtc_disable(to_intel_atomic_state(state), crtc);
|
||||
i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);
|
||||
|
||||
drm_atomic_state_put(state);
|
||||
|
||||
|
@ -487,7 +487,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
|
||||
|
||||
void intel_overlay_reset(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_overlay *overlay = dev_priv->overlay;
|
||||
struct intel_overlay *overlay = dev_priv->display.overlay;
|
||||
|
||||
if (!overlay)
|
||||
return;
|
||||
@ -1113,7 +1113,7 @@ int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_i915_gem_object *new_bo;
|
||||
int ret;
|
||||
|
||||
overlay = dev_priv->overlay;
|
||||
overlay = dev_priv->display.overlay;
|
||||
if (!overlay) {
|
||||
drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
|
||||
return -ENODEV;
|
||||
@ -1273,7 +1273,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
|
||||
struct intel_overlay *overlay;
|
||||
int ret;
|
||||
|
||||
overlay = dev_priv->overlay;
|
||||
overlay = dev_priv->display.overlay;
|
||||
if (!overlay) {
|
||||
drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
|
||||
return -ENODEV;
|
||||
@ -1416,7 +1416,7 @@ void intel_overlay_setup(struct drm_i915_private *dev_priv)
|
||||
update_polyphase_filter(overlay->regs);
|
||||
update_reg_attrs(overlay, overlay->regs);
|
||||
|
||||
dev_priv->overlay = overlay;
|
||||
dev_priv->display.overlay = overlay;
|
||||
drm_info(&dev_priv->drm, "Initialized overlay support.\n");
|
||||
return;
|
||||
|
||||
@ -1428,7 +1428,7 @@ void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_overlay *overlay;
|
||||
|
||||
overlay = fetch_and_zero(&dev_priv->overlay);
|
||||
overlay = fetch_and_zero(&dev_priv->display.overlay);
|
||||
if (!overlay)
|
||||
return;
|
||||
|
||||
@ -1457,7 +1457,7 @@ struct intel_overlay_error_state {
|
||||
struct intel_overlay_error_state *
|
||||
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_overlay *overlay = dev_priv->overlay;
|
||||
struct intel_overlay *overlay = dev_priv->display.overlay;
|
||||
struct intel_overlay_error_state *error;
|
||||
|
||||
if (!overlay || !overlay->active)
|
||||
|
@ -522,7 +522,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
|
||||
}
|
||||
|
||||
/* Check if any DPLLs are using the SSC source */
|
||||
for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
|
||||
for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
|
||||
u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
|
||||
|
||||
if (!(temp & DPLL_VCO_ENABLE))
|
||||
|
@ -311,7 +311,7 @@ void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
|
||||
* can even allow for smooth boot transitions if the BIOS
|
||||
* fb is large enough for the active pipe configuration.
|
||||
*/
|
||||
dev_priv->display->get_initial_plane_config(crtc, &plane_config);
|
||||
dev_priv->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
|
||||
|
||||
/*
|
||||
* If the fb is shared between multiple heads, we'll
|
||||
|
@ -28,7 +28,7 @@ intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
|
||||
* See intel_pps_reset_all() why we need a power domain reference here.
|
||||
*/
|
||||
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
|
||||
mutex_lock(&dev_priv->pps_mutex);
|
||||
mutex_lock(&dev_priv->display.pps.mutex);
|
||||
|
||||
return wakeref;
|
||||
}
|
||||
@ -38,7 +38,7 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
|
||||
mutex_unlock(&dev_priv->pps_mutex);
|
||||
mutex_unlock(&dev_priv->display.pps.mutex);
|
||||
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
|
||||
|
||||
return 0;
|
||||
@ -163,7 +163,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
enum pipe pipe;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
/* We should never land here with regular DP ports */
|
||||
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
|
||||
@ -212,7 +212,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
|
||||
struct intel_connector *connector = intel_dp->attached_connector;
|
||||
int backlight_controller = connector->panel.vbt.backlight.controller;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
/* We should never land here with regular DP ports */
|
||||
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
|
||||
@ -282,7 +282,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
enum port port = dig_port->base.port;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
/* try to find a pipe with this port selected */
|
||||
/* first pick one where the panel is on */
|
||||
@ -407,7 +407,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
|
||||
intel_dp->pps.pps_pipe == INVALID_PIPE)
|
||||
@ -420,7 +420,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
|
||||
intel_dp->pps.pps_pipe == INVALID_PIPE)
|
||||
@ -463,7 +463,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
i915_reg_t pp_stat_reg, pp_ctrl_reg;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
intel_pps_verify_state(intel_dp);
|
||||
|
||||
@ -556,7 +556,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
u32 control;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
|
||||
if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
|
||||
@ -580,7 +580,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
|
||||
i915_reg_t pp_stat_reg, pp_ctrl_reg;
|
||||
bool need_to_disable = !intel_dp->pps.want_panel_vdd;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
if (!intel_dp_is_edp(intel_dp))
|
||||
return false;
|
||||
@ -657,7 +657,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
|
||||
u32 pp;
|
||||
i915_reg_t pp_stat_reg, pp_ctrl_reg;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
|
||||
|
||||
@ -748,7 +748,7 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
if (!intel_dp_is_edp(intel_dp))
|
||||
return;
|
||||
@ -771,7 +771,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
|
||||
u32 pp;
|
||||
i915_reg_t pp_ctrl_reg;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
if (!intel_dp_is_edp(intel_dp))
|
||||
return;
|
||||
@ -832,7 +832,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
|
||||
u32 pp;
|
||||
i915_reg_t pp_ctrl_reg;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
if (!intel_dp_is_edp(intel_dp))
|
||||
return;
|
||||
@ -991,7 +991,7 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
|
||||
{
|
||||
struct intel_encoder *encoder;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
for_each_intel_dp(&dev_priv->drm, encoder) {
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
||||
@ -1021,7 +1021,7 @@ void vlv_pps_init(struct intel_encoder *encoder,
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
|
||||
|
||||
@ -1064,7 +1064,7 @@ static void pps_vdd_init(struct intel_dp *intel_dp)
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
if (!edp_have_panel_vdd(intel_dp))
|
||||
return;
|
||||
@ -1176,7 +1176,7 @@ static void pps_init_delays_bios(struct intel_dp *intel_dp,
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))
|
||||
intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);
|
||||
@ -1223,7 +1223,7 @@ static void pps_init_delays_spec(struct intel_dp *intel_dp,
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
|
||||
* our hw here, which are all in 100usec. */
|
||||
@ -1246,7 +1246,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
|
||||
struct edp_power_seq cur, vbt, spec,
|
||||
*final = &intel_dp->pps.pps_delays;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
/* already initialized? */
|
||||
if (pps_delays_valid(final))
|
||||
@ -1312,7 +1312,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
|
||||
enum port port = dp_to_dig_port(intel_dp)->base.port;
|
||||
const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
|
||||
|
||||
lockdep_assert_held(&dev_priv->pps_mutex);
|
||||
lockdep_assert_held(&dev_priv->display.pps.mutex);
|
||||
|
||||
intel_pps_get_registers(intel_dp, ®s);
|
||||
|
||||
@ -1487,11 +1487,11 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
|
||||
void intel_pps_setup(struct drm_i915_private *i915)
|
||||
{
|
||||
if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
|
||||
i915->pps_mmio_base = PCH_PPS_BASE;
|
||||
i915->display.pps.mmio_base = PCH_PPS_BASE;
|
||||
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
|
||||
i915->pps_mmio_base = VLV_PPS_BASE;
|
||||
i915->display.pps.mmio_base = VLV_PPS_BASE;
|
||||
else
|
||||
i915->pps_mmio_base = PPS_BASE;
|
||||
i915->display.pps.mmio_base = PPS_BASE;
|
||||
}
|
||||
|
||||
void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
|
||||
|
@ -706,7 +706,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
|
||||
if (crtc_state->enable_psr2_sel_fetch)
|
||||
return;
|
||||
|
||||
if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
|
||||
if (!(dev_priv->display.dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
|
||||
return;
|
||||
|
||||
if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
|
||||
@ -1863,7 +1863,9 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(state->base.dev);
|
||||
const struct intel_crtc_state *crtc_state =
|
||||
const struct intel_crtc_state *old_crtc_state =
|
||||
intel_atomic_get_old_crtc_state(state, crtc);
|
||||
const struct intel_crtc_state *new_crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
struct intel_encoder *encoder;
|
||||
|
||||
@ -1871,7 +1873,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
|
||||
return;
|
||||
|
||||
for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
|
||||
crtc_state->uapi.encoder_mask) {
|
||||
old_crtc_state->uapi.encoder_mask) {
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
||||
struct intel_psr *psr = &intel_dp->psr;
|
||||
bool needs_to_disable = false;
|
||||
@ -1884,10 +1886,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
|
||||
* - All planes will go inactive
|
||||
* - Changing between PSR versions
|
||||
*/
|
||||
needs_to_disable |= intel_crtc_needs_modeset(crtc_state);
|
||||
needs_to_disable |= !crtc_state->has_psr;
|
||||
needs_to_disable |= !crtc_state->active_planes;
|
||||
needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled;
|
||||
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
|
||||
needs_to_disable |= !new_crtc_state->has_psr;
|
||||
needs_to_disable |= !new_crtc_state->active_planes;
|
||||
needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled;
|
||||
|
||||
if (psr->enabled && needs_to_disable)
|
||||
intel_psr_disable_locked(intel_dp);
|
||||
|
@ -191,6 +191,9 @@ static struct intel_quirk intel_quirks[] = {
|
||||
/* ASRock ITX*/
|
||||
{ 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
|
||||
{ 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
|
||||
/* ECS Liva Q2 */
|
||||
{ 0x3185, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time },
|
||||
{ 0x3184, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time },
|
||||
};
|
||||
|
||||
void intel_init_quirks(struct drm_i915_private *i915)
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -246,7 +246,7 @@ static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
|
||||
struct intel_uncore *uncore = &i915->uncore;
|
||||
u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
|
||||
u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
|
||||
u32 mask = 0;
|
||||
u32 val;
|
||||
|
||||
@ -279,7 +279,7 @@ static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
|
||||
enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
|
||||
u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
|
||||
u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
|
||||
struct intel_uncore *uncore = &i915->uncore;
|
||||
u32 val, mask = 0;
|
||||
|
||||
|
@ -344,7 +344,7 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
|
||||
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
|
||||
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
||||
|
||||
if (!INTEL_INFO(i915)->display.has_dsc)
|
||||
if (!RUNTIME_INFO(i915)->has_dsc)
|
||||
return false;
|
||||
|
||||
if (DISPLAY_VER(i915) >= 12)
|
||||
@ -597,6 +597,8 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
|
||||
DSC_VER_MIN_SHIFT |
|
||||
vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
|
||||
vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
|
||||
if (vdsc_cfg->dsc_version_minor == 2)
|
||||
pps_val |= DSC_ALT_ICH_SEL;
|
||||
if (vdsc_cfg->block_pred_enable)
|
||||
pps_val |= DSC_BLOCK_PREDICTION;
|
||||
if (vdsc_cfg->convert_rgb)
|
||||
|
@ -142,11 +142,16 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
|
||||
* For XE_LPD+, we use guardband and pipeline override
|
||||
* is deprecated.
|
||||
*/
|
||||
if (DISPLAY_VER(i915) >= 13)
|
||||
if (DISPLAY_VER(i915) >= 13) {
|
||||
/*
|
||||
* FIXME: Subtract Window2 delay from below value.
|
||||
*
|
||||
* Window2 specifies time required to program DSB (Window2) in
|
||||
* number of scan lines. Assuming 0 for no DSB.
|
||||
*/
|
||||
crtc_state->vrr.guardband =
|
||||
crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
|
||||
i915->window2_delay;
|
||||
else
|
||||
crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
|
||||
} else {
|
||||
/*
|
||||
* FIXME: s/4/framestart_delay/ to get consistent
|
||||
* earliest/latest points for register latching regardless
|
||||
@ -159,6 +164,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
|
||||
*/
|
||||
crtc_state->vrr.pipeline_full =
|
||||
min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
|
||||
}
|
||||
|
||||
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
|
||||
}
|
||||
|
@ -1928,7 +1928,7 @@ static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
|
||||
static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
|
||||
enum intel_fbc_id fbc_id, enum plane_id plane_id)
|
||||
{
|
||||
if ((INTEL_INFO(dev_priv)->display.fbc_mask & BIT(fbc_id)) == 0)
|
||||
if ((RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
|
||||
return false;
|
||||
|
||||
return plane_id == PLANE_PRIMARY;
|
||||
|
@ -1933,8 +1933,11 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
|
||||
else
|
||||
intel_dsi->ports = BIT(port);
|
||||
|
||||
intel_dsi->dcs_backlight_ports = intel_connector->panel.vbt.dsi.bl_ports;
|
||||
intel_dsi->dcs_cabc_ports = intel_connector->panel.vbt.dsi.cabc_ports;
|
||||
if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
|
||||
intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
|
||||
|
||||
if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
|
||||
intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
|
||||
|
||||
/* Create a DSI host (and a device) for each port. */
|
||||
for_each_dsi_port(port, intel_dsi->ports) {
|
||||
|
@ -20,7 +20,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
|
||||
unsigned int sg_page_sizes)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(obj->base.dev);
|
||||
unsigned long supported = INTEL_INFO(i915)->page_sizes;
|
||||
unsigned long supported = RUNTIME_INFO(i915)->page_sizes;
|
||||
bool shrinkable;
|
||||
int i;
|
||||
|
||||
@ -66,7 +66,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
|
||||
shrinkable = i915_gem_object_is_shrinkable(obj);
|
||||
|
||||
if (i915_gem_object_is_tiled(obj) &&
|
||||
i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
|
||||
i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) {
|
||||
GEM_BUG_ON(i915_gem_object_has_tiling_quirk(obj));
|
||||
i915_gem_object_set_tiling_quirk(obj);
|
||||
GEM_BUG_ON(!list_empty(&obj->mm.link));
|
||||
|
@ -18,10 +18,12 @@
|
||||
#include "gt/intel_region_lmem.h"
|
||||
#include "i915_drv.h"
|
||||
#include "i915_gem_stolen.h"
|
||||
#include "i915_pci.h"
|
||||
#include "i915_reg.h"
|
||||
#include "i915_utils.h"
|
||||
#include "i915_vgpu.h"
|
||||
#include "intel_mchbar_regs.h"
|
||||
#include "intel_pci_config.h"
|
||||
|
||||
/*
|
||||
* The BIOS typically reserves some of the system's memory for the exclusive
|
||||
@ -827,10 +829,13 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
|
||||
if (WARN_ON_ONCE(instance))
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
|
||||
return ERR_PTR(-ENXIO);
|
||||
|
||||
/* Use DSM base address instead for stolen memory */
|
||||
dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
|
||||
if (IS_DG1(uncore->i915)) {
|
||||
lmem_size = pci_resource_len(pdev, 2);
|
||||
lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
|
||||
if (WARN_ON(lmem_size < dsm_base))
|
||||
return ERR_PTR(-ENODEV);
|
||||
} else {
|
||||
@ -842,11 +847,11 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
|
||||
}
|
||||
|
||||
dsm_size = lmem_size - dsm_base;
|
||||
if (pci_resource_len(pdev, 2) < lmem_size) {
|
||||
if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
|
||||
io_start = 0;
|
||||
io_size = 0;
|
||||
} else {
|
||||
io_start = pci_resource_start(pdev, 2) + dsm_base;
|
||||
io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base;
|
||||
io_size = dsm_size;
|
||||
}
|
||||
|
||||
|
@ -278,7 +278,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
|
||||
*/
|
||||
if (i915_gem_object_has_pages(obj) &&
|
||||
obj->mm.madv == I915_MADV_WILLNEED &&
|
||||
i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
|
||||
i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) {
|
||||
if (tiling == I915_TILING_NONE) {
|
||||
GEM_BUG_ON(!i915_gem_object_has_tiling_quirk(obj));
|
||||
i915_gem_object_clear_tiling_quirk(obj);
|
||||
@ -458,7 +458,7 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
|
||||
}
|
||||
|
||||
/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
|
||||
if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
|
||||
if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
|
||||
args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
|
||||
else
|
||||
args->phys_swizzle_mode = args->swizzle_mode;
|
||||
|
@ -358,7 +358,7 @@ fake_huge_pages_object(struct drm_i915_private *i915, u64 size, bool single)
|
||||
static int igt_check_page_sizes(struct i915_vma *vma)
|
||||
{
|
||||
struct drm_i915_private *i915 = vma->vm->i915;
|
||||
unsigned int supported = INTEL_INFO(i915)->page_sizes;
|
||||
unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
|
||||
struct drm_i915_gem_object *obj = vma->obj;
|
||||
int err;
|
||||
|
||||
@ -419,7 +419,7 @@ static int igt_mock_exhaust_device_supported_pages(void *arg)
|
||||
{
|
||||
struct i915_ppgtt *ppgtt = arg;
|
||||
struct drm_i915_private *i915 = ppgtt->vm.i915;
|
||||
unsigned int saved_mask = INTEL_INFO(i915)->page_sizes;
|
||||
unsigned int saved_mask = RUNTIME_INFO(i915)->page_sizes;
|
||||
struct drm_i915_gem_object *obj;
|
||||
struct i915_vma *vma;
|
||||
int i, j, single;
|
||||
@ -438,7 +438,7 @@ static int igt_mock_exhaust_device_supported_pages(void *arg)
|
||||
combination |= page_sizes[j];
|
||||
}
|
||||
|
||||
mkwrite_device_info(i915)->page_sizes = combination;
|
||||
RUNTIME_INFO(i915)->page_sizes = combination;
|
||||
|
||||
for (single = 0; single <= 1; ++single) {
|
||||
obj = fake_huge_pages_object(i915, combination, !!single);
|
||||
@ -485,7 +485,7 @@ static int igt_mock_exhaust_device_supported_pages(void *arg)
|
||||
out_put:
|
||||
i915_gem_object_put(obj);
|
||||
out_device:
|
||||
mkwrite_device_info(i915)->page_sizes = saved_mask;
|
||||
RUNTIME_INFO(i915)->page_sizes = saved_mask;
|
||||
|
||||
return err;
|
||||
}
|
||||
@ -495,7 +495,7 @@ static int igt_mock_memory_region_huge_pages(void *arg)
|
||||
const unsigned int flags[] = { 0, I915_BO_ALLOC_CONTIGUOUS };
|
||||
struct i915_ppgtt *ppgtt = arg;
|
||||
struct drm_i915_private *i915 = ppgtt->vm.i915;
|
||||
unsigned long supported = INTEL_INFO(i915)->page_sizes;
|
||||
unsigned long supported = RUNTIME_INFO(i915)->page_sizes;
|
||||
struct intel_memory_region *mem;
|
||||
struct drm_i915_gem_object *obj;
|
||||
struct i915_vma *vma;
|
||||
@ -573,7 +573,7 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg)
|
||||
{
|
||||
struct i915_ppgtt *ppgtt = arg;
|
||||
struct drm_i915_private *i915 = ppgtt->vm.i915;
|
||||
unsigned long supported = INTEL_INFO(i915)->page_sizes;
|
||||
unsigned long supported = RUNTIME_INFO(i915)->page_sizes;
|
||||
struct drm_i915_gem_object *obj;
|
||||
int bit;
|
||||
int err;
|
||||
@ -1390,7 +1390,7 @@ out_put:
|
||||
static int igt_ppgtt_sanity_check(void *arg)
|
||||
{
|
||||
struct drm_i915_private *i915 = arg;
|
||||
unsigned int supported = INTEL_INFO(i915)->page_sizes;
|
||||
unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
|
||||
struct {
|
||||
igt_create_fn fn;
|
||||
unsigned int flags;
|
||||
@ -1764,8 +1764,8 @@ int i915_gem_huge_page_mock_selftests(void)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Pretend to be a device which supports the 48b PPGTT */
|
||||
mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
|
||||
mkwrite_device_info(dev_priv)->ppgtt_size = 48;
|
||||
RUNTIME_INFO(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
|
||||
RUNTIME_INFO(dev_priv)->ppgtt_size = 48;
|
||||
|
||||
ppgtt = i915_ppgtt_create(to_gt(dev_priv), 0);
|
||||
if (IS_ERR(ppgtt)) {
|
||||
|
@ -711,7 +711,7 @@ static bool bad_swizzling(struct drm_i915_private *i915)
|
||||
{
|
||||
struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
|
||||
|
||||
if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
|
||||
if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
|
||||
return true;
|
||||
|
||||
if (has_bit17_swizzle(ggtt->bit_6_swizzle_x) ||
|
||||
|
@ -367,7 +367,7 @@ static int igt_partial_tiling(void *arg)
|
||||
unsigned int pitch;
|
||||
struct tile tile;
|
||||
|
||||
if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
|
||||
if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
|
||||
/*
|
||||
* The swizzling pattern is actually unknown as it
|
||||
* varies based on physical address of each page.
|
||||
@ -464,7 +464,7 @@ static int igt_smoke_tiling(void *arg)
|
||||
* Remember to look at the st_seed if we see a flip-flop in BAT!
|
||||
*/
|
||||
|
||||
if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
|
||||
if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
|
||||
return 0;
|
||||
|
||||
obj = huge_gem_object(i915,
|
||||
|
@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
|
||||
u16 vdbox_mask;
|
||||
u16 vebox_mask;
|
||||
|
||||
info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
|
||||
info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
|
||||
|
||||
if (GRAPHICS_VER(i915) < 11)
|
||||
return info->engine_mask;
|
||||
|
@ -16,7 +16,9 @@
|
||||
#include "intel_ggtt_gmch.h"
|
||||
#include "intel_gt.h"
|
||||
#include "intel_gt_regs.h"
|
||||
#include "intel_pci_config.h"
|
||||
#include "i915_drv.h"
|
||||
#include "i915_pci.h"
|
||||
#include "i915_scatterlist.h"
|
||||
#include "i915_utils.h"
|
||||
#include "i915_vgpu.h"
|
||||
@ -869,8 +871,8 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
|
||||
u32 pte_flags;
|
||||
int ret;
|
||||
|
||||
GEM_WARN_ON(pci_resource_len(pdev, 0) != gen6_gttmmadr_size(i915));
|
||||
phys_addr = pci_resource_start(pdev, 0) + gen6_gttadr_offset(i915);
|
||||
GEM_WARN_ON(pci_resource_len(pdev, GTTMMADR_BAR) != gen6_gttmmadr_size(i915));
|
||||
phys_addr = pci_resource_start(pdev, GTTMMADR_BAR) + gen6_gttadr_offset(i915);
|
||||
|
||||
/*
|
||||
* On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
|
||||
@ -930,7 +932,10 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
|
||||
u16 snb_gmch_ctl;
|
||||
|
||||
if (!HAS_LMEM(i915)) {
|
||||
ggtt->gmadr = pci_resource(pdev, 2);
|
||||
if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
|
||||
return -ENXIO;
|
||||
|
||||
ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR);
|
||||
ggtt->mappable_end = resource_size(&ggtt->gmadr);
|
||||
}
|
||||
|
||||
@ -1084,7 +1089,10 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
|
||||
unsigned int size;
|
||||
u16 snb_gmch_ctl;
|
||||
|
||||
ggtt->gmadr = pci_resource(pdev, 2);
|
||||
if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
|
||||
return -ENXIO;
|
||||
|
||||
ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR);
|
||||
ggtt->mappable_end = resource_size(&ggtt->gmadr);
|
||||
|
||||
/*
|
||||
|
@ -727,7 +727,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
|
||||
* bit17 dependent, and so we need to also prevent the pages
|
||||
* from being moved.
|
||||
*/
|
||||
i915->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
|
||||
i915->gem_quirks |= GEM_QUIRK_PIN_SWIZZLED_PAGES;
|
||||
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
||||
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
||||
}
|
||||
|
@ -26,6 +26,7 @@
|
||||
#include "intel_gt_requests.h"
|
||||
#include "intel_migrate.h"
|
||||
#include "intel_mocs.h"
|
||||
#include "intel_pci_config.h"
|
||||
#include "intel_pm.h"
|
||||
#include "intel_rc6.h"
|
||||
#include "intel_renderstate.h"
|
||||
@ -830,7 +831,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
|
||||
unsigned int mmio_bar;
|
||||
int ret;
|
||||
|
||||
mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
|
||||
mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
|
||||
phys_addr = pci_resource_start(pdev, mmio_bar);
|
||||
|
||||
/*
|
||||
|
@ -312,7 +312,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
|
||||
ppgtt->vm.gt = gt;
|
||||
ppgtt->vm.i915 = i915;
|
||||
ppgtt->vm.dma = i915->drm.dev;
|
||||
ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
|
||||
ppgtt->vm.total = BIT_ULL(RUNTIME_INFO(i915)->ppgtt_size);
|
||||
ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;
|
||||
|
||||
dma_resv_init(&ppgtt->vm._resv);
|
||||
|
@ -4,8 +4,10 @@
|
||||
*/
|
||||
|
||||
#include "i915_drv.h"
|
||||
#include "i915_pci.h"
|
||||
#include "i915_reg.h"
|
||||
#include "intel_memory_region.h"
|
||||
#include "intel_pci_config.h"
|
||||
#include "intel_region_lmem.h"
|
||||
#include "intel_region_ttm.h"
|
||||
#include "gem/i915_gem_lmem.h"
|
||||
@ -45,7 +47,6 @@ _resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
|
||||
drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
|
||||
}
|
||||
|
||||
#define LMEM_BAR_NUM 2
|
||||
static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
|
||||
@ -56,15 +57,14 @@ static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t
|
||||
u32 pci_cmd;
|
||||
int i;
|
||||
|
||||
current_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
|
||||
current_size = roundup_pow_of_two(pci_resource_len(pdev, GEN12_LMEM_BAR));
|
||||
|
||||
if (i915->params.lmem_bar_size) {
|
||||
u32 bar_sizes;
|
||||
|
||||
rebar_size = i915->params.lmem_bar_size *
|
||||
(resource_size_t)SZ_1M;
|
||||
bar_sizes = pci_rebar_get_possible_sizes(pdev,
|
||||
LMEM_BAR_NUM);
|
||||
bar_sizes = pci_rebar_get_possible_sizes(pdev, GEN12_LMEM_BAR);
|
||||
|
||||
if (rebar_size == current_size)
|
||||
return;
|
||||
@ -107,7 +107,7 @@ static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t
|
||||
pci_write_config_dword(pdev, PCI_COMMAND,
|
||||
pci_cmd & ~PCI_COMMAND_MEMORY);
|
||||
|
||||
_resize_bar(i915, LMEM_BAR_NUM, rebar_size);
|
||||
_resize_bar(i915, GEN12_LMEM_BAR, rebar_size);
|
||||
|
||||
pci_assign_unassigned_bus_resources(pdev->bus);
|
||||
pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
|
||||
@ -202,6 +202,9 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
|
||||
if (!IS_DGFX(i915))
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
|
||||
return ERR_PTR(-ENXIO);
|
||||
|
||||
if (HAS_FLAT_CCS(i915)) {
|
||||
resource_size_t lmem_range;
|
||||
u64 tile_stolen, flat_ccs_base;
|
||||
@ -236,8 +239,8 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
|
||||
mul_u32_u32(i915->params.lmem_size, SZ_1M));
|
||||
}
|
||||
|
||||
io_start = pci_resource_start(pdev, 2);
|
||||
io_size = min(pci_resource_len(pdev, 2), lmem_size);
|
||||
io_start = pci_resource_start(pdev, GEN12_LMEM_BAR);
|
||||
io_size = min(pci_resource_len(pdev, GEN12_LMEM_BAR), lmem_size);
|
||||
if (!io_size)
|
||||
return ERR_PTR(-EIO);
|
||||
|
||||
|
@ -382,7 +382,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
|
||||
static void gen9_sseu_info_init(struct intel_gt *gt)
|
||||
{
|
||||
struct drm_i915_private *i915 = gt->i915;
|
||||
struct intel_device_info *info = mkwrite_device_info(i915);
|
||||
struct sseu_dev_info *sseu = >->info.sseu;
|
||||
struct intel_uncore *uncore = gt->uncore;
|
||||
u32 fuse2, eu_disable, subslice_mask;
|
||||
@ -471,10 +470,10 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
|
||||
|
||||
if (IS_GEN9_LP(i915)) {
|
||||
#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
|
||||
info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
|
||||
RUNTIME_INFO(i915)->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
|
||||
|
||||
sseu->min_eu_in_pool = 0;
|
||||
if (info->has_pooled_eu) {
|
||||
if (HAS_POOLED_EU(i915)) {
|
||||
if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
|
||||
sseu->min_eu_in_pool = 3;
|
||||
else if (IS_SS_DISABLED(1))
|
||||
|
@ -33,6 +33,7 @@
|
||||
|
||||
#include "i915_drv.h"
|
||||
#include "gvt.h"
|
||||
#include "intel_pci_config.h"
|
||||
|
||||
enum {
|
||||
INTEL_GVT_PCI_BAR_GTTMMIO = 0,
|
||||
@ -353,9 +354,9 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
|
||||
memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
|
||||
|
||||
vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =
|
||||
pci_resource_len(pdev, 0);
|
||||
pci_resource_len(pdev, GTTMMADR_BAR);
|
||||
vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =
|
||||
pci_resource_len(pdev, 2);
|
||||
pci_resource_len(pdev, GTT_APERTURE_BAR);
|
||||
|
||||
memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);
|
||||
|
||||
|
@ -498,7 +498,7 @@ static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
|
||||
|
||||
switch (wrpll_ctl & WRPLL_REF_MASK) {
|
||||
case WRPLL_REF_PCH_SSC:
|
||||
refclk = vgpu->gvt->gt->i915->dpll.ref_clks.ssc;
|
||||
refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc;
|
||||
break;
|
||||
case WRPLL_REF_LCPLL:
|
||||
refclk = 2700000;
|
||||
@ -529,7 +529,7 @@ out:
|
||||
static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
|
||||
{
|
||||
u32 dp_br = 0;
|
||||
int refclk = vgpu->gvt->gt->i915->dpll.ref_clks.nssc;
|
||||
int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc;
|
||||
enum dpio_phy phy = DPIO_PHY0;
|
||||
enum dpio_channel ch = DPIO_CH0;
|
||||
struct dpll clock = {0};
|
||||
|
@ -66,8 +66,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
|
||||
|
||||
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
|
||||
|
||||
intel_device_info_print_static(INTEL_INFO(i915), &p);
|
||||
intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
|
||||
intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p);
|
||||
i915_print_iommu_status(i915, &p);
|
||||
intel_gt_info_print(&to_gt(i915)->info, &p);
|
||||
intel_driver_caps_print(&i915->caps, &p);
|
||||
@ -411,7 +410,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
|
||||
seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
|
||||
swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
|
||||
|
||||
if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
|
||||
if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
|
||||
seq_puts(m, "L-shaped memory detected\n");
|
||||
|
||||
/* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
|
||||
|
@ -252,8 +252,8 @@ static int i915_workqueues_init(struct drm_i915_private *dev_priv)
|
||||
if (dev_priv->wq == NULL)
|
||||
goto out_err;
|
||||
|
||||
dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
|
||||
if (dev_priv->hotplug.dp_wq == NULL)
|
||||
dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
|
||||
if (dev_priv->display.hotplug.dp_wq == NULL)
|
||||
goto out_free_wq;
|
||||
|
||||
return 0;
|
||||
@ -268,7 +268,7 @@ out_err:
|
||||
|
||||
static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
destroy_workqueue(dev_priv->hotplug.dp_wq);
|
||||
destroy_workqueue(dev_priv->display.hotplug.dp_wq);
|
||||
destroy_workqueue(dev_priv->wq);
|
||||
}
|
||||
|
||||
@ -335,9 +335,9 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
|
||||
mutex_init(&dev_priv->sb_lock);
|
||||
cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
|
||||
|
||||
mutex_init(&dev_priv->audio.mutex);
|
||||
mutex_init(&dev_priv->wm.wm_mutex);
|
||||
mutex_init(&dev_priv->pps_mutex);
|
||||
mutex_init(&dev_priv->display.audio.mutex);
|
||||
mutex_init(&dev_priv->display.wm.wm_mutex);
|
||||
mutex_init(&dev_priv->display.pps.mutex);
|
||||
mutex_init(&dev_priv->hdcp_comp_mutex);
|
||||
|
||||
i915_memcpy_init_early(dev_priv);
|
||||
@ -793,8 +793,8 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
|
||||
INTEL_INFO(dev_priv)->platform),
|
||||
GRAPHICS_VER(dev_priv));
|
||||
|
||||
intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
|
||||
intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
|
||||
intel_device_info_print(INTEL_INFO(dev_priv),
|
||||
RUNTIME_INFO(dev_priv), &p);
|
||||
i915_print_iommu_status(dev_priv, &p);
|
||||
intel_gt_info_print(&to_gt(dev_priv)->info, &p);
|
||||
}
|
||||
@ -814,6 +814,7 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
const struct intel_device_info *match_info =
|
||||
(struct intel_device_info *)ent->driver_data;
|
||||
struct intel_device_info *device_info;
|
||||
struct intel_runtime_info *runtime;
|
||||
struct drm_i915_private *i915;
|
||||
|
||||
i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
|
||||
@ -829,7 +830,11 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
/* Setup the write-once "constant" device info */
|
||||
device_info = mkwrite_device_info(i915);
|
||||
memcpy(device_info, match_info, sizeof(*device_info));
|
||||
RUNTIME_INFO(i915)->device_id = pdev->device;
|
||||
|
||||
/* Initialize initial runtime info from static const data and pdev. */
|
||||
runtime = RUNTIME_INFO(i915);
|
||||
memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
|
||||
runtime->device_id = pdev->device;
|
||||
|
||||
return i915;
|
||||
}
|
||||
|
@ -39,14 +39,12 @@
|
||||
|
||||
#include "display/intel_cdclk.h"
|
||||
#include "display/intel_display.h"
|
||||
#include "display/intel_display_core.h"
|
||||
#include "display/intel_display_power.h"
|
||||
#include "display/intel_dmc.h"
|
||||
#include "display/intel_dpll_mgr.h"
|
||||
#include "display/intel_dsb.h"
|
||||
#include "display/intel_fbc.h"
|
||||
#include "display/intel_frontbuffer.h"
|
||||
#include "display/intel_global_state.h"
|
||||
#include "display/intel_gmbus.h"
|
||||
#include "display/intel_opregion.h"
|
||||
|
||||
#include "gem/i915_gem_context_types.h"
|
||||
@ -70,80 +68,27 @@
|
||||
#include "intel_device_info.h"
|
||||
#include "intel_memory_region.h"
|
||||
#include "intel_pch.h"
|
||||
#include "intel_pm_types.h"
|
||||
#include "intel_runtime_pm.h"
|
||||
#include "intel_step.h"
|
||||
#include "intel_uncore.h"
|
||||
#include "intel_wopcm.h"
|
||||
|
||||
struct dpll;
|
||||
struct drm_i915_clock_gating_funcs;
|
||||
struct drm_i915_gem_object;
|
||||
struct drm_i915_private;
|
||||
struct intel_atomic_state;
|
||||
struct intel_audio_funcs;
|
||||
struct intel_cdclk_config;
|
||||
struct intel_cdclk_funcs;
|
||||
struct intel_cdclk_state;
|
||||
struct intel_cdclk_vals;
|
||||
struct intel_color_funcs;
|
||||
struct intel_connector;
|
||||
struct intel_crtc;
|
||||
struct intel_dp;
|
||||
struct intel_dpll_funcs;
|
||||
struct intel_encoder;
|
||||
struct intel_fbdev;
|
||||
struct intel_fdi_funcs;
|
||||
struct intel_gmbus;
|
||||
struct intel_hotplug_funcs;
|
||||
struct intel_initial_plane_config;
|
||||
struct intel_limit;
|
||||
struct intel_overlay;
|
||||
struct intel_overlay_error_state;
|
||||
struct vlv_s0ix_state;
|
||||
|
||||
/* Threshold == 5 for long IRQs, 50 for short */
|
||||
#define HPD_STORM_DEFAULT_THRESHOLD 50
|
||||
|
||||
struct i915_hotplug {
|
||||
struct delayed_work hotplug_work;
|
||||
|
||||
const u32 *hpd, *pch_hpd;
|
||||
|
||||
struct {
|
||||
unsigned long last_jiffies;
|
||||
int count;
|
||||
enum {
|
||||
HPD_ENABLED = 0,
|
||||
HPD_DISABLED = 1,
|
||||
HPD_MARK_DISABLED = 2
|
||||
} state;
|
||||
} stats[HPD_NUM_PINS];
|
||||
u32 event_bits;
|
||||
u32 retry_bits;
|
||||
struct delayed_work reenable_work;
|
||||
|
||||
u32 long_port_mask;
|
||||
u32 short_port_mask;
|
||||
struct work_struct dig_port_work;
|
||||
|
||||
struct work_struct poll_init_work;
|
||||
bool poll_enabled;
|
||||
|
||||
unsigned int hpd_storm_threshold;
|
||||
/* Whether or not to count short HPD IRQs in HPD storms */
|
||||
u8 hpd_short_storm_enabled;
|
||||
|
||||
/*
|
||||
* if we get a HPD irq from DP and a HPD irq from non-DP
|
||||
* the non-DP HPD could block the workqueue on a mode config
|
||||
* mutex getting, that userspace may have taken. However
|
||||
* userspace is waiting on the DP workqueue to run which is
|
||||
* blocked behind the non-DP one.
|
||||
*/
|
||||
struct workqueue_struct *dp_wq;
|
||||
};
|
||||
|
||||
#define I915_GEM_GPU_DOMAINS \
|
||||
(I915_GEM_DOMAIN_RENDER | \
|
||||
I915_GEM_DOMAIN_SAMPLER | \
|
||||
@ -160,43 +105,13 @@ struct sdvo_device_mapping {
|
||||
u8 ddc_pin;
|
||||
};
|
||||
|
||||
/* functions used for watermark calcs for display. */
|
||||
struct drm_i915_wm_disp_funcs {
|
||||
/* update_wm is for legacy wm management */
|
||||
void (*update_wm)(struct drm_i915_private *dev_priv);
|
||||
int (*compute_pipe_wm)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
int (*compute_intermediate_wm)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void (*initial_watermarks)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void (*atomic_update_watermarks)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void (*optimize_watermarks)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
int (*compute_global_watermarks)(struct intel_atomic_state *state);
|
||||
};
|
||||
|
||||
struct drm_i915_display_funcs {
|
||||
/* Returns the active state of the crtc, and if the crtc is active,
|
||||
* fills out the pipe-config with the hw state. */
|
||||
bool (*get_pipe_config)(struct intel_crtc *,
|
||||
struct intel_crtc_state *);
|
||||
void (*get_initial_plane_config)(struct intel_crtc *,
|
||||
struct intel_initial_plane_config *);
|
||||
void (*crtc_enable)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void (*crtc_disable)(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void (*commit_modeset_enables)(struct intel_atomic_state *state);
|
||||
};
|
||||
|
||||
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
|
||||
|
||||
#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
|
||||
|
||||
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
|
||||
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
|
||||
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
|
||||
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
|
||||
#define QUIRK_INCREASE_T12_DELAY (1<<6)
|
||||
#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
|
||||
#define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
|
||||
@ -348,32 +263,11 @@ struct i915_selftest_stash {
|
||||
struct ida mock_region_instances;
|
||||
};
|
||||
|
||||
/* intel_audio.c private */
|
||||
struct intel_audio_private {
|
||||
/* Display internal audio functions */
|
||||
const struct intel_audio_funcs *funcs;
|
||||
|
||||
/* hda/i915 audio component */
|
||||
struct i915_audio_component *component;
|
||||
bool component_registered;
|
||||
/* mutex for audio/video sync */
|
||||
struct mutex mutex;
|
||||
int power_refcount;
|
||||
u32 freq_cntrl;
|
||||
|
||||
/* Used to save the pipe-to-encoder mapping for audio */
|
||||
struct intel_encoder *encoder_map[I915_MAX_PIPES];
|
||||
|
||||
/* necessary resource sharing with HDMI LPE audio driver. */
|
||||
struct {
|
||||
struct platform_device *platdev;
|
||||
int irq;
|
||||
} lpe;
|
||||
};
|
||||
|
||||
struct drm_i915_private {
|
||||
struct drm_device drm;
|
||||
|
||||
struct intel_display display;
|
||||
|
||||
/* FIXME: Device release actions should all be moved to drmm_ */
|
||||
bool do_release;
|
||||
|
||||
@ -417,27 +311,9 @@ struct drm_i915_private {
|
||||
|
||||
struct intel_wopcm wopcm;
|
||||
|
||||
struct intel_dmc dmc;
|
||||
|
||||
struct intel_gmbus *gmbus[GMBUS_NUM_PINS];
|
||||
|
||||
/** gmbus_mutex protects against concurrent usage of the single hw gmbus
|
||||
* controller on different i2c buses. */
|
||||
struct mutex gmbus_mutex;
|
||||
|
||||
/**
|
||||
* Base address of where the gmbus and gpio blocks are located (either
|
||||
* on PCH or on SoC for platforms without PCH).
|
||||
*/
|
||||
u32 gpio_mmio_base;
|
||||
|
||||
/* MMIO base address for MIPI regs */
|
||||
u32 mipi_mmio_base;
|
||||
|
||||
u32 pps_mmio_base;
|
||||
|
||||
wait_queue_head_t gmbus_wait_queue;
|
||||
|
||||
struct pci_dev *bridge_dev;
|
||||
|
||||
struct rb_root uabi_engines;
|
||||
@ -461,22 +337,15 @@ struct drm_i915_private {
|
||||
};
|
||||
u32 pipestat_irq_mask[I915_MAX_PIPES];
|
||||
|
||||
struct i915_hotplug hotplug;
|
||||
struct intel_fbc *fbc[I915_MAX_FBCS];
|
||||
struct intel_opregion opregion;
|
||||
struct intel_vbt_data vbt;
|
||||
|
||||
bool preserve_bios_swizzle;
|
||||
|
||||
/* overlay */
|
||||
struct intel_overlay *overlay;
|
||||
|
||||
/* backlight registers and fields in struct intel_panel */
|
||||
struct mutex backlight_lock;
|
||||
|
||||
/* protects panel power sequencer state */
|
||||
struct mutex pps_mutex;
|
||||
|
||||
unsigned int fsb_freq, mem_freq, is_ddr3;
|
||||
unsigned int skl_preferred_vco_freq;
|
||||
unsigned int max_cdclk_freq;
|
||||
@ -520,31 +389,11 @@ struct drm_i915_private {
|
||||
/* pm private clock gating functions */
|
||||
const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
|
||||
|
||||
/* pm display functions */
|
||||
const struct drm_i915_wm_disp_funcs *wm_disp;
|
||||
|
||||
/* irq display functions */
|
||||
const struct intel_hotplug_funcs *hotplug_funcs;
|
||||
|
||||
/* fdi display functions */
|
||||
const struct intel_fdi_funcs *fdi_funcs;
|
||||
|
||||
/* display pll funcs */
|
||||
const struct intel_dpll_funcs *dpll_funcs;
|
||||
|
||||
/* Display functions */
|
||||
const struct drm_i915_display_funcs *display;
|
||||
|
||||
/* Display internal color functions */
|
||||
const struct intel_color_funcs *color_funcs;
|
||||
|
||||
/* Display CDCLK functions */
|
||||
const struct intel_cdclk_funcs *cdclk_funcs;
|
||||
|
||||
/* PCH chipset type */
|
||||
enum intel_pch pch_type;
|
||||
unsigned short pch_id;
|
||||
|
||||
unsigned long gem_quirks;
|
||||
unsigned long quirks;
|
||||
|
||||
struct drm_atomic_state *modeset_restore_state;
|
||||
@ -554,25 +403,6 @@ struct drm_i915_private {
|
||||
|
||||
/* Kernel Modesetting */
|
||||
|
||||
/**
|
||||
* dpll and cdclk state is protected by connection_mutex
|
||||
* dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
|
||||
* Must be global rather than per dpll, because on some platforms plls
|
||||
* share registers.
|
||||
*/
|
||||
struct {
|
||||
struct mutex lock;
|
||||
|
||||
int num_shared_dpll;
|
||||
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
|
||||
const struct intel_dpll_mgr *mgr;
|
||||
|
||||
struct {
|
||||
int nssc;
|
||||
int ssc;
|
||||
} ref_clks;
|
||||
} dpll;
|
||||
|
||||
struct list_head global_obj_list;
|
||||
|
||||
struct i915_frontbuffer_tracking fb_tracking;
|
||||
@ -604,10 +434,6 @@ struct drm_i915_private {
|
||||
|
||||
struct i915_gpu_error gpu_error;
|
||||
|
||||
/* list of fbdev register on this device */
|
||||
struct intel_fbdev *fbdev;
|
||||
struct work_struct fbdev_suspend_work;
|
||||
|
||||
struct drm_property *broadcast_rgb_property;
|
||||
struct drm_property *force_audio_property;
|
||||
|
||||
@ -627,51 +453,6 @@ struct drm_i915_private {
|
||||
struct i915_suspend_saved_registers regfile;
|
||||
struct vlv_s0ix_state *vlv_s0ix_state;
|
||||
|
||||
enum {
|
||||
I915_SAGV_UNKNOWN = 0,
|
||||
I915_SAGV_DISABLED,
|
||||
I915_SAGV_ENABLED,
|
||||
I915_SAGV_NOT_CONTROLLED
|
||||
} sagv_status;
|
||||
|
||||
u32 sagv_block_time_us;
|
||||
|
||||
struct {
|
||||
/*
|
||||
* Raw watermark latency values:
|
||||
* in 0.1us units for WM0,
|
||||
* in 0.5us units for WM1+.
|
||||
*/
|
||||
/* primary */
|
||||
u16 pri_latency[5];
|
||||
/* sprite */
|
||||
u16 spr_latency[5];
|
||||
/* cursor */
|
||||
u16 cur_latency[5];
|
||||
/*
|
||||
* Raw watermark memory latency values
|
||||
* for SKL for all 8 levels
|
||||
* in 1us units.
|
||||
*/
|
||||
u16 skl_latency[8];
|
||||
|
||||
/* current hardware state */
|
||||
union {
|
||||
struct ilk_wm_values hw;
|
||||
struct vlv_wm_values vlv;
|
||||
struct g4x_wm_values g4x;
|
||||
};
|
||||
|
||||
u8 max_level;
|
||||
|
||||
/*
|
||||
* Should be held around atomic WM register writing; also
|
||||
* protects * intel_crtc->wm.active and
|
||||
* crtc_state->wm.need_postvbl_update.
|
||||
*/
|
||||
struct mutex wm_mutex;
|
||||
} wm;
|
||||
|
||||
struct dram_info {
|
||||
bool wm_lv_0_adjust_needed;
|
||||
u8 num_channels;
|
||||
@ -733,9 +514,6 @@ struct drm_i915_private {
|
||||
struct file *mmap_singleton;
|
||||
} gem;
|
||||
|
||||
/* Window2 specifies time required to program DSB (Window2) in number of scan lines */
|
||||
u8 window2_delay;
|
||||
|
||||
u8 pch_ssc_use;
|
||||
|
||||
/* For i915gm/i945gm vblank irq workaround */
|
||||
@ -756,8 +534,6 @@ struct drm_i915_private {
|
||||
|
||||
bool ipc_enabled;
|
||||
|
||||
struct intel_audio_private audio;
|
||||
|
||||
struct i915_pmu pmu;
|
||||
|
||||
struct i915_drm_clients clients;
|
||||
@ -828,26 +604,6 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
|
||||
|
||||
#define I915_GTT_OFFSET_NONE ((u32)-1)
|
||||
|
||||
/*
|
||||
* Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
|
||||
* considered to be the frontbuffer for the given plane interface-wise. This
|
||||
* doesn't mean that the hw necessarily already scans it out, but that any
|
||||
* rendering (by the cpu or gpu) will land in the frontbuffer eventually.
|
||||
*
|
||||
* We have one bit per pipe and per scanout plane type.
|
||||
*/
|
||||
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
|
||||
#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
|
||||
BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
|
||||
BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
|
||||
BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
|
||||
})
|
||||
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
|
||||
BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
|
||||
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
|
||||
GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
|
||||
INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
|
||||
|
||||
#define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
|
||||
#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
|
||||
#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
|
||||
@ -856,9 +612,9 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
|
||||
|
||||
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
|
||||
|
||||
#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics.ver)
|
||||
#define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics.ver, \
|
||||
INTEL_INFO(i915)->graphics.rel)
|
||||
#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ver)
|
||||
#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ver, \
|
||||
RUNTIME_INFO(i915)->graphics.rel)
|
||||
#define IS_GRAPHICS_VER(i915, from, until) \
|
||||
(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
|
||||
|
||||
@ -1210,7 +966,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
||||
|
||||
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
|
||||
|
||||
#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
|
||||
#define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
|
||||
#define HAS_PPGTT(dev_priv) \
|
||||
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
|
||||
#define HAS_FULL_PPGTT(dev_priv) \
|
||||
@ -1218,7 +974,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
||||
|
||||
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
|
||||
GEM_BUG_ON((sizes) == 0); \
|
||||
((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
|
||||
((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
|
||||
})
|
||||
|
||||
#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
|
||||
@ -1249,13 +1005,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
||||
#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
|
||||
|
||||
#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
|
||||
#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.fbc_mask != 0)
|
||||
#define HAS_FBC(dev_priv) (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
|
||||
#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
|
||||
|
||||
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
|
||||
|
||||
#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
|
||||
#define HAS_DP20(dev_priv) (IS_DG2(dev_priv))
|
||||
#define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
|
||||
|
||||
#define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
|
||||
#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
|
||||
@ -1264,7 +1020,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
||||
#define HAS_PSR_HW_TRACKING(dev_priv) \
|
||||
(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
|
||||
#define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
|
||||
#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
|
||||
#define HAS_TRANSCODER(dev_priv, trans) ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
|
||||
|
||||
#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
|
||||
#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
|
||||
@ -1272,7 +1028,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
||||
|
||||
#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
|
||||
|
||||
#define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
|
||||
#define HAS_DMC(dev_priv) (RUNTIME_INFO(dev_priv)->has_dmc)
|
||||
|
||||
#define HAS_HECI_PXP(dev_priv) \
|
||||
(INTEL_INFO(dev_priv)->has_heci_pxp)
|
||||
@ -1302,7 +1058,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
||||
|
||||
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
|
||||
|
||||
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
|
||||
#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
|
||||
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
|
||||
|
||||
/*
|
||||
@ -1313,7 +1069,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
||||
|
||||
#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
|
||||
|
||||
#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
|
||||
#define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
|
||||
|
||||
#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
|
||||
|
||||
@ -1335,9 +1091,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
||||
#define GT_FREQUENCY_MULTIPLIER 50
|
||||
#define GEN9_FREQ_SCALER 3
|
||||
|
||||
#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->display.pipe_mask))
|
||||
#define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
|
||||
|
||||
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)
|
||||
#define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
|
||||
|
||||
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
|
||||
|
||||
@ -1355,7 +1111,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
||||
#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
|
||||
IS_ALDERLAKE_S(dev_priv))
|
||||
|
||||
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
|
||||
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
|
||||
|
||||
#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
|
||||
|
||||
|
@ -1035,7 +1035,7 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
|
||||
|
||||
if (i915_gem_object_has_pages(obj) &&
|
||||
i915_gem_object_is_tiled(obj) &&
|
||||
i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
|
||||
i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) {
|
||||
if (obj->mm.madv == I915_MADV_WILLNEED) {
|
||||
GEM_BUG_ON(!i915_gem_object_has_tiling_quirk(obj));
|
||||
i915_gem_object_clear_tiling_quirk(obj);
|
||||
@ -1091,8 +1091,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
|
||||
|
||||
/* We need to fallback to 4K pages if host doesn't support huge gtt. */
|
||||
if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
|
||||
mkwrite_device_info(dev_priv)->page_sizes =
|
||||
I915_GTT_PAGE_SIZE_4K;
|
||||
RUNTIME_INFO(dev_priv)->page_sizes = I915_GTT_PAGE_SIZE_4K;
|
||||
|
||||
ret = i915_gem_init_userptr(dev_priv);
|
||||
if (ret)
|
||||
|
@ -36,7 +36,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
|
||||
value = to_gt(i915)->ggtt->num_fences;
|
||||
break;
|
||||
case I915_PARAM_HAS_OVERLAY:
|
||||
value = !!i915->overlay;
|
||||
value = !!i915->display.overlay;
|
||||
break;
|
||||
case I915_PARAM_HAS_BSD:
|
||||
value = !!intel_engine_lookup_user(i915,
|
||||
|
@ -646,8 +646,7 @@ static void err_print_capabilities(struct drm_i915_error_state_buf *m,
|
||||
{
|
||||
struct drm_printer p = i915_error_printer(m);
|
||||
|
||||
intel_device_info_print_static(&error->device_info, &p);
|
||||
intel_device_info_print_runtime(&error->runtime_info, &p);
|
||||
intel_device_info_print(&error->device_info, &error->runtime_info, &p);
|
||||
intel_driver_caps_print(&error->driver_caps, &p);
|
||||
}
|
||||
|
||||
|
@ -185,7 +185,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
|
||||
|
||||
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct i915_hotplug *hpd = &dev_priv->hotplug;
|
||||
struct intel_hotplug *hpd = &dev_priv->display.hotplug;
|
||||
|
||||
if (HAS_GMCH(dev_priv)) {
|
||||
if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
|
||||
@ -1272,7 +1272,7 @@ static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
|
||||
u32 enabled_irqs = 0;
|
||||
|
||||
for_each_intel_encoder(&dev_priv->drm, encoder)
|
||||
if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
|
||||
if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
|
||||
enabled_irqs |= hpd[encoder->hpd_pin];
|
||||
|
||||
return enabled_irqs;
|
||||
@ -1304,12 +1304,12 @@ static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
|
||||
|
||||
static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
wake_up_all(&dev_priv->gmbus_wait_queue);
|
||||
wake_up_all(&dev_priv->display.gmbus.wait_queue);
|
||||
}
|
||||
|
||||
static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
wake_up_all(&dev_priv->gmbus_wait_queue);
|
||||
wake_up_all(&dev_priv->display.gmbus.wait_queue);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DEBUG_FS)
|
||||
@ -1637,7 +1637,7 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
|
||||
if (hotplug_trigger) {
|
||||
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
|
||||
hotplug_trigger, hotplug_trigger,
|
||||
dev_priv->hotplug.hpd,
|
||||
dev_priv->display.hotplug.hpd,
|
||||
i9xx_port_hotplug_long_detect);
|
||||
|
||||
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
|
||||
@ -1841,7 +1841,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
|
||||
|
||||
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
|
||||
hotplug_trigger, dig_hotplug_reg,
|
||||
dev_priv->hotplug.pch_hpd,
|
||||
dev_priv->display.hotplug.pch_hpd,
|
||||
pch_port_hotplug_long_detect);
|
||||
|
||||
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
|
||||
@ -1986,7 +1986,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
|
||||
|
||||
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
|
||||
ddi_hotplug_trigger, dig_hotplug_reg,
|
||||
dev_priv->hotplug.pch_hpd,
|
||||
dev_priv->display.hotplug.pch_hpd,
|
||||
icp_ddi_port_hotplug_long_detect);
|
||||
}
|
||||
|
||||
@ -1998,7 +1998,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
|
||||
|
||||
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
|
||||
tc_hotplug_trigger, dig_hotplug_reg,
|
||||
dev_priv->hotplug.pch_hpd,
|
||||
dev_priv->display.hotplug.pch_hpd,
|
||||
icp_tc_port_hotplug_long_detect);
|
||||
}
|
||||
|
||||
@ -2024,7 +2024,7 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
|
||||
|
||||
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
|
||||
hotplug_trigger, dig_hotplug_reg,
|
||||
dev_priv->hotplug.pch_hpd,
|
||||
dev_priv->display.hotplug.pch_hpd,
|
||||
spt_port_hotplug_long_detect);
|
||||
}
|
||||
|
||||
@ -2036,7 +2036,7 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
|
||||
|
||||
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
|
||||
hotplug2_trigger, dig_hotplug_reg,
|
||||
dev_priv->hotplug.pch_hpd,
|
||||
dev_priv->display.hotplug.pch_hpd,
|
||||
spt_port_hotplug2_long_detect);
|
||||
}
|
||||
|
||||
@ -2057,7 +2057,7 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
|
||||
|
||||
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
|
||||
hotplug_trigger, dig_hotplug_reg,
|
||||
dev_priv->hotplug.hpd,
|
||||
dev_priv->display.hotplug.hpd,
|
||||
ilk_port_hotplug_long_detect);
|
||||
|
||||
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
|
||||
@ -2237,7 +2237,7 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
|
||||
|
||||
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
|
||||
hotplug_trigger, dig_hotplug_reg,
|
||||
dev_priv->hotplug.hpd,
|
||||
dev_priv->display.hotplug.hpd,
|
||||
bxt_port_hotplug_long_detect);
|
||||
|
||||
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
|
||||
@ -2257,7 +2257,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
|
||||
|
||||
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
|
||||
trigger_tc, dig_hotplug_reg,
|
||||
dev_priv->hotplug.hpd,
|
||||
dev_priv->display.hotplug.hpd,
|
||||
gen11_port_hotplug_long_detect);
|
||||
}
|
||||
|
||||
@ -2269,7 +2269,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
|
||||
|
||||
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
|
||||
trigger_tbt, dig_hotplug_reg,
|
||||
dev_priv->hotplug.hpd,
|
||||
dev_priv->display.hotplug.hpd,
|
||||
gen11_port_hotplug_long_detect);
|
||||
}
|
||||
|
||||
@ -2653,9 +2653,9 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
|
||||
}
|
||||
|
||||
static u32
|
||||
gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
|
||||
gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl)
|
||||
{
|
||||
void __iomem * const regs = gt->uncore->regs;
|
||||
void __iomem * const regs = i915->uncore.regs;
|
||||
u32 iir;
|
||||
|
||||
if (!(master_ctl & GEN11_GU_MISC_IRQ))
|
||||
@ -2669,10 +2669,10 @@ gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
|
||||
}
|
||||
|
||||
static void
|
||||
gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
|
||||
gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir)
|
||||
{
|
||||
if (iir & GEN11_GU_MISC_GSE)
|
||||
intel_opregion_asle_intr(gt->i915);
|
||||
intel_opregion_asle_intr(i915);
|
||||
}
|
||||
|
||||
static inline u32 gen11_master_intr_disable(void __iomem * const regs)
|
||||
@ -2736,11 +2736,11 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
|
||||
if (master_ctl & GEN11_DISPLAY_IRQ)
|
||||
gen11_display_irq_handler(i915);
|
||||
|
||||
gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
|
||||
gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
|
||||
|
||||
gen11_master_intr_enable(regs);
|
||||
|
||||
gen11_gu_misc_irq_handler(gt, gu_misc_iir);
|
||||
gen11_gu_misc_irq_handler(i915, gu_misc_iir);
|
||||
|
||||
pmu_irq_stats(i915, IRQ_HANDLED);
|
||||
|
||||
@ -2801,11 +2801,11 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
|
||||
if (master_ctl & GEN11_DISPLAY_IRQ)
|
||||
gen11_display_irq_handler(i915);
|
||||
|
||||
gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
|
||||
gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
|
||||
|
||||
dg1_master_intr_enable(regs);
|
||||
|
||||
gen11_gu_misc_irq_handler(gt, gu_misc_iir);
|
||||
gen11_gu_misc_irq_handler(i915, gu_misc_iir);
|
||||
|
||||
pmu_irq_stats(i915, IRQ_HANDLED);
|
||||
|
||||
@ -3313,8 +3313,8 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
u32 hotplug_irqs, enabled_irqs;
|
||||
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
|
||||
|
||||
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
|
||||
|
||||
@ -3383,8 +3383,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
u32 hotplug_irqs, enabled_irqs;
|
||||
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
|
||||
|
||||
if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
|
||||
intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
|
||||
@ -3460,8 +3460,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
|
||||
u32 hotplug_irqs, enabled_irqs;
|
||||
u32 val;
|
||||
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
|
||||
|
||||
val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
|
||||
val &= ~hotplug_irqs;
|
||||
@ -3538,8 +3538,8 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
|
||||
if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
|
||||
intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
|
||||
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
|
||||
|
||||
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
|
||||
|
||||
@ -3578,8 +3578,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
u32 hotplug_irqs, enabled_irqs;
|
||||
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 8)
|
||||
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
|
||||
@ -3636,8 +3636,8 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
u32 hotplug_irqs, enabled_irqs;
|
||||
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
|
||||
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
|
||||
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
|
||||
|
||||
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
|
||||
|
||||
@ -4370,8 +4370,8 @@ HPD_FUNCS(ilk);
|
||||
|
||||
void intel_hpd_irq_setup(struct drm_i915_private *i915)
|
||||
{
|
||||
if (i915->display_irqs_enabled && i915->hotplug_funcs)
|
||||
i915->hotplug_funcs->hpd_irq_setup(i915);
|
||||
if (i915->display_irqs_enabled && i915->display.funcs.hotplug)
|
||||
i915->display.funcs.hotplug->hpd_irq_setup(i915);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -4413,33 +4413,33 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
|
||||
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
||||
dev_priv->display_irqs_enabled = false;
|
||||
|
||||
dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
|
||||
dev_priv->display.hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
|
||||
/* If we have MST support, we want to avoid doing short HPD IRQ storm
|
||||
* detection, as short HPD storms will occur as a natural part of
|
||||
* sideband messaging with MST.
|
||||
* On older platforms however, IRQ storms can occur with both long and
|
||||
* short pulses, as seen on some G4x systems.
|
||||
*/
|
||||
dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
|
||||
dev_priv->display.hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
|
||||
|
||||
if (HAS_GMCH(dev_priv)) {
|
||||
if (I915_HAS_HOTPLUG(dev_priv))
|
||||
dev_priv->hotplug_funcs = &i915_hpd_funcs;
|
||||
dev_priv->display.funcs.hotplug = &i915_hpd_funcs;
|
||||
} else {
|
||||
if (HAS_PCH_DG2(dev_priv))
|
||||
dev_priv->hotplug_funcs = &icp_hpd_funcs;
|
||||
dev_priv->display.funcs.hotplug = &icp_hpd_funcs;
|
||||
else if (HAS_PCH_DG1(dev_priv))
|
||||
dev_priv->hotplug_funcs = &dg1_hpd_funcs;
|
||||
dev_priv->display.funcs.hotplug = &dg1_hpd_funcs;
|
||||
else if (DISPLAY_VER(dev_priv) >= 11)
|
||||
dev_priv->hotplug_funcs = &gen11_hpd_funcs;
|
||||
dev_priv->display.funcs.hotplug = &gen11_hpd_funcs;
|
||||
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
||||
dev_priv->hotplug_funcs = &bxt_hpd_funcs;
|
||||
dev_priv->display.funcs.hotplug = &bxt_hpd_funcs;
|
||||
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
|
||||
dev_priv->hotplug_funcs = &icp_hpd_funcs;
|
||||
dev_priv->display.funcs.hotplug = &icp_hpd_funcs;
|
||||
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
|
||||
dev_priv->hotplug_funcs = &spt_hpd_funcs;
|
||||
dev_priv->display.funcs.hotplug = &spt_hpd_funcs;
|
||||
else
|
||||
dev_priv->hotplug_funcs = &ilk_hpd_funcs;
|
||||
dev_priv->display.funcs.hotplug = &ilk_hpd_funcs;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -30,10 +30,11 @@
|
||||
#include "i915_drv.h"
|
||||
#include "i915_pci.h"
|
||||
#include "i915_reg.h"
|
||||
#include "intel_pci_config.h"
|
||||
|
||||
#define PLATFORM(x) .platform = (x)
|
||||
#define GEN(x) \
|
||||
.graphics.ver = (x), \
|
||||
.__runtime.graphics.ver = (x), \
|
||||
.media.ver = (x), \
|
||||
.display.ver = (x)
|
||||
|
||||
@ -159,16 +160,16 @@
|
||||
/* Keep in gen based order, and chronological order within a gen */
|
||||
|
||||
#define GEN_DEFAULT_PAGE_SIZES \
|
||||
.page_sizes = I915_GTT_PAGE_SIZE_4K
|
||||
.__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K
|
||||
|
||||
#define GEN_DEFAULT_REGIONS \
|
||||
.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
|
||||
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
|
||||
|
||||
#define I830_FEATURES \
|
||||
GEN(2), \
|
||||
.is_mobile = 1, \
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
|
||||
.display.has_overlay = 1, \
|
||||
.display.cursor_needs_physical = 1, \
|
||||
.display.overlay_needs_physical = 1, \
|
||||
@ -177,7 +178,7 @@
|
||||
.has_3d_pipeline = 1, \
|
||||
.hws_needs_physical = 1, \
|
||||
.unfenced_needs_alignment = 1, \
|
||||
.platform_engine_mask = BIT(RCS0), \
|
||||
.__runtime.platform_engine_mask = BIT(RCS0), \
|
||||
.has_snoop = true, \
|
||||
.has_coherent_ggtt = false, \
|
||||
.dma_mask_size = 32, \
|
||||
@ -189,8 +190,8 @@
|
||||
|
||||
#define I845_FEATURES \
|
||||
GEN(2), \
|
||||
.display.pipe_mask = BIT(PIPE_A), \
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A), \
|
||||
.__runtime.pipe_mask = BIT(PIPE_A), \
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
|
||||
.display.has_overlay = 1, \
|
||||
.display.overlay_needs_physical = 1, \
|
||||
.display.has_gmch = 1, \
|
||||
@ -198,7 +199,7 @@
|
||||
.gpu_reset_clobbers_display = true, \
|
||||
.hws_needs_physical = 1, \
|
||||
.unfenced_needs_alignment = 1, \
|
||||
.platform_engine_mask = BIT(RCS0), \
|
||||
.__runtime.platform_engine_mask = BIT(RCS0), \
|
||||
.has_snoop = true, \
|
||||
.has_coherent_ggtt = false, \
|
||||
.dma_mask_size = 32, \
|
||||
@ -221,22 +222,22 @@ static const struct intel_device_info i845g_info = {
|
||||
static const struct intel_device_info i85x_info = {
|
||||
I830_FEATURES,
|
||||
PLATFORM(INTEL_I85X),
|
||||
.display.fbc_mask = BIT(INTEL_FBC_A),
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
|
||||
};
|
||||
|
||||
static const struct intel_device_info i865g_info = {
|
||||
I845_FEATURES,
|
||||
PLATFORM(INTEL_I865G),
|
||||
.display.fbc_mask = BIT(INTEL_FBC_A),
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
|
||||
};
|
||||
|
||||
#define GEN3_FEATURES \
|
||||
GEN(3), \
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
|
||||
.display.has_gmch = 1, \
|
||||
.gpu_reset_clobbers_display = true, \
|
||||
.platform_engine_mask = BIT(RCS0), \
|
||||
.__runtime.platform_engine_mask = BIT(RCS0), \
|
||||
.has_3d_pipeline = 1, \
|
||||
.has_snoop = true, \
|
||||
.has_coherent_ggtt = true, \
|
||||
@ -266,7 +267,7 @@ static const struct intel_device_info i915gm_info = {
|
||||
.display.has_overlay = 1,
|
||||
.display.overlay_needs_physical = 1,
|
||||
.display.supports_tv = 1,
|
||||
.display.fbc_mask = BIT(INTEL_FBC_A),
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
|
||||
.hws_needs_physical = 1,
|
||||
.unfenced_needs_alignment = 1,
|
||||
};
|
||||
@ -291,7 +292,7 @@ static const struct intel_device_info i945gm_info = {
|
||||
.display.has_overlay = 1,
|
||||
.display.overlay_needs_physical = 1,
|
||||
.display.supports_tv = 1,
|
||||
.display.fbc_mask = BIT(INTEL_FBC_A),
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
|
||||
.hws_needs_physical = 1,
|
||||
.unfenced_needs_alignment = 1,
|
||||
};
|
||||
@ -323,12 +324,12 @@ static const struct intel_device_info pnv_m_info = {
|
||||
|
||||
#define GEN4_FEATURES \
|
||||
GEN(4), \
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
|
||||
.display.has_hotplug = 1, \
|
||||
.display.has_gmch = 1, \
|
||||
.gpu_reset_clobbers_display = true, \
|
||||
.platform_engine_mask = BIT(RCS0), \
|
||||
.__runtime.platform_engine_mask = BIT(RCS0), \
|
||||
.has_3d_pipeline = 1, \
|
||||
.has_snoop = true, \
|
||||
.has_coherent_ggtt = true, \
|
||||
@ -351,7 +352,7 @@ static const struct intel_device_info i965gm_info = {
|
||||
GEN4_FEATURES,
|
||||
PLATFORM(INTEL_I965GM),
|
||||
.is_mobile = 1,
|
||||
.display.fbc_mask = BIT(INTEL_FBC_A),
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
|
||||
.display.has_overlay = 1,
|
||||
.display.supports_tv = 1,
|
||||
.hws_needs_physical = 1,
|
||||
@ -361,7 +362,7 @@ static const struct intel_device_info i965gm_info = {
|
||||
static const struct intel_device_info g45_info = {
|
||||
GEN4_FEATURES,
|
||||
PLATFORM(INTEL_G45),
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
|
||||
.gpu_reset_clobbers_display = false,
|
||||
};
|
||||
|
||||
@ -369,18 +370,18 @@ static const struct intel_device_info gm45_info = {
|
||||
GEN4_FEATURES,
|
||||
PLATFORM(INTEL_GM45),
|
||||
.is_mobile = 1,
|
||||
.display.fbc_mask = BIT(INTEL_FBC_A),
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
|
||||
.display.supports_tv = 1,
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
|
||||
.gpu_reset_clobbers_display = false,
|
||||
};
|
||||
|
||||
#define GEN5_FEATURES \
|
||||
GEN(5), \
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
|
||||
.display.has_hotplug = 1, \
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
|
||||
.has_3d_pipeline = 1, \
|
||||
.has_snoop = true, \
|
||||
.has_coherent_ggtt = true, \
|
||||
@ -403,16 +404,16 @@ static const struct intel_device_info ilk_m_info = {
|
||||
PLATFORM(INTEL_IRONLAKE),
|
||||
.is_mobile = 1,
|
||||
.has_rps = true,
|
||||
.display.fbc_mask = BIT(INTEL_FBC_A),
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
|
||||
};
|
||||
|
||||
#define GEN6_FEATURES \
|
||||
GEN(6), \
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
|
||||
.display.has_hotplug = 1, \
|
||||
.display.fbc_mask = BIT(INTEL_FBC_A), \
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
|
||||
.has_3d_pipeline = 1, \
|
||||
.has_coherent_ggtt = true, \
|
||||
.has_llc = 1, \
|
||||
@ -420,8 +421,8 @@ static const struct intel_device_info ilk_m_info = {
|
||||
.has_rc6p = 1, \
|
||||
.has_rps = true, \
|
||||
.dma_mask_size = 40, \
|
||||
.ppgtt_type = INTEL_PPGTT_ALIASING, \
|
||||
.ppgtt_size = 31, \
|
||||
.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
|
||||
.__runtime.ppgtt_size = 31, \
|
||||
I9XX_PIPE_OFFSETS, \
|
||||
I9XX_CURSOR_OFFSETS, \
|
||||
ILK_COLORS, \
|
||||
@ -460,11 +461,11 @@ static const struct intel_device_info snb_m_gt2_info = {
|
||||
|
||||
#define GEN7_FEATURES \
|
||||
GEN(7), \
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
|
||||
.display.has_hotplug = 1, \
|
||||
.display.fbc_mask = BIT(INTEL_FBC_A), \
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
|
||||
.has_3d_pipeline = 1, \
|
||||
.has_coherent_ggtt = true, \
|
||||
.has_llc = 1, \
|
||||
@ -473,8 +474,8 @@ static const struct intel_device_info snb_m_gt2_info = {
|
||||
.has_reset_engine = true, \
|
||||
.has_rps = true, \
|
||||
.dma_mask_size = 40, \
|
||||
.ppgtt_type = INTEL_PPGTT_ALIASING, \
|
||||
.ppgtt_size = 31, \
|
||||
.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
|
||||
.__runtime.ppgtt_size = 31, \
|
||||
IVB_PIPE_OFFSETS, \
|
||||
IVB_CURSOR_OFFSETS, \
|
||||
IVB_COLORS, \
|
||||
@ -516,8 +517,8 @@ static const struct intel_device_info ivb_q_info = {
|
||||
GEN7_FEATURES,
|
||||
PLATFORM(INTEL_IVYBRIDGE),
|
||||
.gt = 2,
|
||||
.display.pipe_mask = 0, /* legal, last one wins */
|
||||
.display.cpu_transcoder_mask = 0,
|
||||
.__runtime.pipe_mask = 0, /* legal, last one wins */
|
||||
.__runtime.cpu_transcoder_mask = 0,
|
||||
.has_l3_dpf = 1,
|
||||
};
|
||||
|
||||
@ -525,8 +526,8 @@ static const struct intel_device_info vlv_info = {
|
||||
PLATFORM(INTEL_VALLEYVIEW),
|
||||
GEN(7),
|
||||
.is_lp = 1,
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
|
||||
.has_runtime_pm = 1,
|
||||
.has_rc6 = 1,
|
||||
.has_reset_engine = true,
|
||||
@ -534,11 +535,11 @@ static const struct intel_device_info vlv_info = {
|
||||
.display.has_gmch = 1,
|
||||
.display.has_hotplug = 1,
|
||||
.dma_mask_size = 40,
|
||||
.ppgtt_type = INTEL_PPGTT_ALIASING,
|
||||
.ppgtt_size = 31,
|
||||
.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
|
||||
.__runtime.ppgtt_size = 31,
|
||||
.has_snoop = true,
|
||||
.has_coherent_ggtt = false,
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
|
||||
.display.mmio_offset = VLV_DISPLAY_BASE,
|
||||
I9XX_PIPE_OFFSETS,
|
||||
I9XX_CURSOR_OFFSETS,
|
||||
@ -549,8 +550,8 @@ static const struct intel_device_info vlv_info = {
|
||||
|
||||
#define G75_FEATURES \
|
||||
GEN7_FEATURES, \
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
|
||||
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
|
||||
.display.has_ddi = 1, \
|
||||
.display.has_fpga_dbg = 1, \
|
||||
@ -584,8 +585,8 @@ static const struct intel_device_info hsw_gt3_info = {
|
||||
GEN(8), \
|
||||
.has_logical_ring_contexts = 1, \
|
||||
.dma_mask_size = 39, \
|
||||
.ppgtt_type = INTEL_PPGTT_FULL, \
|
||||
.ppgtt_size = 48, \
|
||||
.__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
|
||||
.__runtime.ppgtt_size = 48, \
|
||||
.has_64bit_reloc = 1
|
||||
|
||||
#define BDW_PLATFORM \
|
||||
@ -613,18 +614,18 @@ static const struct intel_device_info bdw_rsvd_info = {
|
||||
static const struct intel_device_info bdw_gt3_info = {
|
||||
BDW_PLATFORM,
|
||||
.gt = 3,
|
||||
.platform_engine_mask =
|
||||
.__runtime.platform_engine_mask =
|
||||
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
|
||||
};
|
||||
|
||||
static const struct intel_device_info chv_info = {
|
||||
PLATFORM(INTEL_CHERRYVIEW),
|
||||
GEN(8),
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
|
||||
.display.has_hotplug = 1,
|
||||
.is_lp = 1,
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
|
||||
.has_64bit_reloc = 1,
|
||||
.has_runtime_pm = 1,
|
||||
.has_rc6 = 1,
|
||||
@ -632,8 +633,8 @@ static const struct intel_device_info chv_info = {
|
||||
.has_logical_ring_contexts = 1,
|
||||
.display.has_gmch = 1,
|
||||
.dma_mask_size = 39,
|
||||
.ppgtt_type = INTEL_PPGTT_FULL,
|
||||
.ppgtt_size = 32,
|
||||
.__runtime.ppgtt_type = INTEL_PPGTT_FULL,
|
||||
.__runtime.ppgtt_size = 32,
|
||||
.has_reset_engine = 1,
|
||||
.has_snoop = true,
|
||||
.has_coherent_ggtt = false,
|
||||
@ -646,16 +647,16 @@ static const struct intel_device_info chv_info = {
|
||||
};
|
||||
|
||||
#define GEN9_DEFAULT_PAGE_SIZES \
|
||||
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
|
||||
I915_GTT_PAGE_SIZE_64K
|
||||
.__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
|
||||
I915_GTT_PAGE_SIZE_64K
|
||||
|
||||
#define GEN9_FEATURES \
|
||||
GEN8_FEATURES, \
|
||||
GEN(9), \
|
||||
GEN9_DEFAULT_PAGE_SIZES, \
|
||||
.display.has_dmc = 1, \
|
||||
.__runtime.has_dmc = 1, \
|
||||
.has_gt_uc = 1, \
|
||||
.display.has_hdcp = 1, \
|
||||
.__runtime.has_hdcp = 1, \
|
||||
.display.has_ipc = 1, \
|
||||
.display.has_psr = 1, \
|
||||
.display.has_psr_hw_tracking = 1, \
|
||||
@ -678,7 +679,7 @@ static const struct intel_device_info skl_gt2_info = {
|
||||
|
||||
#define SKL_GT3_PLUS_PLATFORM \
|
||||
SKL_PLATFORM, \
|
||||
.platform_engine_mask = \
|
||||
.__runtime.platform_engine_mask = \
|
||||
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
|
||||
|
||||
|
||||
@ -697,29 +698,29 @@ static const struct intel_device_info skl_gt4_info = {
|
||||
.is_lp = 1, \
|
||||
.display.dbuf.slice_mask = BIT(DBUF_S1), \
|
||||
.display.has_hotplug = 1, \
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
|
||||
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
|
||||
BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
|
||||
.has_3d_pipeline = 1, \
|
||||
.has_64bit_reloc = 1, \
|
||||
.display.has_ddi = 1, \
|
||||
.display.has_fpga_dbg = 1, \
|
||||
.display.fbc_mask = BIT(INTEL_FBC_A), \
|
||||
.display.has_hdcp = 1, \
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
|
||||
.__runtime.has_hdcp = 1, \
|
||||
.display.has_psr = 1, \
|
||||
.display.has_psr_hw_tracking = 1, \
|
||||
.has_runtime_pm = 1, \
|
||||
.display.has_dmc = 1, \
|
||||
.__runtime.has_dmc = 1, \
|
||||
.has_rc6 = 1, \
|
||||
.has_rps = true, \
|
||||
.display.has_dp_mst = 1, \
|
||||
.has_logical_ring_contexts = 1, \
|
||||
.has_gt_uc = 1, \
|
||||
.dma_mask_size = 39, \
|
||||
.ppgtt_type = INTEL_PPGTT_FULL, \
|
||||
.ppgtt_size = 48, \
|
||||
.__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
|
||||
.__runtime.ppgtt_size = 48, \
|
||||
.has_reset_engine = 1, \
|
||||
.has_snoop = true, \
|
||||
.has_coherent_ggtt = false, \
|
||||
@ -761,7 +762,7 @@ static const struct intel_device_info kbl_gt2_info = {
|
||||
static const struct intel_device_info kbl_gt3_info = {
|
||||
KBL_PLATFORM,
|
||||
.gt = 3,
|
||||
.platform_engine_mask =
|
||||
.__runtime.platform_engine_mask =
|
||||
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
|
||||
};
|
||||
|
||||
@ -782,7 +783,7 @@ static const struct intel_device_info cfl_gt2_info = {
|
||||
static const struct intel_device_info cfl_gt3_info = {
|
||||
CFL_PLATFORM,
|
||||
.gt = 3,
|
||||
.platform_engine_mask =
|
||||
.__runtime.platform_engine_mask =
|
||||
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
|
||||
};
|
||||
|
||||
@ -801,15 +802,15 @@ static const struct intel_device_info cml_gt2_info = {
|
||||
};
|
||||
|
||||
#define GEN11_DEFAULT_PAGE_SIZES \
|
||||
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
|
||||
I915_GTT_PAGE_SIZE_64K | \
|
||||
I915_GTT_PAGE_SIZE_2M
|
||||
.__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
|
||||
I915_GTT_PAGE_SIZE_64K | \
|
||||
I915_GTT_PAGE_SIZE_2M
|
||||
|
||||
#define GEN11_FEATURES \
|
||||
GEN9_FEATURES, \
|
||||
GEN11_DEFAULT_PAGE_SIZES, \
|
||||
.display.abox_mask = BIT(0), \
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
|
||||
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
|
||||
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
|
||||
.display.pipe_offsets = { \
|
||||
@ -832,37 +833,37 @@ static const struct intel_device_info cml_gt2_info = {
|
||||
ICL_COLORS, \
|
||||
.display.dbuf.size = 2048, \
|
||||
.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
|
||||
.display.has_dsc = 1, \
|
||||
.__runtime.has_dsc = 1, \
|
||||
.has_coherent_ggtt = false, \
|
||||
.has_logical_ring_elsq = 1
|
||||
|
||||
static const struct intel_device_info icl_info = {
|
||||
GEN11_FEATURES,
|
||||
PLATFORM(INTEL_ICELAKE),
|
||||
.platform_engine_mask =
|
||||
.__runtime.platform_engine_mask =
|
||||
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
|
||||
};
|
||||
|
||||
static const struct intel_device_info ehl_info = {
|
||||
GEN11_FEATURES,
|
||||
PLATFORM(INTEL_ELKHARTLAKE),
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
|
||||
.ppgtt_size = 36,
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
|
||||
.__runtime.ppgtt_size = 36,
|
||||
};
|
||||
|
||||
static const struct intel_device_info jsl_info = {
|
||||
GEN11_FEATURES,
|
||||
PLATFORM(INTEL_JASPERLAKE),
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
|
||||
.ppgtt_size = 36,
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
|
||||
.__runtime.ppgtt_size = 36,
|
||||
};
|
||||
|
||||
#define GEN12_FEATURES \
|
||||
GEN11_FEATURES, \
|
||||
GEN(12), \
|
||||
.display.abox_mask = GENMASK(2, 1), \
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
|
||||
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
|
||||
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
|
||||
.display.pipe_offsets = { \
|
||||
@ -890,7 +891,7 @@ static const struct intel_device_info tgl_info = {
|
||||
GEN12_FEATURES,
|
||||
PLATFORM(INTEL_TIGERLAKE),
|
||||
.display.has_modular_fia = 1,
|
||||
.platform_engine_mask =
|
||||
.__runtime.platform_engine_mask =
|
||||
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
|
||||
};
|
||||
|
||||
@ -898,17 +899,17 @@ static const struct intel_device_info rkl_info = {
|
||||
GEN12_FEATURES,
|
||||
PLATFORM(INTEL_ROCKETLAKE),
|
||||
.display.abox_mask = BIT(0),
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
|
||||
BIT(TRANSCODER_C),
|
||||
.display.has_hti = 1,
|
||||
.display.has_psr_hw_tracking = 0,
|
||||
.platform_engine_mask =
|
||||
.__runtime.platform_engine_mask =
|
||||
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
|
||||
};
|
||||
|
||||
#define DGFX_FEATURES \
|
||||
.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
|
||||
.__runtime.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
|
||||
.has_llc = 0, \
|
||||
.has_pxp = 0, \
|
||||
.has_snoop = 1, \
|
||||
@ -918,24 +919,24 @@ static const struct intel_device_info rkl_info = {
|
||||
static const struct intel_device_info dg1_info = {
|
||||
GEN12_FEATURES,
|
||||
DGFX_FEATURES,
|
||||
.graphics.rel = 10,
|
||||
.__runtime.graphics.rel = 10,
|
||||
PLATFORM(INTEL_DG1),
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
|
||||
.require_force_probe = 1,
|
||||
.platform_engine_mask =
|
||||
.__runtime.platform_engine_mask =
|
||||
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
|
||||
BIT(VCS0) | BIT(VCS2),
|
||||
/* Wa_16011227922 */
|
||||
.ppgtt_size = 47,
|
||||
.__runtime.ppgtt_size = 47,
|
||||
};
|
||||
|
||||
static const struct intel_device_info adl_s_info = {
|
||||
GEN12_FEATURES,
|
||||
PLATFORM(INTEL_ALDERLAKE_S),
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
|
||||
.display.has_hti = 1,
|
||||
.display.has_psr_hw_tracking = 0,
|
||||
.platform_engine_mask =
|
||||
.__runtime.platform_engine_mask =
|
||||
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
|
||||
.dma_mask_size = 39,
|
||||
};
|
||||
@ -951,18 +952,18 @@ static const struct intel_device_info adl_s_info = {
|
||||
.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
|
||||
BIT(DBUF_S4), \
|
||||
.display.has_ddi = 1, \
|
||||
.display.has_dmc = 1, \
|
||||
.__runtime.has_dmc = 1, \
|
||||
.display.has_dp_mst = 1, \
|
||||
.display.has_dsb = 1, \
|
||||
.display.has_dsc = 1, \
|
||||
.display.fbc_mask = BIT(INTEL_FBC_A), \
|
||||
.__runtime.has_dsc = 1, \
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
|
||||
.display.has_fpga_dbg = 1, \
|
||||
.display.has_hdcp = 1, \
|
||||
.__runtime.has_hdcp = 1, \
|
||||
.display.has_hotplug = 1, \
|
||||
.display.has_ipc = 1, \
|
||||
.display.has_psr = 1, \
|
||||
.display.ver = 13, \
|
||||
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
|
||||
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
|
||||
.display.pipe_offsets = { \
|
||||
[TRANSCODER_A] = PIPE_A_OFFSET, \
|
||||
[TRANSCODER_B] = PIPE_B_OFFSET, \
|
||||
@ -985,28 +986,28 @@ static const struct intel_device_info adl_p_info = {
|
||||
GEN12_FEATURES,
|
||||
XE_LPD_FEATURES,
|
||||
PLATFORM(INTEL_ALDERLAKE_P),
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
|
||||
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
|
||||
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
|
||||
.display.has_cdclk_crawl = 1,
|
||||
.display.has_modular_fia = 1,
|
||||
.display.has_psr_hw_tracking = 0,
|
||||
.platform_engine_mask =
|
||||
.__runtime.platform_engine_mask =
|
||||
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
|
||||
.ppgtt_size = 48,
|
||||
.__runtime.ppgtt_size = 48,
|
||||
.dma_mask_size = 39,
|
||||
};
|
||||
|
||||
#undef GEN
|
||||
|
||||
#define XE_HP_PAGE_SIZES \
|
||||
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
|
||||
I915_GTT_PAGE_SIZE_64K | \
|
||||
I915_GTT_PAGE_SIZE_2M
|
||||
.__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
|
||||
I915_GTT_PAGE_SIZE_64K | \
|
||||
I915_GTT_PAGE_SIZE_2M
|
||||
|
||||
#define XE_HP_FEATURES \
|
||||
.graphics.ver = 12, \
|
||||
.graphics.rel = 50, \
|
||||
.__runtime.graphics.ver = 12, \
|
||||
.__runtime.graphics.rel = 50, \
|
||||
XE_HP_PAGE_SIZES, \
|
||||
.dma_mask_size = 46, \
|
||||
.has_3d_pipeline = 1, \
|
||||
@ -1022,8 +1023,8 @@ static const struct intel_device_info adl_p_info = {
|
||||
.has_reset_engine = 1, \
|
||||
.has_rps = 1, \
|
||||
.has_runtime_pm = 1, \
|
||||
.ppgtt_size = 48, \
|
||||
.ppgtt_type = INTEL_PPGTT_FULL
|
||||
.__runtime.ppgtt_size = 48, \
|
||||
.__runtime.ppgtt_type = INTEL_PPGTT_FULL
|
||||
|
||||
#define XE_HPM_FEATURES \
|
||||
.media.ver = 12, \
|
||||
@ -1039,7 +1040,7 @@ static const struct intel_device_info xehpsdv_info = {
|
||||
.has_64k_pages = 1,
|
||||
.needs_compact_pt = 1,
|
||||
.has_media_ratio_mode = 1,
|
||||
.platform_engine_mask =
|
||||
.__runtime.platform_engine_mask =
|
||||
BIT(RCS0) | BIT(BCS0) |
|
||||
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
|
||||
BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
|
||||
@ -1052,7 +1053,7 @@ static const struct intel_device_info xehpsdv_info = {
|
||||
XE_HP_FEATURES, \
|
||||
XE_HPM_FEATURES, \
|
||||
DGFX_FEATURES, \
|
||||
.graphics.rel = 55, \
|
||||
.__runtime.graphics.rel = 55, \
|
||||
.media.rel = 55, \
|
||||
PLATFORM(INTEL_DG2), \
|
||||
.has_4tile = 1, \
|
||||
@ -1061,7 +1062,7 @@ static const struct intel_device_info xehpsdv_info = {
|
||||
.has_heci_pxp = 1, \
|
||||
.needs_compact_pt = 1, \
|
||||
.has_media_ratio_mode = 1, \
|
||||
.platform_engine_mask = \
|
||||
.__runtime.platform_engine_mask = \
|
||||
BIT(RCS0) | BIT(BCS0) | \
|
||||
BIT(VECS0) | BIT(VECS1) | \
|
||||
BIT(VCS0) | BIT(VCS2) | \
|
||||
@ -1070,7 +1071,7 @@ static const struct intel_device_info xehpsdv_info = {
|
||||
static const struct intel_device_info dg2_info = {
|
||||
DG2_FEATURES,
|
||||
XE_LPD_FEATURES,
|
||||
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
|
||||
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
|
||||
BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
|
||||
.require_force_probe = 1,
|
||||
};
|
||||
@ -1096,12 +1097,12 @@ static const struct intel_device_info pvc_info = {
|
||||
XE_HPC_FEATURES,
|
||||
XE_HPM_FEATURES,
|
||||
DGFX_FEATURES,
|
||||
.graphics.rel = 60,
|
||||
.__runtime.graphics.rel = 60,
|
||||
.media.rel = 60,
|
||||
PLATFORM(INTEL_PONTEVECCHIO),
|
||||
.display = { 0 },
|
||||
.has_flat_ccs = 0,
|
||||
.platform_engine_mask =
|
||||
.__runtime.platform_engine_mask =
|
||||
BIT(BCS0) |
|
||||
BIT(VCS0) |
|
||||
BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
|
||||
@ -1111,7 +1112,8 @@ static const struct intel_device_info pvc_info = {
|
||||
#define XE_LPDP_FEATURES \
|
||||
XE_LPD_FEATURES, \
|
||||
.display.ver = 14, \
|
||||
.display.has_cdclk_crawl = 1
|
||||
.display.has_cdclk_crawl = 1, \
|
||||
.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
|
||||
|
||||
__maybe_unused
|
||||
static const struct intel_device_info mtl_info = {
|
||||
@ -1121,15 +1123,15 @@ static const struct intel_device_info mtl_info = {
|
||||
* Real graphics IP version will be obtained from hardware GMD_ID
|
||||
* register. Value provided here is just for sanity checking.
|
||||
*/
|
||||
.graphics.ver = 12,
|
||||
.graphics.rel = 70,
|
||||
.__runtime.graphics.ver = 12,
|
||||
.__runtime.graphics.rel = 70,
|
||||
.media.ver = 13,
|
||||
PLATFORM(INTEL_METEORLAKE),
|
||||
.display.has_modular_fia = 1,
|
||||
.has_flat_ccs = 0,
|
||||
.has_snoop = 1,
|
||||
.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
|
||||
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
|
||||
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
|
||||
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
|
||||
.require_force_probe = 1,
|
||||
};
|
||||
|
||||
@ -1263,6 +1265,27 @@ static bool force_probe(u16 device_id, const char *devices)
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
|
||||
{
|
||||
if (!pci_resource_flags(pdev, bar))
|
||||
return false;
|
||||
|
||||
if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
|
||||
return false;
|
||||
|
||||
if (!pci_resource_len(pdev, bar))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info)
|
||||
{
|
||||
int gttmmaddr_bar = intel_info->__runtime.graphics.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
|
||||
|
||||
return i915_pci_resource_valid(pdev, gttmmaddr_bar);
|
||||
}
|
||||
|
||||
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
struct intel_device_info *intel_info =
|
||||
@ -1288,6 +1311,9 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
if (PCI_FUNC(pdev->devfn))
|
||||
return -ENODEV;
|
||||
|
||||
if (!intel_mmio_bar_valid(pdev, intel_info))
|
||||
return -ENXIO;
|
||||
|
||||
/* Detect if we need to wait for other drivers early on */
|
||||
if (intel_modeset_probe_defer(pdev))
|
||||
return -EPROBE_DEFER;
|
||||
|
@ -6,7 +6,13 @@
|
||||
#ifndef __I915_PCI_H__
|
||||
#define __I915_PCI_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct pci_dev;
|
||||
|
||||
int i915_pci_register_driver(void);
|
||||
void i915_pci_unregister_driver(void);
|
||||
|
||||
bool i915_pci_resource_valid(struct pci_dev *pdev, int bar);
|
||||
|
||||
#endif /* __I915_PCI_H__ */
|
||||
|
@ -1464,7 +1464,7 @@
|
||||
/*
|
||||
* GPIO regs
|
||||
*/
|
||||
#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
|
||||
#define GPIO(gpio) _MMIO(dev_priv->display.gmbus.mmio_base + 0x5010 + \
|
||||
4 * (gpio))
|
||||
|
||||
# define GPIO_CLOCK_DIR_MASK (1 << 0)
|
||||
@ -1482,7 +1482,7 @@
|
||||
# define GPIO_DATA_VAL_IN (1 << 12)
|
||||
# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
|
||||
|
||||
#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
|
||||
#define GMBUS0 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5100) /* clock/port select */
|
||||
#define GMBUS_AKSV_SELECT (1 << 11)
|
||||
#define GMBUS_RATE_100KHZ (0 << 8)
|
||||
#define GMBUS_RATE_50KHZ (1 << 8)
|
||||
@ -1491,7 +1491,7 @@
|
||||
#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
|
||||
#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
|
||||
|
||||
#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
|
||||
#define GMBUS1 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5104) /* command/status */
|
||||
#define GMBUS_SW_CLR_INT (1 << 31)
|
||||
#define GMBUS_SW_RDY (1 << 30)
|
||||
#define GMBUS_ENT (1 << 29) /* enable timeout */
|
||||
@ -1506,7 +1506,7 @@
|
||||
#define GMBUS_SLAVE_ADDR_SHIFT 1
|
||||
#define GMBUS_SLAVE_READ (1 << 0)
|
||||
#define GMBUS_SLAVE_WRITE (0 << 0)
|
||||
#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
|
||||
#define GMBUS2 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5108) /* status */
|
||||
#define GMBUS_INUSE (1 << 15)
|
||||
#define GMBUS_HW_WAIT_PHASE (1 << 14)
|
||||
#define GMBUS_STALL_TIMEOUT (1 << 13)
|
||||
@ -1514,14 +1514,14 @@
|
||||
#define GMBUS_HW_RDY (1 << 11)
|
||||
#define GMBUS_SATOER (1 << 10)
|
||||
#define GMBUS_ACTIVE (1 << 9)
|
||||
#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
|
||||
#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
|
||||
#define GMBUS3 _MMIO(dev_priv->display.gmbus.mmio_base + 0x510c) /* data buffer bytes 3-0 */
|
||||
#define GMBUS4 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5110) /* interrupt mask (Pineview+) */
|
||||
#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
|
||||
#define GMBUS_NAK_EN (1 << 3)
|
||||
#define GMBUS_IDLE_EN (1 << 2)
|
||||
#define GMBUS_HW_WAIT_EN (1 << 1)
|
||||
#define GMBUS_HW_RDY_EN (1 << 0)
|
||||
#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
|
||||
#define GMBUS5 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5120) /* byte index */
|
||||
#define GMBUS_2BYTE_INDEX_EN (1 << 31)
|
||||
|
||||
/*
|
||||
@ -1916,6 +1916,13 @@
|
||||
#define CLKGATE_DIS_PSL(pipe) \
|
||||
_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
|
||||
|
||||
#define _CLKGATE_DIS_PSL_EXT_A 0x4654C
|
||||
#define _CLKGATE_DIS_PSL_EXT_B 0x46550
|
||||
#define PIPEDMC_GATING_DIS REG_BIT(12)
|
||||
|
||||
#define CLKGATE_DIS_PSL_EXT(pipe) \
|
||||
_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
|
||||
|
||||
/*
|
||||
* Display engine regs
|
||||
*/
|
||||
@ -2822,7 +2829,7 @@
|
||||
#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
|
||||
#define PCH_PPS_BASE 0xC7200
|
||||
|
||||
#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
|
||||
#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \
|
||||
PPS_BASE + (reg) + \
|
||||
(pps_idx) * 0x100)
|
||||
|
||||
@ -2918,118 +2925,6 @@
|
||||
|
||||
#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
|
||||
|
||||
#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
|
||||
#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
|
||||
#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
|
||||
_VLV_BLC_PWM_CTL2_B)
|
||||
|
||||
#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
|
||||
#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
|
||||
#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
|
||||
_VLV_BLC_PWM_CTL_B)
|
||||
|
||||
#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
|
||||
#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
|
||||
#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
|
||||
_VLV_BLC_HIST_CTL_B)
|
||||
|
||||
/* Backlight control */
|
||||
#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
|
||||
#define BLM_PWM_ENABLE (1 << 31)
|
||||
#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
|
||||
#define BLM_PIPE_SELECT (1 << 29)
|
||||
#define BLM_PIPE_SELECT_IVB (3 << 29)
|
||||
#define BLM_PIPE_A (0 << 29)
|
||||
#define BLM_PIPE_B (1 << 29)
|
||||
#define BLM_PIPE_C (2 << 29) /* ivb + */
|
||||
#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
|
||||
#define BLM_TRANSCODER_B BLM_PIPE_B
|
||||
#define BLM_TRANSCODER_C BLM_PIPE_C
|
||||
#define BLM_TRANSCODER_EDP (3 << 29)
|
||||
#define BLM_PIPE(pipe) ((pipe) << 29)
|
||||
#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
|
||||
#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
|
||||
#define BLM_PHASE_IN_ENABLE (1 << 25)
|
||||
#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
|
||||
#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
|
||||
#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
|
||||
#define BLM_PHASE_IN_COUNT_SHIFT (8)
|
||||
#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
|
||||
#define BLM_PHASE_IN_INCR_SHIFT (0)
|
||||
#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
|
||||
#define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
|
||||
/*
|
||||
* This is the most significant 15 bits of the number of backlight cycles in a
|
||||
* complete cycle of the modulated backlight control.
|
||||
*
|
||||
* The actual value is this field multiplied by two.
|
||||
*/
|
||||
#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
|
||||
#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
|
||||
#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
|
||||
/*
|
||||
* This is the number of cycles out of the backlight modulation cycle for which
|
||||
* the backlight is on.
|
||||
*
|
||||
* This field must be no greater than the number of cycles in the complete
|
||||
* backlight modulation cycle.
|
||||
*/
|
||||
#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
|
||||
#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
|
||||
#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
|
||||
#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
|
||||
|
||||
#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
|
||||
#define BLM_HISTOGRAM_ENABLE (1 << 31)
|
||||
|
||||
/* New registers for PCH-split platforms. Safe where new bits show up, the
|
||||
* register layout machtes with gen4 BLC_PWM_CTL[12]. */
|
||||
#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
|
||||
#define BLC_PWM_CPU_CTL _MMIO(0x48254)
|
||||
|
||||
#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
|
||||
|
||||
/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
|
||||
* like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
|
||||
#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
|
||||
#define BLM_PCH_PWM_ENABLE (1 << 31)
|
||||
#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
|
||||
#define BLM_PCH_POLARITY (1 << 29)
|
||||
#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
|
||||
|
||||
#define UTIL_PIN_CTL _MMIO(0x48400)
|
||||
#define UTIL_PIN_ENABLE (1 << 31)
|
||||
#define UTIL_PIN_PIPE_MASK (3 << 29)
|
||||
#define UTIL_PIN_PIPE(x) ((x) << 29)
|
||||
#define UTIL_PIN_MODE_MASK (0xf << 24)
|
||||
#define UTIL_PIN_MODE_DATA (0 << 24)
|
||||
#define UTIL_PIN_MODE_PWM (1 << 24)
|
||||
#define UTIL_PIN_MODE_VBLANK (4 << 24)
|
||||
#define UTIL_PIN_MODE_VSYNC (5 << 24)
|
||||
#define UTIL_PIN_MODE_EYE_LEVEL (8 << 24)
|
||||
#define UTIL_PIN_OUTPUT_DATA (1 << 23)
|
||||
#define UTIL_PIN_POLARITY (1 << 22)
|
||||
#define UTIL_PIN_DIRECTION_INPUT (1 << 19)
|
||||
#define UTIL_PIN_INPUT_DATA (1 << 16)
|
||||
|
||||
/* BXT backlight register definition. */
|
||||
#define _BXT_BLC_PWM_CTL1 0xC8250
|
||||
#define BXT_BLC_PWM_ENABLE (1 << 31)
|
||||
#define BXT_BLC_PWM_POLARITY (1 << 29)
|
||||
#define _BXT_BLC_PWM_FREQ1 0xC8254
|
||||
#define _BXT_BLC_PWM_DUTY1 0xC8258
|
||||
|
||||
#define _BXT_BLC_PWM_CTL2 0xC8350
|
||||
#define _BXT_BLC_PWM_FREQ2 0xC8354
|
||||
#define _BXT_BLC_PWM_DUTY2 0xC8358
|
||||
|
||||
#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
|
||||
_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
|
||||
#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
|
||||
_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
|
||||
#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
|
||||
_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
|
||||
|
||||
#define PCH_GTC_CTL _MMIO(0xe7000)
|
||||
#define PCH_GTC_ENABLE (1 << 31)
|
||||
|
||||
@ -5926,7 +5821,8 @@
|
||||
_BW_BUDDY1_PAGE_MASK))
|
||||
|
||||
#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
|
||||
#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
|
||||
#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
|
||||
#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
|
||||
|
||||
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
|
||||
#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
|
||||
@ -6937,265 +6833,6 @@ enum skl_power_gate {
|
||||
#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
|
||||
#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
|
||||
|
||||
/* HDCP Key Registers */
|
||||
#define HDCP_KEY_CONF _MMIO(0x66c00)
|
||||
#define HDCP_AKSV_SEND_TRIGGER BIT(31)
|
||||
#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
|
||||
#define HDCP_KEY_LOAD_TRIGGER BIT(8)
|
||||
#define HDCP_KEY_STATUS _MMIO(0x66c04)
|
||||
#define HDCP_FUSE_IN_PROGRESS BIT(7)
|
||||
#define HDCP_FUSE_ERROR BIT(6)
|
||||
#define HDCP_FUSE_DONE BIT(5)
|
||||
#define HDCP_KEY_LOAD_STATUS BIT(1)
|
||||
#define HDCP_KEY_LOAD_DONE BIT(0)
|
||||
#define HDCP_AKSV_LO _MMIO(0x66c10)
|
||||
#define HDCP_AKSV_HI _MMIO(0x66c14)
|
||||
|
||||
/* HDCP Repeater Registers */
|
||||
#define HDCP_REP_CTL _MMIO(0x66d00)
|
||||
#define HDCP_TRANSA_REP_PRESENT BIT(31)
|
||||
#define HDCP_TRANSB_REP_PRESENT BIT(30)
|
||||
#define HDCP_TRANSC_REP_PRESENT BIT(29)
|
||||
#define HDCP_TRANSD_REP_PRESENT BIT(28)
|
||||
#define HDCP_DDIB_REP_PRESENT BIT(30)
|
||||
#define HDCP_DDIA_REP_PRESENT BIT(29)
|
||||
#define HDCP_DDIC_REP_PRESENT BIT(28)
|
||||
#define HDCP_DDID_REP_PRESENT BIT(27)
|
||||
#define HDCP_DDIF_REP_PRESENT BIT(26)
|
||||
#define HDCP_DDIE_REP_PRESENT BIT(25)
|
||||
#define HDCP_TRANSA_SHA1_M0 (1 << 20)
|
||||
#define HDCP_TRANSB_SHA1_M0 (2 << 20)
|
||||
#define HDCP_TRANSC_SHA1_M0 (3 << 20)
|
||||
#define HDCP_TRANSD_SHA1_M0 (4 << 20)
|
||||
#define HDCP_DDIB_SHA1_M0 (1 << 20)
|
||||
#define HDCP_DDIA_SHA1_M0 (2 << 20)
|
||||
#define HDCP_DDIC_SHA1_M0 (3 << 20)
|
||||
#define HDCP_DDID_SHA1_M0 (4 << 20)
|
||||
#define HDCP_DDIF_SHA1_M0 (5 << 20)
|
||||
#define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
|
||||
#define HDCP_SHA1_BUSY BIT(16)
|
||||
#define HDCP_SHA1_READY BIT(17)
|
||||
#define HDCP_SHA1_COMPLETE BIT(18)
|
||||
#define HDCP_SHA1_V_MATCH BIT(19)
|
||||
#define HDCP_SHA1_TEXT_32 (1 << 1)
|
||||
#define HDCP_SHA1_COMPLETE_HASH (2 << 1)
|
||||
#define HDCP_SHA1_TEXT_24 (4 << 1)
|
||||
#define HDCP_SHA1_TEXT_16 (5 << 1)
|
||||
#define HDCP_SHA1_TEXT_8 (6 << 1)
|
||||
#define HDCP_SHA1_TEXT_0 (7 << 1)
|
||||
#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
|
||||
#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
|
||||
#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
|
||||
#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
|
||||
#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
|
||||
#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
|
||||
#define HDCP_SHA_TEXT _MMIO(0x66d18)
|
||||
|
||||
/* HDCP Auth Registers */
|
||||
#define _PORTA_HDCP_AUTHENC 0x66800
|
||||
#define _PORTB_HDCP_AUTHENC 0x66500
|
||||
#define _PORTC_HDCP_AUTHENC 0x66600
|
||||
#define _PORTD_HDCP_AUTHENC 0x66700
|
||||
#define _PORTE_HDCP_AUTHENC 0x66A00
|
||||
#define _PORTF_HDCP_AUTHENC 0x66900
|
||||
#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
|
||||
_PORTA_HDCP_AUTHENC, \
|
||||
_PORTB_HDCP_AUTHENC, \
|
||||
_PORTC_HDCP_AUTHENC, \
|
||||
_PORTD_HDCP_AUTHENC, \
|
||||
_PORTE_HDCP_AUTHENC, \
|
||||
_PORTF_HDCP_AUTHENC) + (x))
|
||||
#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
|
||||
#define _TRANSA_HDCP_CONF 0x66400
|
||||
#define _TRANSB_HDCP_CONF 0x66500
|
||||
#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
|
||||
_TRANSB_HDCP_CONF)
|
||||
#define HDCP_CONF(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_CONF(trans) : \
|
||||
PORT_HDCP_CONF(port))
|
||||
|
||||
#define HDCP_CONF_CAPTURE_AN BIT(0)
|
||||
#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
|
||||
#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
|
||||
#define _TRANSA_HDCP_ANINIT 0x66404
|
||||
#define _TRANSB_HDCP_ANINIT 0x66504
|
||||
#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP_ANINIT, \
|
||||
_TRANSB_HDCP_ANINIT)
|
||||
#define HDCP_ANINIT(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_ANINIT(trans) : \
|
||||
PORT_HDCP_ANINIT(port))
|
||||
|
||||
#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
|
||||
#define _TRANSA_HDCP_ANLO 0x66408
|
||||
#define _TRANSB_HDCP_ANLO 0x66508
|
||||
#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
|
||||
_TRANSB_HDCP_ANLO)
|
||||
#define HDCP_ANLO(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_ANLO(trans) : \
|
||||
PORT_HDCP_ANLO(port))
|
||||
|
||||
#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
|
||||
#define _TRANSA_HDCP_ANHI 0x6640C
|
||||
#define _TRANSB_HDCP_ANHI 0x6650C
|
||||
#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
|
||||
_TRANSB_HDCP_ANHI)
|
||||
#define HDCP_ANHI(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_ANHI(trans) : \
|
||||
PORT_HDCP_ANHI(port))
|
||||
|
||||
#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
|
||||
#define _TRANSA_HDCP_BKSVLO 0x66410
|
||||
#define _TRANSB_HDCP_BKSVLO 0x66510
|
||||
#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP_BKSVLO, \
|
||||
_TRANSB_HDCP_BKSVLO)
|
||||
#define HDCP_BKSVLO(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_BKSVLO(trans) : \
|
||||
PORT_HDCP_BKSVLO(port))
|
||||
|
||||
#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
|
||||
#define _TRANSA_HDCP_BKSVHI 0x66414
|
||||
#define _TRANSB_HDCP_BKSVHI 0x66514
|
||||
#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP_BKSVHI, \
|
||||
_TRANSB_HDCP_BKSVHI)
|
||||
#define HDCP_BKSVHI(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_BKSVHI(trans) : \
|
||||
PORT_HDCP_BKSVHI(port))
|
||||
|
||||
#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
|
||||
#define _TRANSA_HDCP_RPRIME 0x66418
|
||||
#define _TRANSB_HDCP_RPRIME 0x66518
|
||||
#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP_RPRIME, \
|
||||
_TRANSB_HDCP_RPRIME)
|
||||
#define HDCP_RPRIME(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_RPRIME(trans) : \
|
||||
PORT_HDCP_RPRIME(port))
|
||||
|
||||
#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
|
||||
#define _TRANSA_HDCP_STATUS 0x6641C
|
||||
#define _TRANSB_HDCP_STATUS 0x6651C
|
||||
#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP_STATUS, \
|
||||
_TRANSB_HDCP_STATUS)
|
||||
#define HDCP_STATUS(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP_STATUS(trans) : \
|
||||
PORT_HDCP_STATUS(port))
|
||||
|
||||
#define HDCP_STATUS_STREAM_A_ENC BIT(31)
|
||||
#define HDCP_STATUS_STREAM_B_ENC BIT(30)
|
||||
#define HDCP_STATUS_STREAM_C_ENC BIT(29)
|
||||
#define HDCP_STATUS_STREAM_D_ENC BIT(28)
|
||||
#define HDCP_STATUS_AUTH BIT(21)
|
||||
#define HDCP_STATUS_ENC BIT(20)
|
||||
#define HDCP_STATUS_RI_MATCH BIT(19)
|
||||
#define HDCP_STATUS_R0_READY BIT(18)
|
||||
#define HDCP_STATUS_AN_READY BIT(17)
|
||||
#define HDCP_STATUS_CIPHER BIT(16)
|
||||
#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
|
||||
|
||||
/* HDCP2.2 Registers */
|
||||
#define _PORTA_HDCP2_BASE 0x66800
|
||||
#define _PORTB_HDCP2_BASE 0x66500
|
||||
#define _PORTC_HDCP2_BASE 0x66600
|
||||
#define _PORTD_HDCP2_BASE 0x66700
|
||||
#define _PORTE_HDCP2_BASE 0x66A00
|
||||
#define _PORTF_HDCP2_BASE 0x66900
|
||||
#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
|
||||
_PORTA_HDCP2_BASE, \
|
||||
_PORTB_HDCP2_BASE, \
|
||||
_PORTC_HDCP2_BASE, \
|
||||
_PORTD_HDCP2_BASE, \
|
||||
_PORTE_HDCP2_BASE, \
|
||||
_PORTF_HDCP2_BASE) + (x))
|
||||
|
||||
#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
|
||||
#define _TRANSA_HDCP2_AUTH 0x66498
|
||||
#define _TRANSB_HDCP2_AUTH 0x66598
|
||||
#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
|
||||
_TRANSB_HDCP2_AUTH)
|
||||
#define AUTH_LINK_AUTHENTICATED BIT(31)
|
||||
#define AUTH_LINK_TYPE BIT(30)
|
||||
#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
|
||||
#define AUTH_CLR_KEYS BIT(18)
|
||||
#define HDCP2_AUTH(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP2_AUTH(trans) : \
|
||||
PORT_HDCP2_AUTH(port))
|
||||
|
||||
#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0)
|
||||
#define _TRANSA_HDCP2_CTL 0x664B0
|
||||
#define _TRANSB_HDCP2_CTL 0x665B0
|
||||
#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
|
||||
_TRANSB_HDCP2_CTL)
|
||||
#define CTL_LINK_ENCRYPTION_REQ BIT(31)
|
||||
#define HDCP2_CTL(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP2_CTL(trans) : \
|
||||
PORT_HDCP2_CTL(port))
|
||||
|
||||
#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4)
|
||||
#define _TRANSA_HDCP2_STATUS 0x664B4
|
||||
#define _TRANSB_HDCP2_STATUS 0x665B4
|
||||
#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP2_STATUS, \
|
||||
_TRANSB_HDCP2_STATUS)
|
||||
#define LINK_TYPE_STATUS BIT(22)
|
||||
#define LINK_AUTH_STATUS BIT(21)
|
||||
#define LINK_ENCRYPTION_STATUS BIT(20)
|
||||
#define HDCP2_STATUS(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP2_STATUS(trans) : \
|
||||
PORT_HDCP2_STATUS(port))
|
||||
|
||||
#define _PIPEA_HDCP2_STREAM_STATUS 0x668C0
|
||||
#define _PIPEB_HDCP2_STREAM_STATUS 0x665C0
|
||||
#define _PIPEC_HDCP2_STREAM_STATUS 0x666C0
|
||||
#define _PIPED_HDCP2_STREAM_STATUS 0x667C0
|
||||
#define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \
|
||||
_PIPEA_HDCP2_STREAM_STATUS, \
|
||||
_PIPEB_HDCP2_STREAM_STATUS, \
|
||||
_PIPEC_HDCP2_STREAM_STATUS, \
|
||||
_PIPED_HDCP2_STREAM_STATUS))
|
||||
|
||||
#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0
|
||||
#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0
|
||||
#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP2_STREAM_STATUS, \
|
||||
_TRANSB_HDCP2_STREAM_STATUS)
|
||||
#define STREAM_ENCRYPTION_STATUS BIT(31)
|
||||
#define STREAM_TYPE_STATUS BIT(30)
|
||||
#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP2_STREAM_STATUS(trans) : \
|
||||
PIPE_HDCP2_STREAM_STATUS(pipe))
|
||||
|
||||
#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
|
||||
#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
|
||||
#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
|
||||
_PORTA_HDCP2_AUTH_STREAM, \
|
||||
_PORTB_HDCP2_AUTH_STREAM)
|
||||
#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
|
||||
#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
|
||||
#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
|
||||
_TRANSA_HDCP2_AUTH_STREAM, \
|
||||
_TRANSB_HDCP2_AUTH_STREAM)
|
||||
#define AUTH_STREAM_TYPE BIT(31)
|
||||
#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
|
||||
(GRAPHICS_VER(dev_priv) >= 12 ? \
|
||||
TRANS_HDCP2_AUTH_STREAM(trans) : \
|
||||
PORT_HDCP2_AUTH_STREAM(port))
|
||||
|
||||
/* Per-pipe DDI Function Control */
|
||||
#define _TRANS_DDI_FUNC_CTL_A 0x60400
|
||||
#define _TRANS_DDI_FUNC_CTL_B 0x61400
|
||||
@ -8367,6 +8004,7 @@ enum skl_power_gate {
|
||||
#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
|
||||
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
|
||||
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
|
||||
#define DSC_ALT_ICH_SEL (1 << 20)
|
||||
#define DSC_VBR_ENABLE (1 << 19)
|
||||
#define DSC_422_ENABLE (1 << 18)
|
||||
#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
|
||||
@ -8717,4 +8355,10 @@ enum skl_power_gate {
|
||||
#define GEN12_CULLBIT2 _MMIO(0x7030)
|
||||
#define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC)
|
||||
|
||||
#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
|
||||
#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)
|
||||
#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)
|
||||
#define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
|
||||
#define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
|
||||
|
||||
#endif /* _I915_REG_H_ */
|
||||
|
@ -360,10 +360,6 @@ wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
|
||||
#define KHz(x) (1000 * (x))
|
||||
#define MHz(x) KHz(1000 * (x))
|
||||
|
||||
#define KBps(x) (1000 * (x))
|
||||
#define MBps(x) KBps(1000 * (x))
|
||||
#define GBps(x) ((u64)1000 * MBps((x)))
|
||||
|
||||
void add_taint_for_CI(struct drm_i915_private *i915, unsigned int taint);
|
||||
static inline void __add_taint_for_CI(unsigned int taint)
|
||||
{
|
||||
|
@ -88,14 +88,15 @@ const char *intel_platform_name(enum intel_platform platform)
|
||||
return platform_names[platform];
|
||||
}
|
||||
|
||||
void intel_device_info_print_static(const struct intel_device_info *info,
|
||||
struct drm_printer *p)
|
||||
void intel_device_info_print(const struct intel_device_info *info,
|
||||
const struct intel_runtime_info *runtime,
|
||||
struct drm_printer *p)
|
||||
{
|
||||
if (info->graphics.rel)
|
||||
drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver,
|
||||
info->graphics.rel);
|
||||
if (runtime->graphics.rel)
|
||||
drm_printf(p, "graphics version: %u.%02u\n", runtime->graphics.ver,
|
||||
runtime->graphics.rel);
|
||||
else
|
||||
drm_printf(p, "graphics version: %u\n", info->graphics.ver);
|
||||
drm_printf(p, "graphics version: %u\n", runtime->graphics.ver);
|
||||
|
||||
if (info->media.rel)
|
||||
drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel);
|
||||
@ -108,26 +109,28 @@ void intel_device_info_print_static(const struct intel_device_info *info,
|
||||
drm_printf(p, "display version: %u\n", info->display.ver);
|
||||
|
||||
drm_printf(p, "gt: %d\n", info->gt);
|
||||
drm_printf(p, "memory-regions: %x\n", info->memory_regions);
|
||||
drm_printf(p, "page-sizes: %x\n", info->page_sizes);
|
||||
drm_printf(p, "memory-regions: %x\n", runtime->memory_regions);
|
||||
drm_printf(p, "page-sizes: %x\n", runtime->page_sizes);
|
||||
drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
|
||||
drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
|
||||
drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
|
||||
drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
|
||||
drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);
|
||||
drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
|
||||
|
||||
#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
|
||||
DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
|
||||
#undef PRINT_FLAG
|
||||
|
||||
drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
|
||||
|
||||
#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
|
||||
DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
|
||||
#undef PRINT_FLAG
|
||||
}
|
||||
|
||||
void intel_device_info_print_runtime(const struct intel_runtime_info *info,
|
||||
struct drm_printer *p)
|
||||
{
|
||||
drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
|
||||
drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
|
||||
drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
|
||||
drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
|
||||
|
||||
drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
|
||||
}
|
||||
|
||||
#undef INTEL_VGA_DEVICE
|
||||
@ -364,55 +367,55 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
|
||||
!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
|
||||
drm_info(&dev_priv->drm,
|
||||
"Display fused off, disabling\n");
|
||||
info->display.pipe_mask = 0;
|
||||
info->display.cpu_transcoder_mask = 0;
|
||||
info->display.fbc_mask = 0;
|
||||
runtime->pipe_mask = 0;
|
||||
runtime->cpu_transcoder_mask = 0;
|
||||
runtime->fbc_mask = 0;
|
||||
} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
|
||||
drm_info(&dev_priv->drm, "PipeC fused off\n");
|
||||
info->display.pipe_mask &= ~BIT(PIPE_C);
|
||||
info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
|
||||
runtime->pipe_mask &= ~BIT(PIPE_C);
|
||||
runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
|
||||
}
|
||||
} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
|
||||
u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
|
||||
|
||||
if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
|
||||
info->display.pipe_mask &= ~BIT(PIPE_A);
|
||||
info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
|
||||
info->display.fbc_mask &= ~BIT(INTEL_FBC_A);
|
||||
runtime->pipe_mask &= ~BIT(PIPE_A);
|
||||
runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
|
||||
runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
|
||||
}
|
||||
if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
|
||||
info->display.pipe_mask &= ~BIT(PIPE_B);
|
||||
info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
|
||||
runtime->pipe_mask &= ~BIT(PIPE_B);
|
||||
runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
|
||||
}
|
||||
if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
|
||||
info->display.pipe_mask &= ~BIT(PIPE_C);
|
||||
info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
|
||||
runtime->pipe_mask &= ~BIT(PIPE_C);
|
||||
runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
|
||||
}
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12 &&
|
||||
(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
|
||||
info->display.pipe_mask &= ~BIT(PIPE_D);
|
||||
info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
|
||||
runtime->pipe_mask &= ~BIT(PIPE_D);
|
||||
runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
|
||||
}
|
||||
|
||||
if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
|
||||
info->display.has_hdcp = 0;
|
||||
runtime->has_hdcp = 0;
|
||||
|
||||
if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
|
||||
info->display.fbc_mask = 0;
|
||||
runtime->fbc_mask = 0;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
|
||||
info->display.has_dmc = 0;
|
||||
runtime->has_dmc = 0;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 10 &&
|
||||
(dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
|
||||
info->display.has_dsc = 0;
|
||||
runtime->has_dsc = 0;
|
||||
}
|
||||
|
||||
if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
|
||||
drm_info(&dev_priv->drm,
|
||||
"Disabling ppGTT for VT-d support\n");
|
||||
info->ppgtt_type = INTEL_PPGTT_NONE;
|
||||
runtime->ppgtt_type = INTEL_PPGTT_NONE;
|
||||
}
|
||||
|
||||
runtime->rawclk_freq = intel_read_rawclk(dev_priv);
|
||||
|
@ -164,7 +164,6 @@ enum intel_ppgtt_type {
|
||||
func(has_media_ratio_mode); \
|
||||
func(has_mslice_steering); \
|
||||
func(has_one_eu_per_fuse_bit); \
|
||||
func(has_pooled_eu); \
|
||||
func(has_pxp); \
|
||||
func(has_rc6); \
|
||||
func(has_rc6p); \
|
||||
@ -180,14 +179,11 @@ enum intel_ppgtt_type {
|
||||
/* Keep in alphabetical order */ \
|
||||
func(cursor_needs_physical); \
|
||||
func(has_cdclk_crawl); \
|
||||
func(has_dmc); \
|
||||
func(has_ddi); \
|
||||
func(has_dp_mst); \
|
||||
func(has_dsb); \
|
||||
func(has_dsc); \
|
||||
func(has_fpga_dbg); \
|
||||
func(has_gmch); \
|
||||
func(has_hdcp); \
|
||||
func(has_hotplug); \
|
||||
func(has_hti); \
|
||||
func(has_ipc); \
|
||||
@ -203,23 +199,59 @@ struct ip_version {
|
||||
u8 rel;
|
||||
};
|
||||
|
||||
struct intel_device_info {
|
||||
struct intel_runtime_info {
|
||||
struct ip_version graphics;
|
||||
struct ip_version media;
|
||||
|
||||
/*
|
||||
* Platform mask is used for optimizing or-ed IS_PLATFORM calls into
|
||||
* single runtime conditionals, and also to provide groundwork for
|
||||
* future per platform, or per SKU build optimizations.
|
||||
*
|
||||
* Array can be extended when necessary if the corresponding
|
||||
* BUILD_BUG_ON is hit.
|
||||
*/
|
||||
u32 platform_mask[2];
|
||||
|
||||
u16 device_id;
|
||||
|
||||
intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
|
||||
|
||||
enum intel_platform platform;
|
||||
u32 rawclk_freq;
|
||||
|
||||
unsigned int dma_mask_size; /* available DMA address bits */
|
||||
struct intel_step_info step;
|
||||
|
||||
unsigned int page_sizes; /* page sizes supported by the HW */
|
||||
|
||||
enum intel_ppgtt_type ppgtt_type;
|
||||
unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
|
||||
|
||||
unsigned int page_sizes; /* page sizes supported by the HW */
|
||||
|
||||
u32 memory_regions; /* regions supported by the HW */
|
||||
|
||||
bool has_pooled_eu;
|
||||
|
||||
/* display */
|
||||
struct {
|
||||
u8 pipe_mask;
|
||||
u8 cpu_transcoder_mask;
|
||||
|
||||
u8 num_sprites[I915_MAX_PIPES];
|
||||
u8 num_scalers[I915_MAX_PIPES];
|
||||
|
||||
u8 fbc_mask;
|
||||
|
||||
bool has_hdcp;
|
||||
bool has_dmc;
|
||||
bool has_dsc;
|
||||
};
|
||||
};
|
||||
|
||||
struct intel_device_info {
|
||||
struct ip_version media;
|
||||
|
||||
enum intel_platform platform;
|
||||
|
||||
unsigned int dma_mask_size; /* available DMA address bits */
|
||||
|
||||
u8 gt; /* GT number, 0 if undefined */
|
||||
|
||||
#define DEFINE_FLAG(name) u8 name:1
|
||||
@ -230,9 +262,6 @@ struct intel_device_info {
|
||||
u8 ver;
|
||||
u8 rel;
|
||||
|
||||
u8 pipe_mask;
|
||||
u8 cpu_transcoder_mask;
|
||||
u8 fbc_mask;
|
||||
u8 abox_mask;
|
||||
|
||||
struct {
|
||||
@ -259,27 +288,11 @@ struct intel_device_info {
|
||||
u32 gamma_lut_tests;
|
||||
} color;
|
||||
} display;
|
||||
};
|
||||
|
||||
struct intel_runtime_info {
|
||||
/*
|
||||
* Platform mask is used for optimizing or-ed IS_PLATFORM calls into
|
||||
* into single runtime conditionals, and also to provide groundwork
|
||||
* for future per platform, or per SKU build optimizations.
|
||||
*
|
||||
* Array can be extended when necessary if the corresponding
|
||||
* BUILD_BUG_ON is hit.
|
||||
* Initial runtime info. Do not access outside of i915_driver_create().
|
||||
*/
|
||||
u32 platform_mask[2];
|
||||
|
||||
u16 device_id;
|
||||
|
||||
u8 num_sprites[I915_MAX_PIPES];
|
||||
u8 num_scalers[I915_MAX_PIPES];
|
||||
|
||||
u32 rawclk_freq;
|
||||
|
||||
struct intel_step_info step;
|
||||
const struct intel_runtime_info __runtime;
|
||||
};
|
||||
|
||||
struct intel_driver_caps {
|
||||
@ -292,10 +305,9 @@ const char *intel_platform_name(enum intel_platform platform);
|
||||
void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
|
||||
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
|
||||
|
||||
void intel_device_info_print_static(const struct intel_device_info *info,
|
||||
struct drm_printer *p);
|
||||
void intel_device_info_print_runtime(const struct intel_runtime_info *info,
|
||||
struct drm_printer *p);
|
||||
void intel_device_info_print(const struct intel_device_info *info,
|
||||
const struct intel_runtime_info *runtime,
|
||||
struct drm_printer *p);
|
||||
|
||||
void intel_driver_caps_print(const struct intel_driver_caps *caps,
|
||||
struct drm_printer *p);
|
||||
|
@ -4,6 +4,7 @@
|
||||
*/
|
||||
|
||||
#include "display/intel_audio_regs.h"
|
||||
#include "display/intel_backlight_regs.h"
|
||||
#include "display/intel_dmc_regs.h"
|
||||
#include "display/vlv_dsi_pll_regs.h"
|
||||
#include "gt/intel_gt_regs.h"
|
||||
|
@ -138,6 +138,11 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
|
||||
drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) &&
|
||||
!IS_ALDERLAKE_P(dev_priv));
|
||||
return PCH_ADP;
|
||||
case INTEL_PCH_MTP_DEVICE_ID_TYPE:
|
||||
case INTEL_PCH_MTP2_DEVICE_ID_TYPE:
|
||||
drm_dbg_kms(&dev_priv->drm, "Found Meteor Lake PCH\n");
|
||||
drm_WARN_ON(&dev_priv->drm, !IS_METEORLAKE(dev_priv));
|
||||
return PCH_MTP;
|
||||
default:
|
||||
return PCH_NONE;
|
||||
}
|
||||
@ -166,7 +171,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
|
||||
* make an educated guess as to which PCH is really there.
|
||||
*/
|
||||
|
||||
if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
|
||||
if (IS_METEORLAKE(dev_priv))
|
||||
id = INTEL_PCH_MTP_DEVICE_ID_TYPE;
|
||||
else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
|
||||
id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
|
||||
else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
|
||||
id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
|
||||
|
@ -25,6 +25,7 @@ enum intel_pch {
|
||||
PCH_ICP, /* Ice Lake/Jasper Lake PCH */
|
||||
PCH_TGP, /* Tiger Lake/Mule Creek Canyon PCH */
|
||||
PCH_ADP, /* Alder Lake PCH */
|
||||
PCH_MTP, /* Meteor Lake PCH */
|
||||
|
||||
/* Fake PCHs, functionality handled on the same PCI dev */
|
||||
PCH_DG1 = 1024,
|
||||
@ -57,12 +58,15 @@ enum intel_pch {
|
||||
#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180
|
||||
#define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00
|
||||
#define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x5480
|
||||
#define INTEL_PCH_MTP_DEVICE_ID_TYPE 0x7E00
|
||||
#define INTEL_PCH_MTP2_DEVICE_ID_TYPE 0xAE00
|
||||
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
|
||||
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
|
||||
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
|
||||
|
||||
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
|
||||
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
|
||||
#define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
|
||||
#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
|
||||
#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
|
||||
#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
|
||||
|
@ -6,6 +6,13 @@
|
||||
#ifndef __INTEL_PCI_CONFIG_H__
|
||||
#define __INTEL_PCI_CONFIG_H__
|
||||
|
||||
/* PCI BARs */
|
||||
#define GTTMMADR_BAR 0
|
||||
#define GEN2_GTTMMADR_BAR 1
|
||||
#define GFXMEM_BAR 2
|
||||
#define GTT_APERTURE_BAR GFXMEM_BAR
|
||||
#define GEN12_LMEM_BAR GFXMEM_BAR
|
||||
|
||||
/* BSM in include/drm/i915_drm.h */
|
||||
|
||||
#define MCHBAR_I915 0x44
|
||||
|
@ -468,13 +468,13 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
|
||||
{
|
||||
bool ret;
|
||||
|
||||
mutex_lock(&dev_priv->wm.wm_mutex);
|
||||
mutex_lock(&dev_priv->display.wm.wm_mutex);
|
||||
ret = _intel_set_memory_cxsr(dev_priv, enable);
|
||||
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
||||
dev_priv->wm.vlv.cxsr = enable;
|
||||
dev_priv->display.wm.vlv.cxsr = enable;
|
||||
else if (IS_G4X(dev_priv))
|
||||
dev_priv->wm.g4x.cxsr = enable;
|
||||
mutex_unlock(&dev_priv->wm.wm_mutex);
|
||||
dev_priv->display.wm.g4x.cxsr = enable;
|
||||
mutex_unlock(&dev_priv->display.wm.wm_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -834,7 +834,7 @@ static bool is_enabling(int old, int new, int threshold)
|
||||
|
||||
static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
return dev_priv->wm.max_level + 1;
|
||||
return dev_priv->display.wm.max_level + 1;
|
||||
}
|
||||
|
||||
static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
|
||||
@ -1093,11 +1093,11 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
|
||||
static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
/* all latencies in usec */
|
||||
dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
|
||||
dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
|
||||
dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
|
||||
dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
|
||||
dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
|
||||
dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
|
||||
|
||||
dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
|
||||
dev_priv->display.wm.max_level = G4X_WM_LEVEL_HPLL;
|
||||
}
|
||||
|
||||
static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
|
||||
@ -1150,7 +1150,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
const struct drm_display_mode *pipe_mode =
|
||||
&crtc_state->hw.pipe_mode;
|
||||
unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
|
||||
unsigned int latency = dev_priv->display.wm.pri_latency[level] * 10;
|
||||
unsigned int pixel_rate, htotal, cpp, width, wm;
|
||||
|
||||
if (latency == 0)
|
||||
@ -1324,7 +1324,7 @@ static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
||||
|
||||
if (level > dev_priv->wm.max_level)
|
||||
if (level > dev_priv->display.wm.max_level)
|
||||
return false;
|
||||
|
||||
return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
|
||||
@ -1583,7 +1583,7 @@ static void g4x_merge_wm(struct drm_i915_private *dev_priv,
|
||||
|
||||
static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
|
||||
struct g4x_wm_values *old_wm = &dev_priv->display.wm.g4x;
|
||||
struct g4x_wm_values new_wm = {};
|
||||
|
||||
g4x_merge_wm(dev_priv, &new_wm);
|
||||
@ -1609,10 +1609,10 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
|
||||
const struct intel_crtc_state *crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
|
||||
mutex_lock(&dev_priv->wm.wm_mutex);
|
||||
mutex_lock(&dev_priv->display.wm.wm_mutex);
|
||||
crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
|
||||
g4x_program_watermarks(dev_priv);
|
||||
mutex_unlock(&dev_priv->wm.wm_mutex);
|
||||
mutex_unlock(&dev_priv->display.wm.wm_mutex);
|
||||
}
|
||||
|
||||
static void g4x_optimize_watermarks(struct intel_atomic_state *state,
|
||||
@ -1625,10 +1625,10 @@ static void g4x_optimize_watermarks(struct intel_atomic_state *state,
|
||||
if (!crtc_state->wm.need_postvbl_update)
|
||||
return;
|
||||
|
||||
mutex_lock(&dev_priv->wm.wm_mutex);
|
||||
mutex_lock(&dev_priv->display.wm.wm_mutex);
|
||||
crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
|
||||
g4x_program_watermarks(dev_priv);
|
||||
mutex_unlock(&dev_priv->wm.wm_mutex);
|
||||
mutex_unlock(&dev_priv->display.wm.wm_mutex);
|
||||
}
|
||||
|
||||
/* latency must be in 0.1us units. */
|
||||
@ -1650,15 +1650,15 @@ static unsigned int vlv_wm_method2(unsigned int pixel_rate,
|
||||
static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
/* all latencies in usec */
|
||||
dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
|
||||
dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
|
||||
|
||||
dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
|
||||
dev_priv->display.wm.max_level = VLV_WM_LEVEL_PM2;
|
||||
|
||||
if (IS_CHERRYVIEW(dev_priv)) {
|
||||
dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
|
||||
dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
|
||||
dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
|
||||
dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
|
||||
|
||||
dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
|
||||
dev_priv->display.wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1672,7 +1672,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
|
||||
&crtc_state->hw.pipe_mode;
|
||||
unsigned int pixel_rate, htotal, cpp, width, wm;
|
||||
|
||||
if (dev_priv->wm.pri_latency[level] == 0)
|
||||
if (dev_priv->display.wm.pri_latency[level] == 0)
|
||||
return USHRT_MAX;
|
||||
|
||||
if (!intel_wm_plane_visible(crtc_state, plane_state))
|
||||
@ -1693,7 +1693,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
|
||||
wm = 63;
|
||||
} else {
|
||||
wm = vlv_wm_method2(pixel_rate, htotal, width, cpp,
|
||||
dev_priv->wm.pri_latency[level] * 10);
|
||||
dev_priv->display.wm.pri_latency[level] * 10);
|
||||
}
|
||||
|
||||
return min_t(unsigned int, wm, USHRT_MAX);
|
||||
@ -2158,7 +2158,7 @@ static void vlv_merge_wm(struct drm_i915_private *dev_priv,
|
||||
struct intel_crtc *crtc;
|
||||
int num_active_pipes = 0;
|
||||
|
||||
wm->level = dev_priv->wm.max_level;
|
||||
wm->level = dev_priv->display.wm.max_level;
|
||||
wm->cxsr = true;
|
||||
|
||||
for_each_intel_crtc(&dev_priv->drm, crtc) {
|
||||
@ -2197,7 +2197,7 @@ static void vlv_merge_wm(struct drm_i915_private *dev_priv,
|
||||
|
||||
static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
|
||||
struct vlv_wm_values *old_wm = &dev_priv->display.wm.vlv;
|
||||
struct vlv_wm_values new_wm = {};
|
||||
|
||||
vlv_merge_wm(dev_priv, &new_wm);
|
||||
@ -2235,10 +2235,10 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
|
||||
const struct intel_crtc_state *crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
|
||||
mutex_lock(&dev_priv->wm.wm_mutex);
|
||||
mutex_lock(&dev_priv->display.wm.wm_mutex);
|
||||
crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
|
||||
vlv_program_watermarks(dev_priv);
|
||||
mutex_unlock(&dev_priv->wm.wm_mutex);
|
||||
mutex_unlock(&dev_priv->display.wm.wm_mutex);
|
||||
}
|
||||
|
||||
static void vlv_optimize_watermarks(struct intel_atomic_state *state,
|
||||
@ -2251,10 +2251,10 @@ static void vlv_optimize_watermarks(struct intel_atomic_state *state,
|
||||
if (!crtc_state->wm.need_postvbl_update)
|
||||
return;
|
||||
|
||||
mutex_lock(&dev_priv->wm.wm_mutex);
|
||||
mutex_lock(&dev_priv->display.wm.wm_mutex);
|
||||
crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
|
||||
vlv_program_watermarks(dev_priv);
|
||||
mutex_unlock(&dev_priv->wm.wm_mutex);
|
||||
mutex_unlock(&dev_priv->display.wm.wm_mutex);
|
||||
}
|
||||
|
||||
static void i965_update_wm(struct drm_i915_private *dev_priv)
|
||||
@ -2835,9 +2835,9 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
|
||||
const struct intel_plane_state *curstate,
|
||||
struct intel_wm_level *result)
|
||||
{
|
||||
u16 pri_latency = dev_priv->wm.pri_latency[level];
|
||||
u16 spr_latency = dev_priv->wm.spr_latency[level];
|
||||
u16 cur_latency = dev_priv->wm.cur_latency[level];
|
||||
u16 pri_latency = dev_priv->display.wm.pri_latency[level];
|
||||
u16 spr_latency = dev_priv->display.wm.spr_latency[level];
|
||||
u16 cur_latency = dev_priv->display.wm.cur_latency[level];
|
||||
|
||||
/* WM1+ latency values stored in 0.5us units */
|
||||
if (level > 0) {
|
||||
@ -2861,16 +2861,75 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
|
||||
result->enable = true;
|
||||
}
|
||||
|
||||
static void
|
||||
adjust_wm_latency(struct drm_i915_private *i915,
|
||||
u16 wm[], int max_level, int read_latency)
|
||||
{
|
||||
bool wm_lv_0_adjust_needed = i915->dram_info.wm_lv_0_adjust_needed;
|
||||
int i, level;
|
||||
|
||||
/*
|
||||
* If a level n (n > 1) has a 0us latency, all levels m (m >= n)
|
||||
* need to be disabled. We make sure to sanitize the values out
|
||||
* of the punit to satisfy this requirement.
|
||||
*/
|
||||
for (level = 1; level <= max_level; level++) {
|
||||
if (wm[level] == 0) {
|
||||
for (i = level + 1; i <= max_level; i++)
|
||||
wm[i] = 0;
|
||||
|
||||
max_level = level - 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* WaWmMemoryReadLatency
|
||||
*
|
||||
* punit doesn't take into account the read latency so we need
|
||||
* to add proper adjustement to each valid level we retrieve
|
||||
* from the punit when level 0 response data is 0us.
|
||||
*/
|
||||
if (wm[0] == 0) {
|
||||
for (level = 0; level <= max_level; level++)
|
||||
wm[level] += read_latency;
|
||||
}
|
||||
|
||||
/*
|
||||
* WA Level-0 adjustment for 16GB DIMMs: SKL+
|
||||
* If we could not get dimm info enable this WA to prevent from
|
||||
* any underrun. If not able to get Dimm info assume 16GB dimm
|
||||
* to avoid any underrun.
|
||||
*/
|
||||
if (wm_lv_0_adjust_needed)
|
||||
wm[0] += 1;
|
||||
}
|
||||
|
||||
static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
|
||||
u16 wm[])
|
||||
{
|
||||
struct intel_uncore *uncore = &dev_priv->uncore;
|
||||
int max_level = ilk_wm_max_level(dev_priv);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 9) {
|
||||
if (DISPLAY_VER(dev_priv) >= 14) {
|
||||
u32 val;
|
||||
int ret, i;
|
||||
int level, max_level = ilk_wm_max_level(dev_priv);
|
||||
|
||||
val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1);
|
||||
wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
|
||||
wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
|
||||
val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3);
|
||||
wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
|
||||
wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
|
||||
val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5);
|
||||
wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
|
||||
wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
|
||||
|
||||
adjust_wm_latency(dev_priv, wm, max_level, 6);
|
||||
} else if (DISPLAY_VER(dev_priv) >= 9) {
|
||||
int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
|
||||
int mult = IS_DG2(dev_priv) ? 2 : 1;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
/* read the first set of memory latencies[0:3] */
|
||||
val = 0; /* data0 to be programmed to 0 for first set */
|
||||
@ -2909,44 +2968,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
|
||||
wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
|
||||
GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
|
||||
|
||||
/*
|
||||
* If a level n (n > 1) has a 0us latency, all levels m (m >= n)
|
||||
* need to be disabled. We make sure to sanitize the values out
|
||||
* of the punit to satisfy this requirement.
|
||||
*/
|
||||
for (level = 1; level <= max_level; level++) {
|
||||
if (wm[level] == 0) {
|
||||
for (i = level + 1; i <= max_level; i++)
|
||||
wm[i] = 0;
|
||||
|
||||
max_level = level - 1;
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* WaWmMemoryReadLatency
|
||||
*
|
||||
* punit doesn't take into account the read latency so we need
|
||||
* to add proper adjustement to each valid level we retrieve
|
||||
* from the punit when level 0 response data is 0us.
|
||||
*/
|
||||
if (wm[0] == 0) {
|
||||
u8 adjust = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
|
||||
|
||||
for (level = 0; level <= max_level; level++)
|
||||
wm[level] += adjust;
|
||||
}
|
||||
|
||||
/*
|
||||
* WA Level-0 adjustment for 16GB DIMMs: SKL+
|
||||
* If we could not get dimm info enable this WA to prevent from
|
||||
* any underrun. If not able to get Dimm info assume 16GB dimm
|
||||
* to avoid any underrun.
|
||||
*/
|
||||
if (dev_priv->dram_info.wm_lv_0_adjust_needed)
|
||||
wm[0] += 1;
|
||||
adjust_wm_latency(dev_priv, wm, max_level, read_latency);
|
||||
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
|
||||
u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
|
||||
|
||||
@ -3061,18 +3083,18 @@ static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
|
||||
* The BIOS provided WM memory latency values are often
|
||||
* inadequate for high resolution displays. Adjust them.
|
||||
*/
|
||||
changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12);
|
||||
changed |= ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12);
|
||||
changed |= ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
|
||||
changed = ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.pri_latency, 12);
|
||||
changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.spr_latency, 12);
|
||||
changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.cur_latency, 12);
|
||||
|
||||
if (!changed)
|
||||
return;
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"WM latency values increased to avoid potential underruns\n");
|
||||
intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
|
||||
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
|
||||
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
|
||||
intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
|
||||
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
|
||||
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
|
||||
}
|
||||
|
||||
static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
|
||||
@ -3088,37 +3110,37 @@ static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
|
||||
* interrupts only. To play it safe we disable LP3
|
||||
* watermarks entirely.
|
||||
*/
|
||||
if (dev_priv->wm.pri_latency[3] == 0 &&
|
||||
dev_priv->wm.spr_latency[3] == 0 &&
|
||||
dev_priv->wm.cur_latency[3] == 0)
|
||||
if (dev_priv->display.wm.pri_latency[3] == 0 &&
|
||||
dev_priv->display.wm.spr_latency[3] == 0 &&
|
||||
dev_priv->display.wm.cur_latency[3] == 0)
|
||||
return;
|
||||
|
||||
dev_priv->wm.pri_latency[3] = 0;
|
||||
dev_priv->wm.spr_latency[3] = 0;
|
||||
dev_priv->wm.cur_latency[3] = 0;
|
||||
dev_priv->display.wm.pri_latency[3] = 0;
|
||||
dev_priv->display.wm.spr_latency[3] = 0;
|
||||
dev_priv->display.wm.cur_latency[3] = 0;
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"LP3 watermarks disabled due to potential for lost interrupts\n");
|
||||
intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
|
||||
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
|
||||
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
|
||||
intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
|
||||
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
|
||||
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
|
||||
}
|
||||
|
||||
static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
|
||||
intel_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
|
||||
|
||||
memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
|
||||
sizeof(dev_priv->wm.pri_latency));
|
||||
memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
|
||||
sizeof(dev_priv->wm.pri_latency));
|
||||
memcpy(dev_priv->display.wm.spr_latency, dev_priv->display.wm.pri_latency,
|
||||
sizeof(dev_priv->display.wm.pri_latency));
|
||||
memcpy(dev_priv->display.wm.cur_latency, dev_priv->display.wm.pri_latency,
|
||||
sizeof(dev_priv->display.wm.pri_latency));
|
||||
|
||||
intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
|
||||
intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
|
||||
intel_fixup_spr_wm_latency(dev_priv, dev_priv->display.wm.spr_latency);
|
||||
intel_fixup_cur_wm_latency(dev_priv, dev_priv->display.wm.cur_latency);
|
||||
|
||||
intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
|
||||
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
|
||||
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
|
||||
intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
|
||||
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
|
||||
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) == 6) {
|
||||
snb_wm_latency_quirk(dev_priv);
|
||||
@ -3128,8 +3150,8 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
|
||||
|
||||
static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
|
||||
intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
|
||||
intel_read_wm_latency(dev_priv, dev_priv->display.wm.skl_latency);
|
||||
intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->display.wm.skl_latency);
|
||||
}
|
||||
|
||||
static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
|
||||
@ -3386,7 +3408,7 @@ static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
|
||||
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
||||
return 2 * level;
|
||||
else
|
||||
return dev_priv->wm.pri_latency[level];
|
||||
return dev_priv->display.wm.pri_latency[level];
|
||||
}
|
||||
|
||||
static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
|
||||
@ -3538,7 +3560,7 @@ static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
|
||||
static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
|
||||
unsigned int dirty)
|
||||
{
|
||||
struct ilk_wm_values *previous = &dev_priv->wm.hw;
|
||||
struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
|
||||
bool changed = false;
|
||||
|
||||
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM_LP_ENABLE) {
|
||||
@ -3572,7 +3594,7 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
|
||||
static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
|
||||
struct ilk_wm_values *results)
|
||||
{
|
||||
struct ilk_wm_values *previous = &dev_priv->wm.hw;
|
||||
struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
|
||||
unsigned int dirty;
|
||||
u32 val;
|
||||
|
||||
@ -3634,7 +3656,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
|
||||
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
|
||||
intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, results->wm_lp[2]);
|
||||
|
||||
dev_priv->wm.hw = *results;
|
||||
dev_priv->display.wm.hw = *results;
|
||||
}
|
||||
|
||||
bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
|
||||
@ -3669,7 +3691,7 @@ static bool
|
||||
intel_has_sagv(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
return DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv) &&
|
||||
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
|
||||
dev_priv->display.sagv.status != I915_SAGV_NOT_CONTROLLED;
|
||||
}
|
||||
|
||||
static u32
|
||||
@ -3700,7 +3722,7 @@ intel_sagv_block_time(struct drm_i915_private *dev_priv)
|
||||
static void intel_sagv_init(struct drm_i915_private *i915)
|
||||
{
|
||||
if (!intel_has_sagv(i915))
|
||||
i915->sagv_status = I915_SAGV_NOT_CONTROLLED;
|
||||
i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
|
||||
|
||||
/*
|
||||
* Probe to see if we have working SAGV control.
|
||||
@ -3709,21 +3731,21 @@ static void intel_sagv_init(struct drm_i915_private *i915)
|
||||
if (DISPLAY_VER(i915) < 11)
|
||||
skl_sagv_disable(i915);
|
||||
|
||||
drm_WARN_ON(&i915->drm, i915->sagv_status == I915_SAGV_UNKNOWN);
|
||||
drm_WARN_ON(&i915->drm, i915->display.sagv.status == I915_SAGV_UNKNOWN);
|
||||
|
||||
i915->sagv_block_time_us = intel_sagv_block_time(i915);
|
||||
i915->display.sagv.block_time_us = intel_sagv_block_time(i915);
|
||||
|
||||
drm_dbg_kms(&i915->drm, "SAGV supported: %s, original SAGV block time: %u us\n",
|
||||
str_yes_no(intel_has_sagv(i915)), i915->sagv_block_time_us);
|
||||
str_yes_no(intel_has_sagv(i915)), i915->display.sagv.block_time_us);
|
||||
|
||||
/* avoid overflow when adding with wm0 latency/etc. */
|
||||
if (drm_WARN(&i915->drm, i915->sagv_block_time_us > U16_MAX,
|
||||
if (drm_WARN(&i915->drm, i915->display.sagv.block_time_us > U16_MAX,
|
||||
"Excessive SAGV block time %u, ignoring\n",
|
||||
i915->sagv_block_time_us))
|
||||
i915->sagv_block_time_us = 0;
|
||||
i915->display.sagv.block_time_us))
|
||||
i915->display.sagv.block_time_us = 0;
|
||||
|
||||
if (!intel_has_sagv(i915))
|
||||
i915->sagv_block_time_us = 0;
|
||||
i915->display.sagv.block_time_us = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -3744,7 +3766,7 @@ static void skl_sagv_enable(struct drm_i915_private *dev_priv)
|
||||
if (!intel_has_sagv(dev_priv))
|
||||
return;
|
||||
|
||||
if (dev_priv->sagv_status == I915_SAGV_ENABLED)
|
||||
if (dev_priv->display.sagv.status == I915_SAGV_ENABLED)
|
||||
return;
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
|
||||
@ -3759,14 +3781,14 @@ static void skl_sagv_enable(struct drm_i915_private *dev_priv)
|
||||
*/
|
||||
if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
|
||||
drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
|
||||
dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
|
||||
dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
|
||||
return;
|
||||
} else if (ret < 0) {
|
||||
drm_err(&dev_priv->drm, "Failed to enable SAGV\n");
|
||||
return;
|
||||
}
|
||||
|
||||
dev_priv->sagv_status = I915_SAGV_ENABLED;
|
||||
dev_priv->display.sagv.status = I915_SAGV_ENABLED;
|
||||
}
|
||||
|
||||
static void skl_sagv_disable(struct drm_i915_private *dev_priv)
|
||||
@ -3776,7 +3798,7 @@ static void skl_sagv_disable(struct drm_i915_private *dev_priv)
|
||||
if (!intel_has_sagv(dev_priv))
|
||||
return;
|
||||
|
||||
if (dev_priv->sagv_status == I915_SAGV_DISABLED)
|
||||
if (dev_priv->display.sagv.status == I915_SAGV_DISABLED)
|
||||
return;
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
|
||||
@ -3791,14 +3813,14 @@ static void skl_sagv_disable(struct drm_i915_private *dev_priv)
|
||||
*/
|
||||
if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
|
||||
drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
|
||||
dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
|
||||
dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
|
||||
return;
|
||||
} else if (ret < 0) {
|
||||
drm_err(&dev_priv->drm, "Failed to disable SAGV (%d)\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
dev_priv->sagv_status = I915_SAGV_DISABLED;
|
||||
dev_priv->display.sagv.status = I915_SAGV_DISABLED;
|
||||
}
|
||||
|
||||
static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)
|
||||
@ -4321,7 +4343,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
|
||||
drm_WARN_ON(&dev_priv->drm, ret);
|
||||
|
||||
for (level = 0; level <= max_level; level++) {
|
||||
unsigned int latency = dev_priv->wm.skl_latency[level];
|
||||
unsigned int latency = dev_priv->display.wm.skl_latency[level];
|
||||
|
||||
skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
|
||||
if (wm.min_ddb_alloc == U16_MAX)
|
||||
@ -4905,7 +4927,7 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool
|
||||
|
||||
if (IS_DG2(dev_priv))
|
||||
return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus);
|
||||
else if (IS_ALDERLAKE_P(dev_priv))
|
||||
else if (DISPLAY_VER(dev_priv) >= 13)
|
||||
return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus);
|
||||
else if (DISPLAY_VER(dev_priv) == 12)
|
||||
return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus);
|
||||
@ -5560,8 +5582,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
|
||||
result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
|
||||
result->enable = true;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) < 12 && dev_priv->sagv_block_time_us)
|
||||
result->can_sagv = latency >= dev_priv->sagv_block_time_us;
|
||||
if (DISPLAY_VER(dev_priv) < 12 && dev_priv->display.sagv.block_time_us)
|
||||
result->can_sagv = latency >= dev_priv->display.sagv.block_time_us;
|
||||
}
|
||||
|
||||
static void
|
||||
@ -5576,7 +5598,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
|
||||
|
||||
for (level = 0; level <= max_level; level++) {
|
||||
struct skl_wm_level *result = &levels[level];
|
||||
unsigned int latency = dev_priv->wm.skl_latency[level];
|
||||
unsigned int latency = dev_priv->display.wm.skl_latency[level];
|
||||
|
||||
skl_compute_plane_wm(crtc_state, plane, level, latency,
|
||||
wm_params, result_prev, result);
|
||||
@ -5595,8 +5617,8 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
|
||||
struct skl_wm_level *levels = plane_wm->wm;
|
||||
unsigned int latency = 0;
|
||||
|
||||
if (dev_priv->sagv_block_time_us)
|
||||
latency = dev_priv->sagv_block_time_us + dev_priv->wm.skl_latency[0];
|
||||
if (dev_priv->display.sagv.block_time_us)
|
||||
latency = dev_priv->display.sagv.block_time_us + dev_priv->display.wm.skl_latency[0];
|
||||
|
||||
skl_compute_plane_wm(crtc_state, plane, 0, latency,
|
||||
wm_params, &levels[0],
|
||||
@ -6458,10 +6480,10 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
|
||||
const struct intel_crtc_state *crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
|
||||
mutex_lock(&dev_priv->wm.wm_mutex);
|
||||
mutex_lock(&dev_priv->display.wm.wm_mutex);
|
||||
crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
|
||||
ilk_program_watermarks(dev_priv);
|
||||
mutex_unlock(&dev_priv->wm.wm_mutex);
|
||||
mutex_unlock(&dev_priv->display.wm.wm_mutex);
|
||||
}
|
||||
|
||||
static void ilk_optimize_watermarks(struct intel_atomic_state *state,
|
||||
@ -6474,10 +6496,10 @@ static void ilk_optimize_watermarks(struct intel_atomic_state *state,
|
||||
if (!crtc_state->wm.need_postvbl_update)
|
||||
return;
|
||||
|
||||
mutex_lock(&dev_priv->wm.wm_mutex);
|
||||
mutex_lock(&dev_priv->display.wm.wm_mutex);
|
||||
crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
|
||||
ilk_program_watermarks(dev_priv);
|
||||
mutex_unlock(&dev_priv->wm.wm_mutex);
|
||||
mutex_unlock(&dev_priv->display.wm.wm_mutex);
|
||||
}
|
||||
|
||||
static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
|
||||
@ -6560,7 +6582,10 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
|
||||
enum plane_id plane_id;
|
||||
u8 slices;
|
||||
|
||||
skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
|
||||
memset(&crtc_state->wm.skl.optimal, 0,
|
||||
sizeof(crtc_state->wm.skl.optimal));
|
||||
if (crtc_state->hw.active)
|
||||
skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
|
||||
crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;
|
||||
|
||||
memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));
|
||||
@ -6571,6 +6596,9 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
|
||||
struct skl_ddb_entry *ddb_y =
|
||||
&crtc_state->wm.skl.plane_ddb_y[plane_id];
|
||||
|
||||
if (!crtc_state->hw.active)
|
||||
continue;
|
||||
|
||||
skl_ddb_get_hw_plane_state(dev_priv, crtc->pipe,
|
||||
plane_id, ddb, ddb_y);
|
||||
|
||||
@ -6677,7 +6705,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
|
||||
{
|
||||
struct drm_device *dev = crtc->base.dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct ilk_wm_values *hw = &dev_priv->wm.hw;
|
||||
struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
|
||||
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
|
||||
struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
|
||||
enum pipe pipe = crtc->pipe;
|
||||
@ -6825,7 +6853,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
|
||||
|
||||
void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct g4x_wm_values *wm = &dev_priv->wm.g4x;
|
||||
struct g4x_wm_values *wm = &dev_priv->display.wm.g4x;
|
||||
struct intel_crtc *crtc;
|
||||
|
||||
g4x_read_wm_values(dev_priv, wm);
|
||||
@ -6919,7 +6947,7 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
|
||||
struct intel_plane *plane;
|
||||
struct intel_crtc *crtc;
|
||||
|
||||
mutex_lock(&dev_priv->wm.wm_mutex);
|
||||
mutex_lock(&dev_priv->display.wm.wm_mutex);
|
||||
|
||||
for_each_intel_plane(&dev_priv->drm, plane) {
|
||||
struct intel_crtc *crtc =
|
||||
@ -6967,12 +6995,12 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
|
||||
|
||||
g4x_program_watermarks(dev_priv);
|
||||
|
||||
mutex_unlock(&dev_priv->wm.wm_mutex);
|
||||
mutex_unlock(&dev_priv->display.wm.wm_mutex);
|
||||
}
|
||||
|
||||
void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct vlv_wm_values *wm = &dev_priv->wm.vlv;
|
||||
struct vlv_wm_values *wm = &dev_priv->display.wm.vlv;
|
||||
struct intel_crtc *crtc;
|
||||
u32 val;
|
||||
|
||||
@ -7006,7 +7034,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"Punit not acking DDR DVFS request, "
|
||||
"assuming DDR DVFS is disabled\n");
|
||||
dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
|
||||
dev_priv->display.wm.max_level = VLV_WM_LEVEL_PM5;
|
||||
} else {
|
||||
val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
|
||||
if ((val & FORCE_DDR_HIGH_FREQ) == 0)
|
||||
@ -7075,7 +7103,7 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
|
||||
struct intel_plane *plane;
|
||||
struct intel_crtc *crtc;
|
||||
|
||||
mutex_lock(&dev_priv->wm.wm_mutex);
|
||||
mutex_lock(&dev_priv->display.wm.wm_mutex);
|
||||
|
||||
for_each_intel_plane(&dev_priv->drm, plane) {
|
||||
struct intel_crtc *crtc =
|
||||
@ -7116,7 +7144,7 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
|
||||
|
||||
vlv_program_watermarks(dev_priv);
|
||||
|
||||
mutex_unlock(&dev_priv->wm.wm_mutex);
|
||||
mutex_unlock(&dev_priv->display.wm.wm_mutex);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -7137,7 +7165,7 @@ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
|
||||
|
||||
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct ilk_wm_values *hw = &dev_priv->wm.hw;
|
||||
struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
|
||||
struct intel_crtc *crtc;
|
||||
|
||||
ilk_init_lp_watermarks(dev_priv);
|
||||
@ -8168,18 +8196,18 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
|
||||
}
|
||||
}
|
||||
|
||||
static const struct drm_i915_wm_disp_funcs skl_wm_funcs = {
|
||||
static const struct intel_wm_funcs skl_wm_funcs = {
|
||||
.compute_global_watermarks = skl_compute_wm,
|
||||
};
|
||||
|
||||
static const struct drm_i915_wm_disp_funcs ilk_wm_funcs = {
|
||||
static const struct intel_wm_funcs ilk_wm_funcs = {
|
||||
.compute_pipe_wm = ilk_compute_pipe_wm,
|
||||
.compute_intermediate_wm = ilk_compute_intermediate_wm,
|
||||
.initial_watermarks = ilk_initial_watermarks,
|
||||
.optimize_watermarks = ilk_optimize_watermarks,
|
||||
};
|
||||
|
||||
static const struct drm_i915_wm_disp_funcs vlv_wm_funcs = {
|
||||
static const struct intel_wm_funcs vlv_wm_funcs = {
|
||||
.compute_pipe_wm = vlv_compute_pipe_wm,
|
||||
.compute_intermediate_wm = vlv_compute_intermediate_wm,
|
||||
.initial_watermarks = vlv_initial_watermarks,
|
||||
@ -8187,30 +8215,30 @@ static const struct drm_i915_wm_disp_funcs vlv_wm_funcs = {
|
||||
.atomic_update_watermarks = vlv_atomic_update_fifo,
|
||||
};
|
||||
|
||||
static const struct drm_i915_wm_disp_funcs g4x_wm_funcs = {
|
||||
static const struct intel_wm_funcs g4x_wm_funcs = {
|
||||
.compute_pipe_wm = g4x_compute_pipe_wm,
|
||||
.compute_intermediate_wm = g4x_compute_intermediate_wm,
|
||||
.initial_watermarks = g4x_initial_watermarks,
|
||||
.optimize_watermarks = g4x_optimize_watermarks,
|
||||
};
|
||||
|
||||
static const struct drm_i915_wm_disp_funcs pnv_wm_funcs = {
|
||||
static const struct intel_wm_funcs pnv_wm_funcs = {
|
||||
.update_wm = pnv_update_wm,
|
||||
};
|
||||
|
||||
static const struct drm_i915_wm_disp_funcs i965_wm_funcs = {
|
||||
static const struct intel_wm_funcs i965_wm_funcs = {
|
||||
.update_wm = i965_update_wm,
|
||||
};
|
||||
|
||||
static const struct drm_i915_wm_disp_funcs i9xx_wm_funcs = {
|
||||
static const struct intel_wm_funcs i9xx_wm_funcs = {
|
||||
.update_wm = i9xx_update_wm,
|
||||
};
|
||||
|
||||
static const struct drm_i915_wm_disp_funcs i845_wm_funcs = {
|
||||
static const struct intel_wm_funcs i845_wm_funcs = {
|
||||
.update_wm = i845_update_wm,
|
||||
};
|
||||
|
||||
static const struct drm_i915_wm_disp_funcs nop_funcs = {
|
||||
static const struct intel_wm_funcs nop_funcs = {
|
||||
};
|
||||
|
||||
/* Set up chip specific power management-related functions */
|
||||
@ -8227,27 +8255,27 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
|
||||
/* For FIFO watermark updates */
|
||||
if (DISPLAY_VER(dev_priv) >= 9) {
|
||||
skl_setup_wm_latency(dev_priv);
|
||||
dev_priv->wm_disp = &skl_wm_funcs;
|
||||
dev_priv->display.funcs.wm = &skl_wm_funcs;
|
||||
} else if (HAS_PCH_SPLIT(dev_priv)) {
|
||||
ilk_setup_wm_latency(dev_priv);
|
||||
|
||||
if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->wm.pri_latency[1] &&
|
||||
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
|
||||
(DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
|
||||
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
|
||||
dev_priv->wm_disp = &ilk_wm_funcs;
|
||||
if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->display.wm.pri_latency[1] &&
|
||||
dev_priv->display.wm.spr_latency[1] && dev_priv->display.wm.cur_latency[1]) ||
|
||||
(DISPLAY_VER(dev_priv) != 5 && dev_priv->display.wm.pri_latency[0] &&
|
||||
dev_priv->display.wm.spr_latency[0] && dev_priv->display.wm.cur_latency[0])) {
|
||||
dev_priv->display.funcs.wm = &ilk_wm_funcs;
|
||||
} else {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"Failed to read display plane latency. "
|
||||
"Disable CxSR\n");
|
||||
dev_priv->wm_disp = &nop_funcs;
|
||||
dev_priv->display.funcs.wm = &nop_funcs;
|
||||
}
|
||||
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
||||
vlv_setup_wm_latency(dev_priv);
|
||||
dev_priv->wm_disp = &vlv_wm_funcs;
|
||||
dev_priv->display.funcs.wm = &vlv_wm_funcs;
|
||||
} else if (IS_G4X(dev_priv)) {
|
||||
g4x_setup_wm_latency(dev_priv);
|
||||
dev_priv->wm_disp = &g4x_wm_funcs;
|
||||
dev_priv->display.funcs.wm = &g4x_wm_funcs;
|
||||
} else if (IS_PINEVIEW(dev_priv)) {
|
||||
if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
|
||||
dev_priv->is_ddr3,
|
||||
@ -8261,22 +8289,22 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
|
||||
dev_priv->fsb_freq, dev_priv->mem_freq);
|
||||
/* Disable CxSR and never update its watermark again */
|
||||
intel_set_memory_cxsr(dev_priv, false);
|
||||
dev_priv->wm_disp = &nop_funcs;
|
||||
dev_priv->display.funcs.wm = &nop_funcs;
|
||||
} else
|
||||
dev_priv->wm_disp = &pnv_wm_funcs;
|
||||
dev_priv->display.funcs.wm = &pnv_wm_funcs;
|
||||
} else if (DISPLAY_VER(dev_priv) == 4) {
|
||||
dev_priv->wm_disp = &i965_wm_funcs;
|
||||
dev_priv->display.funcs.wm = &i965_wm_funcs;
|
||||
} else if (DISPLAY_VER(dev_priv) == 3) {
|
||||
dev_priv->wm_disp = &i9xx_wm_funcs;
|
||||
dev_priv->display.funcs.wm = &i9xx_wm_funcs;
|
||||
} else if (DISPLAY_VER(dev_priv) == 2) {
|
||||
if (INTEL_NUM_PIPES(dev_priv) == 1)
|
||||
dev_priv->wm_disp = &i845_wm_funcs;
|
||||
dev_priv->display.funcs.wm = &i845_wm_funcs;
|
||||
else
|
||||
dev_priv->wm_disp = &i9xx_wm_funcs;
|
||||
dev_priv->display.funcs.wm = &i9xx_wm_funcs;
|
||||
} else {
|
||||
drm_err(&dev_priv->drm,
|
||||
"unexpected fall-through in %s\n", __func__);
|
||||
dev_priv->wm_disp = &nop_funcs;
|
||||
dev_priv->display.funcs.wm = &nop_funcs;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -2070,7 +2070,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
|
||||
|
||||
if (GRAPHICS_VER(i915) >= 11) {
|
||||
/* we'll prune the domains of missing engines later */
|
||||
intel_engine_mask_t emask = INTEL_INFO(i915)->platform_engine_mask;
|
||||
intel_engine_mask_t emask = RUNTIME_INFO(i915)->platform_engine_mask;
|
||||
int i;
|
||||
|
||||
uncore->fw_get_funcs = &uncore_get_fallback;
|
||||
|
@ -172,14 +172,14 @@ struct drm_i915_private *mock_gem_device(void)
|
||||
/* Using the global GTT may ask questions about KMS users, so prepare */
|
||||
drm_mode_config_init(&i915->drm);
|
||||
|
||||
mkwrite_device_info(i915)->graphics.ver = -1;
|
||||
RUNTIME_INFO(i915)->graphics.ver = -1;
|
||||
|
||||
mkwrite_device_info(i915)->page_sizes =
|
||||
RUNTIME_INFO(i915)->page_sizes =
|
||||
I915_GTT_PAGE_SIZE_4K |
|
||||
I915_GTT_PAGE_SIZE_64K |
|
||||
I915_GTT_PAGE_SIZE_2M;
|
||||
|
||||
mkwrite_device_info(i915)->memory_regions = REGION_SMEM;
|
||||
RUNTIME_INFO(i915)->memory_regions = REGION_SMEM;
|
||||
intel_memory_regions_hw_probe(i915);
|
||||
|
||||
spin_lock_init(&i915->gpu_error.lock);
|
||||
@ -209,7 +209,7 @@ struct drm_i915_private *mock_gem_device(void)
|
||||
mock_init_ggtt(to_gt(i915));
|
||||
to_gt(i915)->vm = i915_vm_get(&to_gt(i915)->ggtt->vm);
|
||||
|
||||
mkwrite_device_info(i915)->platform_engine_mask = BIT(0);
|
||||
RUNTIME_INFO(i915)->platform_engine_mask = BIT(0);
|
||||
to_gt(i915)->info.engine_mask = BIT(0);
|
||||
|
||||
to_gt(i915)->engine[RCS0] = mock_engine(i915, "mock", RCS0);
|
||||
|
@ -641,6 +641,7 @@
|
||||
INTEL_VGA_DEVICE(0x4682, info), \
|
||||
INTEL_VGA_DEVICE(0x4688, info), \
|
||||
INTEL_VGA_DEVICE(0x468A, info), \
|
||||
INTEL_VGA_DEVICE(0x468B, info), \
|
||||
INTEL_VGA_DEVICE(0x4690, info), \
|
||||
INTEL_VGA_DEVICE(0x4692, info), \
|
||||
INTEL_VGA_DEVICE(0x4693, info)
|
||||
|
Loading…
Reference in New Issue
Block a user