[MIPS] FP affinity: Coding style cleanups
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -109,7 +109,7 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
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read_unlock(&tasklist_lock);
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/* Compute new global allowed CPU set if necessary */
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if( (p->thread.mflags & MF_FPUBOUND)
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if ((p->thread.mflags & MF_FPUBOUND)
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&& cpus_intersects(new_mask, mt_fpu_cpumask)) {
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cpus_and(effective_mask, new_mask, mt_fpu_cpumask);
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retval = set_cpus_allowed(p, effective_mask);
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@ -195,27 +195,31 @@ void mips_mt_regdump(unsigned long mvpctl)
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nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
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ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
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printk("-- per-VPE State --\n");
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for(i = 0; i < nvpe; i++) {
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for(tc = 0; tc < ntc; tc++) {
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for (i = 0; i < nvpe; i++) {
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for (tc = 0; tc < ntc; tc++) {
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settc(tc);
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if((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
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printk(" VPE %d\n", i);
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printk(" VPEControl : %08lx\n", read_vpe_c0_vpecontrol());
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printk(" VPEConf0 : %08lx\n", read_vpe_c0_vpeconf0());
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printk(" VPE%d.Status : %08lx\n",
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i, read_vpe_c0_status());
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printk(" VPE%d.EPC : %08lx\n", i, read_vpe_c0_epc());
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printk(" VPE%d.Cause : %08lx\n", i, read_vpe_c0_cause());
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printk(" VPE%d.Config7 : %08lx\n",
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i, read_vpe_c0_config7());
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break; /* Next VPE */
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if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
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printk(" VPE %d\n", i);
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printk(" VPEControl : %08lx\n",
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read_vpe_c0_vpecontrol());
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printk(" VPEConf0 : %08lx\n",
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read_vpe_c0_vpeconf0());
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printk(" VPE%d.Status : %08lx\n",
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i, read_vpe_c0_status());
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printk(" VPE%d.EPC : %08lx\n",
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i, read_vpe_c0_epc());
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printk(" VPE%d.Cause : %08lx\n",
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i, read_vpe_c0_cause());
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printk(" VPE%d.Config7 : %08lx\n",
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i, read_vpe_c0_config7());
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break; /* Next VPE */
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}
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}
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}
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}
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printk("-- per-TC State --\n");
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for(tc = 0; tc < ntc; tc++) {
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for (tc = 0; tc < ntc; tc++) {
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settc(tc);
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if(read_tc_c0_tcbind() == read_c0_tcbind()) {
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if (read_tc_c0_tcbind() == read_c0_tcbind()) {
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/* Are we dumping ourself? */
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haltval = 0; /* Then we're not halted, and mustn't be */
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tcstatval = flags; /* And pre-dump TCStatus is flags */
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@ -384,7 +388,7 @@ void mips_mt_set_cpuoptions(void)
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mt_fpemul_threshold = fpaff_threshold;
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} else {
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mt_fpemul_threshold =
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(FPUSEFACTOR * (loops_per_jiffy/(500000/HZ))) / HZ;
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(FPUSEFACTOR * (loops_per_jiffy / (500000 / HZ))) / HZ;
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}
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printk("FPU Affinity set after %ld emulations\n",
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mt_fpemul_threshold);
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@ -752,6 +752,33 @@ asmlinkage void do_ri(struct pt_regs *regs)
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force_sig(SIGILL, current);
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}
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/*
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* MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
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* emulated more than some threshold number of instructions, force migration to
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* a "CPU" that has FP support.
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*/
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static void mt_ase_fp_affinity(void)
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{
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#ifdef CONFIG_MIPS_MT_FPAFF
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if (mt_fpemul_threshold > 0 &&
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((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
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/*
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* If there's no FPU present, or if the application has already
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* restricted the allowed set to exclude any CPUs with FPUs,
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* we'll skip the procedure.
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*/
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if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
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cpumask_t tmask;
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cpus_and(tmask, current->thread.user_cpus_allowed,
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mt_fpu_cpumask);
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set_cpus_allowed(current, tmask);
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current->thread.mflags |= MF_FPUBOUND;
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}
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}
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#endif /* CONFIG_MIPS_MT_FPAFF */
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}
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asmlinkage void do_cpu(struct pt_regs *regs)
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{
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unsigned int cpid;
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@ -785,36 +812,8 @@ asmlinkage void do_cpu(struct pt_regs *regs)
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¤t->thread.fpu, 0);
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if (sig)
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force_sig(sig, current);
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#ifdef CONFIG_MIPS_MT_FPAFF
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else {
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/*
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* MIPS MT processors may have fewer FPU contexts
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* than CPU threads. If we've emulated more than
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* some threshold number of instructions, force
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* migration to a "CPU" that has FP support.
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*/
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if(mt_fpemul_threshold > 0
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&& ((current->thread.emulated_fp++
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> mt_fpemul_threshold))) {
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/*
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* If there's no FPU present, or if the
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* application has already restricted
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* the allowed set to exclude any CPUs
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* with FPUs, we'll skip the procedure.
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*/
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if (cpus_intersects(current->cpus_allowed,
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mt_fpu_cpumask)) {
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cpumask_t tmask;
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cpus_and(tmask,
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current->thread.user_cpus_allowed,
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mt_fpu_cpumask);
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set_cpus_allowed(current, tmask);
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current->thread.mflags |= MF_FPUBOUND;
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}
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}
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}
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#endif /* CONFIG_MIPS_MT_FPAFF */
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else
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mt_ase_fp_affinity();
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}
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return;
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@ -44,7 +44,7 @@ struct task_struct;
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* different thread.
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*/
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#define switch_to(prev,next,last) \
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#define __mips_mt_fpaff_switch_to(prev) \
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do { \
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if (cpu_has_fpu && \
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(prev->thread.mflags & MF_FPUBOUND) && \
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@ -52,24 +52,22 @@ do { \
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prev->thread.mflags &= ~MF_FPUBOUND; \
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prev->cpus_allowed = prev->thread.user_cpus_allowed; \
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} \
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if (cpu_has_dsp) \
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__save_dsp(prev); \
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next->thread.emulated_fp = 0; \
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(last) = resume(prev, next, task_thread_info(next)); \
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if (cpu_has_dsp) \
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__restore_dsp(current); \
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} while(0)
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#else
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#define __mips_mt_fpaff_switch_to(prev) do { (prev); } while (0)
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#endif
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#define switch_to(prev,next,last) \
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do { \
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__mips_mt_fpaff_switch_to(prev); \
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if (cpu_has_dsp) \
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__save_dsp(prev); \
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(last) = resume(prev, next, task_thread_info(next)); \
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if (cpu_has_dsp) \
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__restore_dsp(current); \
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} while(0)
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#endif
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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